Chip test control method, controller and storage medium

Abstract

The embodiment of the invention provides a chip testing control method, a controller and a storage medium, and relates to the technical field of chip testing, and the method comprises the steps: carrying out the preset configuration processing of a chip testing device, and obtaining preset configuration information, the preset configuration processing comprises area layout setting, port positioning calibration, chip test device window binding and test function automatic starting parameter configuration; acquiring a current running state of the chip testing device; and under the condition that the current running state is non-running and a to-be-detected chip is obtained, controlling the chip testing device to detect the to-be-detected chip based on the preset configuration information through a preset running instruction to obtain testing information. According to the embodiment of the invention, the chip testing efficiency and the resource utilization rate can be improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a control method, controller and storage medium for chip testing. Background Technology

[0002] In semiconductor manufacturing testing, automated test equipment (ATE) is a core component for ensuring production capacity and efficiency. However, ATE may malfunction and shut down, or face production bottlenecks when market demand surges. The traditional solution is to redevelop the ATE software to adapt it for manual testing, but this process is time-consuming and labor-intensive, and the adaptation work may need to be repeated once the ATE software is updated. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a control method, controller, and storage medium for chip testing, aiming to improve the efficiency and resource utilization of chip testing.

[0004] In a first aspect, embodiments of this application provide a control method for chip testing, applied to a chip testing apparatus, the method comprising: The chip testing device is subjected to a preset configuration process to obtain preset configuration information, wherein the preset configuration process includes regional layout settings, port positioning calibration, chip testing device window binding, and automatic start parameter configuration for testing functions; Obtain the current operating status of the chip testing device; When the current running state is not running and the chip to be tested is acquired, the chip testing device is controlled by a preset running instruction to test the chip to be tested based on the preset configuration information, and test information is obtained.

[0005] According to some embodiments of this application, the preset configuration processing of the chip testing device to obtain preset configuration information includes regional layout settings, port positioning calibration, chip testing device window binding, and automatic start parameter configuration for testing functions. The method includes: The chip testing device is configured with a regional layout to obtain regional layout parameters; The chip testing device is calibrated for port positioning to obtain port positioning data; The chip testing device is bound to a window to obtain a binding identifier. The chip testing device is configured with automatic test function startup parameters to obtain automatic test parameters. Preset configuration information is obtained based on the regional layout parameters, the port positioning data, the binding identifier, and the automatic test parameters.

[0006] According to some embodiments of this application, the chip testing apparatus further includes an image recognition module; the method for performing port positioning calibration on the chip testing apparatus to obtain port positioning data includes: The image recognition module acquires port images of the chip testing device. The position deviation value is obtained by comparing the port image with a preset standard port template; When the position deviation value is greater than the preset deviation value, the port of the chip testing device is automatically compensated to obtain port positioning data.

[0007] According to some embodiments of this application, the chip testing device includes a data acquisition module and a display module; when the current operating state is not running, the chip testing device is controlled by preset operating instructions to test the chip to be tested based on the preset configuration information to obtain test information, the method including: According to the test instructions, the data acquisition module is controlled to test the chip to be tested based on the preset configuration information, so as to obtain the real-time data of the interface table of the chip testing device; The real-time data is reorganized to obtain test information, which is then displayed through the echo module.

[0008] According to some embodiments of this application, the chip testing apparatus further includes a data synchronization module; before reorganizing the real-time data to obtain test information and displaying the test information through the echo module, the apparatus further includes: The data synchronization module is controlled to monitor the interface data update events of the chip testing device in real time. When an interface data update event is detected, collect the updated real-time data.

[0009] According to some embodiments of this application, the echo module includes at least a first test area and a second test area, wherein the first test area and the second test area are each composed of multiple independent test areas; the method of reorganizing the real-time data to obtain test information and displaying the test information through the echo module includes: When the chip under test in the first test area is tested, the real-time data is reorganized to obtain first test information and the first test information is displayed in the first test area. When the chip under test in the second test area is tested, the real-time data is reorganized to obtain second test information and the second test information is displayed in the second test area.

[0010] According to some embodiments of this application, the test information includes at least one of the following: test progress, test status, and test results.

[0011] According to some embodiments of this application, after controlling the chip testing device to test the chip to be tested based on the preset configuration information by a preset running instruction and obtaining test information, the method further includes: The test information is pushed to the user, and the user is reminded to sort and put away the chips that have completed the test. The test information is pushed to the user in at least one of the following ways: voice test information, SMS test information.

[0012] Secondly, embodiments of this application provide a controller, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the chip testing control method described in the first aspect when running the computer program.

[0013] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program for causing a computer to execute the chip testing control method described in the first aspect.

[0014] According to the technical solution of this application embodiment, at least the following beneficial effects are achieved: First, this application embodiment performs preset configuration processing on the chip testing device to obtain preset configuration information, wherein the preset configuration processing includes regional layout setting, port positioning calibration, chip testing device window binding, and automatic start parameter configuration for the test function; it obtains the current running status of the chip testing device; when the current running status is not running and the chip to be tested is obtained, the chip testing device is controlled by preset running instructions to test the chip to be tested based on the preset configuration information to obtain test information. This application embodiment can improve the efficiency of chip testing and the utilization rate of resources.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0017] Figure 1 This is a flowchart of a chip testing control method provided in one embodiment of this application; Figure 2 This is a flowchart of obtaining preset configuration information provided in one embodiment of this application; Figure 3 This is a flowchart illustrating the process of obtaining port location data according to an embodiment of this application; Figure 4 This is a flowchart illustrating the process of obtaining test information according to an embodiment of this application; Figure 5 This is a flowchart illustrating the collection and updating of real-time data provided in one embodiment of this application; Figure 6 This is a flowchart of obtaining test information provided in another embodiment of this application; Figure 7 This is a flowchart illustrating the process of obtaining port location data according to an embodiment of this application; Figure 8 This is an overall flowchart of a chip testing control method provided in one embodiment of this application; Figure 9 This is a schematic diagram of a controller for performing a control method for chip testing according to an embodiment of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0021] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0022] In some cases, automated test equipment (ATE) is a core component in semiconductor manufacturing testing, ensuring both capacity and efficiency. However, ATEs may malfunction and become unusable, or face capacity bottlenecks when market demand surges. The traditional solution is to redevelop the ATE software to adapt it for manual testing, but this process is time-consuming and labor-intensive, and the adaptation work may need to be repeated once the software is updated.

[0023] like Figure 1 As shown, Figure 1 This is a flowchart of a chip testing control method provided in one embodiment of this application; the chip testing control method may include, but is not limited to, steps S110, S120 and S130.

[0024] Step S110: Perform preset configuration processing on the chip testing device to obtain preset configuration information. The preset configuration processing includes area layout setting, port positioning calibration, chip testing device window binding, and automatic start parameter configuration for testing functions. Step S120: Obtain the current operating status of the chip testing device; Step S130: When the current running state is not running and the chip to be tested is obtained, the chip testing device is controlled by the preset running instructions to test the chip to be tested based on the preset configuration information, and the test information is obtained.

[0025] It should be noted that the pre-configuration of the chip testing device is a standardized process that enables the chip testing device to have accurate and stable testing capabilities, eliminates the uncertainty of the initial state of the equipment, and divides and defines the physical operation area and logical function area of ​​the chip testing device to ensure the orderly transmission, positioning, detection and storage of chips during the testing process.

[0026] In one embodiment, the chip testing device window binding achieves a one-to-one correspondence between the hardware modules of the chip testing device and the operation window, ensuring that users can monitor and control the operating status of each hardware unit in real time through a visual interface. First, disconnect all USB-to-TTL cables, then activate the "Start Positioning" button and connect the USB-to-TTL cables in sequence. Each connected cable will display its COM port number sequentially. After all cables are connected and sorted, activating the "Save Positioning" button will automatically generate a COM.txt file saved in the current folder. This file can be loaded and used by the testing device. When selecting the area where test results need to be displayed, the user can select the first position in the test display area, or select all or none at once.

[0027] In one embodiment, the automatic start parameter configuration of the chip testing device triggers the automatic start of the testing function, reducing manual intervention. When the photoelectric sensor of the testing device detects the presence of the chip and continuously detects no signal fluctuations for 300ms, false triggering due to instantaneous signal interference is avoided, ensuring a stable testing environment. Specifically, the current operating status of the chip testing device can be obtained by using a diffuse reflection photoelectric sensor. The detection distance is not specifically limited in this embodiment and can be from 5mm to 50mm. Alternatively, a pressure sensor can be used to detect the current operating status of the chip testing device, thereby detecting whether a chip has been placed and whether the chip has been placed in place.

[0028] It should be noted that the current running status output can be divided into three categories: not running (no test process is being executed), running (test process is in progress), and fault status (a module has encountered an error and cannot be executed).

[0029] In one embodiment, the current operating state is "not running", that is, all hardware modules are in standby ready state, there is no fault alarm, and the communication link is normal; the chip to be detected exists, that is, the photoelectric sensor of the chip detection device detects the chip for 300ms continuously, and the pressure sensor confirms that the chip is placed stably (the pressure value is greater than or equal to the preset pressure value), and the preset pressure value can be set according to the actual weight of the chip.

[0030] Specifically, test information can be stored in a structured format (JSON format) and a PDF test report can be generated, supporting local printing and cloud upload. The test report includes data trend charts (such as comparisons of measured values ​​for the same test item across different chips), facilitating subsequent quality analysis and process optimization.

[0031] It is worth noting that the modular design of the preset configuration processing in this application embodiment enables the device to quickly adapt to the testing requirements of chips with different package types. Only a few configuration parameters need to be modified to complete the device debugging, enhancing the device's versatility and flexibility. Through standardized configuration, real-time status monitoring, and automated test execution, efficient, accurate, and traceable chip testing is achieved.

[0032] like Figure 2 As shown, Figure 2 This is a flowchart of obtaining preset configuration information provided in one embodiment of this application; regarding the preset configuration processing of the chip testing device in the above step S110 to obtain preset configuration information, the preset configuration processing includes regional layout setting, port positioning calibration, chip testing device window binding and test function automatic start parameter configuration, which may include but is not limited to steps S210 to S250.

[0033] Step S210: Set the area layout of the chip testing device to obtain the area layout parameters; Step S220: Perform port positioning calibration on the chip testing device to obtain port positioning data; Step S230: Bind the chip testing device window to the chip testing device to obtain the binding identifier; Step S240: Configure the automatic start parameters for the chip testing device to obtain the automatic test parameters; Step S250: Obtain preset configuration information based on area layout parameters, port location data, binding identifier, and automatic test parameters.

[0034] In one embodiment, configuration software performs cross-validation on four types of parameters. For example, it verifies whether the port coordinates in the port location data are within the probe contact area defined by the area layout parameters, and checks whether the functional module corresponding to the binding identifier is called in the automatic test parameter process, ensuring that there are no logical conflicts between parameters. Simultaneously, a timestamp and version number are added to each type of parameter. The generated preset configuration information includes a configuration header (configuration time, version number, test object model), a parameter body (standardized data of the four types of parameters), and a configuration tail (checksum). The generated area layout parameters, port location data, binding identifier, and automatic test parameters are then merged to remove redundant information and verify data consistency, ultimately generating complete and unified preset configuration information.

[0035] Specifically, the boundary coordinates of the test core area in the verification area layout parameters are consistent with the center coordinates of the test mount in the port positioning data to avoid misalignment due to coordinate reference deviation. If a deviation exists, a calibration reminder is triggered, and the area layout settings are reset.

[0036] like Figure 3 As shown, Figure 3 This is a flowchart of obtaining port positioning data provided in one embodiment of this application; regarding the above step S220 of calibrating the port positioning of the chip testing device to obtain port positioning data, it may include, but is not limited to, steps S310 to S330.

[0037] Step S310: Acquire port images of the chip testing device through the image recognition module; Step S320: Compare and calculate the position deviation value by comparing the port image with the preset standard port template; Step S330: When the position deviation value is greater than the preset deviation value, the port of the chip testing device is automatically compensated to obtain port positioning data.

[0038] In one embodiment, after the chip testing device enters the test-ready state, the data processing module sends an image acquisition trigger signal to the image recognition module. Upon receiving the signal, the image recognition module captures an image of the port to obtain the original image. The original image is then preprocessed, sequentially performing grayscale conversion, noise reduction, and edge enhancement to obtain a clear port image, which is then transmitted to the data processing module. After receiving the port image to be processed, the data processing module first calls a pre-stored preset standard port template. The standard port template is a standard image acquired and calibrated by the same image recognition module during the chip testing device's factory calibration state. The template contains the standard coordinates of the port positioning markers (establishing a two-dimensional rectangular coordinate system with the upper left corner of the image as the origin, and the coordinate unit being pixels) and the standard feature parameters of the port contour (such as contour perimeter, key vertex coordinates, etc.). Subsequently, the data processing module employs an image comparison algorithm based on feature point matching to compare the image to be processed with a standard template: The Harris corner detection algorithm extracts feature points (mainly port positioning markers, pin interface corners, etc.) from both the image to be processed and the standard template, and calculates the SIFT descriptor for each feature point to achieve preliminary feature point matching; the RANSAC algorithm is used to remove outliers (such as pseudo-feature points caused by image noise) during the matching process, retaining matching pairs with an accuracy rate higher than 95%; based on the coordinates of the successfully matched feature points, a coordinate transformation relationship is established between the image to be processed and the standard template, and the transformation matrix (including translation, rotation angle, and scaling factor) is solved using the least squares method; based on the transformation matrix, the offset of the port positioning marker in the image to be processed relative to the corresponding marker in the standard template is calculated, and this offset is the preliminary positional deviation value. When the positional deviation value exceeds a preset deviation value, the data processing module immediately generates an automatic compensation command. The preset deviation value can be adjusted according to actual conditions.

[0039] like Figure 4 As shown, Figure 4 This is a flowchart of obtaining test information provided in one embodiment of this application; regarding the above step S130, when the current running state is not running, the chip testing device is controlled by a preset running instruction to test the chip to be tested based on the preset configuration information to obtain test information, which may include, but is not limited to, steps S410 to S420.

[0040] Step S410: Control the data acquisition module to test the chip to be tested based on the preset configuration information according to the test command, and obtain the real-time data of the interface table of the chip testing device. Step S420: Reorganize the real-time data to obtain test information and display the test information through the echo module.

[0041] In one embodiment, the test instructions sent by the instruction generation module are transmitted to the data processing module in JSON format. The data processing module extracts the unique identifier and test items of the chip under test by parsing the instructions, and performs tests on the chip under test based on the preset configuration information to obtain real-time data of the interface table of the chip testing device. After receiving the real-time data of the table, the data processing module first removes redundant data, deleting duplicate "chip serial number" fields (only retained in the first data entry) and null data (such as empty fields corresponding to incomplete test items); secondly, it performs validity verification on the data by comparing the original data values ​​with the outlier threshold in the preset configuration information, removing obviously abnormal data points, and marking the collection time of abnormal data; thirdly, it performs data statistical optimization by statistically analyzing the continuously collected data of the same test item, calculating characteristic values ​​such as average and standard deviation, and reorganizing the preprocessed data to form structured test information.

[0042] like Figure 5 As shown, Figure 5 This is a flowchart of the acquisition and update of real-time data provided in one embodiment of this application; before the above step S420 reorganizes the real-time data to obtain test information and displays the test information through the echo module, it may include, but is not limited to, steps S510 to S520.

[0043] Step S510: Control the data synchronization module to monitor the interface data update events of the chip testing device in real time; Step S520: When an interface data update event is detected, collect the updated real-time data.

[0044] In one embodiment, the data synchronization module establishes an initial connection with the chip testing device through a communication interface unit, negotiates a data transmission protocol (such as determining the data frame format, baud rate, and verification method), and the chip testing device sends the baseline format information of the interface data (including data field type, field length, initial value, and data update flag definition) to the data synchronization module. The monitoring control unit starts a data update event monitoring algorithm, performs real-time parsing of the data stream output by the chip testing device interface based on the negotiated transmission protocol, and extracts the data update flag (including the value change flag of a certain field and the update flag byte in the data frame header) from the data stream. The monitoring control unit can set the monitoring frequency to 10kHz, that is, it checks the data update flag every 100μs, and compares the field values ​​of the data stream in real time. The monitoring frequency is not specifically limited in this embodiment and can be adjusted according to the actual situation.

[0045] It should be noted that when the data update flag changes from "0" (no update) to "1" (update), an interface data update event is determined to exist; when the difference between the value of a certain data field and the value of the last collected data exceeds a preset threshold (the threshold can be customized according to the data type, such as ±0.01V for voltage parameters and ±1mA for current parameters), an interface data update event is determined to exist; when a new data frame appears in the data stream (the frame header identifier is consistent with the reference format, and the similarity between the data in the frame and the historical frame data is less than 95%), an interface data update event is determined to exist.

[0046] It should be noted that if no interface data update event is detected, the monitoring control unit continues to monitor and sends a connection status detection signal to the chip testing device at preset time intervals to ensure that the communication link is unobstructed. If no feedback signal is received for three consecutive times, an alarm mechanism is triggered (such as lighting up a red indicator light or sending an alarm SMS to the user terminal).

[0047] like Figure 6 As shown, Figure 6 This is a flowchart of obtaining test information provided in another embodiment of this application; the echo module includes at least a first test area and a second test area, and the first test area and the second test area are each composed of multiple independent test areas; regarding the above step S420 of reorganizing the real-time data to obtain test information and displaying the test information through the echo module, it may include, but is not limited to, steps S610 to S620.

[0048] Step S610: While testing the chip to be tested in the first test area, the real-time data is reorganized to obtain the first test information and the first test information is displayed in the first test area. Step S620: While testing the chip under test in the second test area, the real-time data is reorganized to obtain the second test information and displayed in the second test area.

[0049] It should be noted that the number of independent test areas in the first and second test areas can be set according to actual testing needs. A 2x16 or 3x8 layout can be quickly set, or a user-defined layout can be used. The division of the first and second test areas can be done by columns, rows, or a user-defined layout.

[0050] In one embodiment, the test information includes at least one of the following: test progress, test status, and test results.

[0051] like Figure 7 As shown, Figure 7This is a flowchart of obtaining port positioning data provided in one embodiment of this application; regarding the above step S130, after controlling the chip testing device to test the chip to be tested based on the preset configuration information by the preset running instructions and obtaining the test information, it may include, but is not limited to, step S710.

[0052] Step S710: Push test information to the user and remind the user to sort and put away the chips that have been tested. The test information is pushed to the user in at least one of the following ways: voice test information, SMS test information.

[0053] It should be noted that when the chip testing device is controlled by the preset running instructions to test the chip to be tested based on the preset configuration information, and the test information is obtained, the test information can be pushed to the user via voice or SMS, and the user is reminded to sort and put away the tested chips.

[0054] like Figure 8 As shown, Figure 8 This is an overall flowchart of a chip testing control method provided in one embodiment of this application.

[0055] Step S810: Configure the area layout; Step S820: Perform port positioning calibration; Step S830: Bind the chip testing device window; Step S840: Configure the automatic startup parameters for the test function; Step S850: Save settings; Step S860: Determine whether the chip testing device is running. If yes, proceed to step S870; otherwise, proceed to step S880. Step S870: No operation performed. Step S880: The control chip testing device performs the test; Step S890: Obtain test information.

[0056] In one embodiment, in the test preparation and execution process of the chip testing device, the area layout is first set, and then port positioning calibration is performed to ensure the test connection accuracy. Then, the chip testing device window binding operation is performed, and then the test function automatic start parameters are configured and all the above settings are saved. After that, it is determined whether the chip testing device is currently running. If it is running, no additional operation is performed. If it is not running, the chip testing device is controlled to start the detection process and finally obtain the corresponding chip test information.

[0057] Based on the control methods for chip testing described in the above embodiments, the following presents various embodiments of the controller, computer-readable storage medium, and computer program product of this application.

[0058] like Figure 9 As shown, Figure 9 This is a schematic diagram of a controller for performing a chip testing control method according to an embodiment of this application. The controller 900 implemented in this application includes: a processor 910, a memory 920, and a computer program stored in the memory 920 and executable on the processor 910, wherein... Figure 9 The example uses a processor 910 and a memory 920.

[0059] The processor 910 and the memory 920 can be connected via a bus or other means. Figure 9 Taking the example of a connection between China and Israel via a bus.

[0060] Memory 920, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 920 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 920 may optionally include remotely located memories 920 relative to processor 910, which can be connected to controller 900 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0061] Those skilled in the art will understand that Figure 9 The device structure shown does not constitute a limitation on the controller 900 and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0062] exist Figure 9 In the controller 900 shown, the processor 910 can be used to call the fast communication program stored in the memory 920, thereby implementing the chip testing control method described above. Specifically, the non-transitory software program and instructions required to implement the chip testing control method of the above embodiment are stored in the memory 920. When executed by the processor 910, the chip testing control method of the above embodiment is executed.

[0063] It is worth noting that, since the controller 900 of this application embodiment can execute the chip testing control method of any of the above embodiments, the specific implementation method and technical effects of the controller 900 of this application embodiment can be referred to the specific implementation method and technical effects of the chip testing control method of any of the above embodiments.

[0064] Furthermore, one embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for performing the aforementioned chip testing control method. Exemplarily, the above-described control method is executed... Figures 1 to 8 The methods and steps in the text.

[0065] It is worth noting that, since the computer-readable storage medium of this application embodiment is capable of executing the chip testing control method of any of the above embodiments, the specific implementation method and technical effects of the computer-readable storage medium of this application embodiment can be referred to the specific implementation method and technical effects of the chip testing control method of any of the above embodiments.

[0066] Furthermore, one embodiment of this application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the aforementioned chip testing control method. Exemplarily, the above-described method is executed... Figures 1 to 8 The methods and steps in the text.

[0067] It is worth noting that, since the computer program product of this application embodiment can execute the chip testing control method of any of the above embodiments, the specific implementation method and technical effect of the computer program product of this application embodiment can refer to the specific implementation method and technical effect of the chip testing control method of any of the above embodiments.

[0068] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0069] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A control method for chip testing, characterized in that, Applied to a chip testing apparatus, the method includes: The chip testing device is subjected to a preset configuration process to obtain preset configuration information, wherein the preset configuration process includes regional layout settings, port positioning calibration, chip testing device window binding, and automatic start parameter configuration for testing functions; Obtain the current operating status of the chip testing device; When the current running state is not running and the chip to be tested is acquired, the chip testing device is controlled by a preset running instruction to test the chip to be tested based on the preset configuration information, and test information is obtained.

2. The method according to claim 1, characterized in that, The chip testing device is subjected to a preset configuration process to obtain preset configuration information. This preset configuration process includes setting the area layout, calibrating port positioning, binding the chip testing device window, and configuring automatic startup parameters for the testing function. The method includes: The chip testing device is configured with a regional layout to obtain regional layout parameters; The chip testing device is calibrated for port positioning to obtain port positioning data; The chip testing device is bound to a window to obtain a binding identifier. The chip testing device is configured with automatic test function startup parameters to obtain automatic test parameters. Preset configuration information is obtained based on the regional layout parameters, the port positioning data, the binding identifier, and the automatic test parameters.

3. The method according to claim 1, characterized in that, The chip testing device further includes an image recognition module; the method for calibrating the port positioning of the chip testing device to obtain port positioning data includes: The image recognition module acquires port images of the chip testing device. The position deviation value is obtained by comparing the port image with a preset standard port template; When the position deviation value is greater than the preset deviation value, the port of the chip testing device is automatically compensated to obtain port positioning data.

4. The method according to claim 1, characterized in that, The chip testing device includes a data acquisition module and a display module; when the current operating state is not running, the chip testing device is controlled by preset operating instructions to test the chip to be tested based on the preset configuration information to obtain test information. The method includes: According to the test instructions, the data acquisition module is controlled to test the chip to be tested based on the preset configuration information, so as to obtain the real-time data of the interface table of the chip testing device; The real-time data is reorganized to obtain test information, which is then displayed through the echo module.

5. The method according to claim 4, characterized in that, The chip testing device further includes a data synchronization module; before reorganizing the real-time data to obtain test information and displaying the test information through the echo module, the device further includes: The data synchronization module is controlled to monitor the interface data update events of the chip testing device in real time. When an interface data update event is detected, collect the updated real-time data.

6. The method according to claim 4, characterized in that, The echo module includes at least a first test area and a second test area, wherein the first test area and the second test area are each composed of multiple independent test areas; the method of reorganizing the real-time data to obtain test information and displaying the test information through the echo module includes: When the chip under test in the first test area is tested, the real-time data is reorganized to obtain first test information and the first test information is displayed in the first test area. When the chip under test in the second test area is tested, the real-time data is reorganized to obtain second test information and the second test information is displayed in the second test area.

7. The method according to claim 1, characterized in that, The test information includes at least one of the following: test progress, test status, and test results.

8. The method according to claim 1, characterized in that, After controlling the chip testing device to test the chip to be tested based on the preset configuration information through preset operating instructions and obtaining test information, the method further includes: The test information is pushed to the user, and the user is reminded to sort and put away the chips that have completed the test. The test information is pushed to the user in at least one of the following ways: voice test information, SMS test information.

9. A controller, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, performs the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for causing a computer to perform the method as described in any one of claims 1 to 8.

Images