Voltage reference evaluation board with electromagnetic compatibility and method

Abstract

The invention discloses a voltage reference evaluation board and method with electromagnetic compatibility, the evaluation board comprises a core board and a bottom board which are split, the core board is integrated with a high-speed digital circuit, and the bottom board is provided with high-precision analog chips in a centralized manner; an inter-board ground loop is formed between the core board and the bottom board through a connector which vertically penetrates through the core board and the bottom board; the bottom plate comprises a four-layer plate laminated structure, namely a top signal layer, a ground layer, a power supply layer and a bottom signal layer in sequence from top to bottom; the bottom signal layer is provided with a reference voltage source, an ADC, an operational amplifier, a voltage dividing module and a test connecting hole of the reference voltage source to be tested, which are far away from the main control area of the core board. An annular heat insulation groove is formed in the periphery of the reference voltage source to form an air heat insulation layer, high-density grounding via hole arrays are arranged on the two sides of the heat insulation groove, and bridging capacitors are laid on the high-density grounding via hole arrays in a cross-groove mode. The electromagnetic compatibility of the voltage reference evaluation board can be improved, and thermal interference can be suppressed.

Description

Technical Field

[0001] This invention relates to the field of circuit electronics, and more particularly to an electromagnetic compatibility design method and a voltage reference evaluation board for a voltage reference evaluation circuit. Background Technology

[0002] A voltage reference evaluation board is an engineering development platform specifically designed for testing, verifying, and optimizing the performance of voltage reference chips. Its core value lies in providing a quantifiable and reproducible reference voltage verification environment for high-precision analog systems (such as ADC data converters, sensor interfaces, and voltage reference chips). These evaluation boards integrate the reference voltage source and its associated circuitry, and provide standardized test interfaces, enabling engineers to comprehensively evaluate the key performance parameters of the reference chip under real-world application conditions, thereby accelerating the system design process.

[0003] The output accuracy and stability of voltage reference evaluation boards are highly susceptible to electromagnetic interference (EMI) and thermal interference. However, the increasingly complex electromagnetic environment poses a severe challenge to high-precision analog circuits, especially voltage reference circuits. Electromagnetic compatibility (EMC) issues have become a key bottleneck affecting the reliability of voltage reference evaluation board test results, measurement accuracy, and even the board's own functional normality. Furthermore, eliminating the conflict between thermal interference and EMC is also crucial. Summary of the Invention

[0004] This invention focuses on the systematic design challenges of voltage reference evaluation boards in complex electromagnetic environments, and proposes a collaborative architecture for electromagnetic compatibility and thermal management. The core objective is to solve the coupling effect of thermal noise and electromagnetic interference through multi-dimensional optimization: while suppressing the temperature drift of the reference voltage source, electromagnetic compatibility is ensured, thereby improving the anti-interference capability and long-term reliability in high-precision measurement scenarios.

[0005] The technical solution adopted in this invention is: A voltage reference evaluation board with electromagnetic compatibility is provided, comprising a split core board and a base board, wherein the core board integrates high-speed digital circuits and the base board centrally arranges high-precision analog chips; and the core board and the base board form an in-board ground loop through a vertically penetrating connector. The base plate consists of a four-layer stacked structure, from top to bottom: top signal layer, ground layer, power layer, and bottom signal layer. The bottom signal layer has a reference voltage source, ADC, operational amplifier, voltage divider module, and test terminals for the reference voltage source under test, which are located away from the main control area of ​​the core board. Among them, the reference voltage source is surrounded by annular heat insulation grooves to form an air heat insulation layer, and a high-density grounding via array is deployed on both sides of the heat insulation groove, with bridging capacitors laid across the grooves.

[0006] Following the above technical solution, the test connection is specifically a four-pin socket.

[0007] Following the above technical solution, the output terminal of the reference voltage source under test is equipped with a decoupling capacitor and an RC filter circuit.

[0008] According to the above technical solution, both the input and output terminals of the operational amplifier are equipped with capacitor banks to suppress common-mode noise conduction.

[0009] Following the above technical solution, the bridging capacitors laid across the trench are ceramic bridging capacitors with a capacitance value of 1–10nF.

[0010] Following the above technical solution, the spacing of the high-density grounding via array is ≤λ / 10.

[0011] According to the above technical solution, the ADC is located between the core board and the reference voltage source, and the reference input terminal of the ADC is equipped with a large-capacity capacitor to stabilize the low-frequency reference potential. The large-capacity capacitor in the analog input channel suppresses the intermediate frequency ripple. The input and output terminals of the ADC are respectively equipped with large and small capacitor groups, and the large and small capacitor groups adopt a star grounding topology.

[0012] This invention also provides an electromagnetic compatibility design method for a voltage reference evaluation board, comprising the following steps: The system is designed with separate core board and baseboard. The core board integrates high-speed digital circuits, while the baseboard centrally houses high-precision analog chips. The core board and baseboard are connected by a vertically penetrating connector to form an in-board ground loop. The baseboard is designed as a four-layer stacked structure, consisting of a top signal layer, a ground layer, a power layer, and a bottom signal layer from top to bottom. The bottom signal layer has test holes for a reference voltage source, ADC, operational amplifier, voltage divider module, and voltage source under test, which are located away from the main control area of ​​the core board. An annular heat insulation groove is opened around the reference voltage source to form an air heat insulation layer, and a high-density grounding via array is deployed on both sides of the heat insulation groove, with bridging capacitors laid across the groove.

[0013] Following the above technical solution, in the multilayer PCB routing design of the voltage reference evaluation board, the interconnection traces between each IC follow the principles of electromagnetic compatibility and signal integrity.

[0014] Following the above technical solution, in the interconnection architecture between the core board and the baseboard, the connector adopts a copper layer covering structure, and the connector is grounded at both ends: the connector passes through the stacked structure of the core board and the baseboard, the upper end of the connector forms a low impedance connection with the ground plane of the core board, with an impedance ≤20mΩ, and the lower end is connected to the ground layer of the baseboard using the same process to construct a through grounding path.

[0015] The beneficial effects of this invention are as follows: To improve the electromagnetic compatibility of the voltage reference evaluation board and suppress thermal interference, this invention adopts a collaborative architecture of electromagnetic compatibility and thermal management. In terms of circuit layout, a core board-baseboard split architecture is adopted to achieve physical isolation between digital and analog areas. In terms of grounding loop, a complete ground layer and power layer are laid. The core board and baseboard are connected by connectors, and the connector connection post grounds the baseboard and core board ground layers. In addition, the baseboard is designed with an active thermal isolation structure for heat-sensitive areas, effectively isolating temperature effects while protecting electromagnetic compatibility.

[0016] Furthermore, this invention, through an electromagnetic compatibility-thermal management collaborative architecture, achieves full-domain electromagnetic compatibility and implements multi-gradient thermal insulation protection for thermally sensitive areas such as the reference voltage source and ADC. It also innovatively adopts an electromagnetic compensation topology to offset the ground plane fracture effect caused by the thermal insulation structure, providing a reliable verification platform for high-precision analog circuits.

[0017] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the main layout of the voltage reference evaluation board according to an embodiment of the present invention; Figure 2 This is a schematic diagram of an annular heat insulation groove formed around the reference voltage source in an embodiment of the present invention; Figure 3 This is a schematic diagram of the external via array of the heat insulation groove surrounding the reference voltage source in an embodiment of the present invention; Figure 4 This is a schematic diagram of an annular heat insulation groove formed around the reference voltage source to be measured in an embodiment of the present invention; Figure 5 This is a schematic diagram of the external via array of the heat insulation groove of the reference voltage source to be tested according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the inter-board connection between the core board and the base plate in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] In this invention, it should also be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0023] Furthermore, it should be noted that the features of the various embodiments of the present invention can be combined or integrated in whole or in part, and as those skilled in the art will understand, they can interact and operate in different ways. Each embodiment can be implemented independently of each other or in association with one another.

[0024] The electromagnetic compatibility design method for the voltage reference evaluation board according to an embodiment of the present invention includes the following steps: The system is designed with separate core board and baseboard. The core board integrates high-speed digital circuits, while the baseboard centrally houses high-precision analog chips. The core board and baseboard are connected by a vertically penetrating connector to form an in-board ground loop. The baseboard is designed as a four-layer stacked structure, consisting of a top signal layer, a ground layer, a power layer, and a bottom signal layer from top to bottom. The bottom signal layer has test holes for a reference voltage source, ADC, operational amplifier, voltage divider module, and voltage source under test, which are located away from the main control area of ​​the core board. An annular heat insulation groove can be opened around the reference voltage source to form an air heat insulation layer, and a high-density grounding via array can be deployed on both sides of the heat insulation groove, with bridging capacitors laid across the groove.

[0025] In the multilayer PCB routing design of the voltage reference evaluation board, the interconnection traces between each IC follow the principles of electromagnetic compatibility and signal integrity.

[0026] In the interconnect architecture between the core board and the baseboard, the connector adopts a copper layer covering structure and is grounded at both ends: the connector passes through the stacked structure of the core board and the baseboard, the upper end of the connector forms a low impedance connection with the ground plane of the core board with an impedance ≤20mΩ, and the lower end is connected to the ground layer of the baseboard using the same process to build a through grounding path.

[0027] The voltage reference evaluation board designed according to the electromagnetic compatibility design method of the above voltage reference evaluation board, such as... Figure 1 As shown, the electromagnetic compatibility (EMC) voltage reference evaluation board of this invention includes a split core board and a baseboard. The core board integrates high-speed digital circuits, while the baseboard centrally houses high-precision analog chips. Physical isolation enables synergistic optimization of EMC between digital and analog circuits, blocking the conduction and radiation interference of digital noise to sensitive analog signals at the source, thus conforming to the interference source isolation principle in EMC design. Furthermore, a vertically penetrating connector forms an in-board ground loop between the core board and the baseboard, significantly shortening the high-speed signal transmission path, minimizing the signal return loop area, effectively suppressing high-frequency radiated emissions (>1GHz band), and directly reducing the risk of electromagnetic interference (EMI).

[0028] The base plate comprises a four-layer stacked structure, consisting of a top signal layer, a ground layer, a power layer, and a bottom signal layer from top to bottom. The bottom signal layer houses a reference voltage source, ADC, operational amplifier, voltage divider module, and test ports for the voltage source under test, all located away from the core board's main control area. An annular heat-insulating groove forms an air insulation layer around the reference voltage source, and a high-density array of grounding vias (with a spacing ≤ λ / 10) is deployed on both sides of the groove. Bridging capacitors, such as ceramic bridging capacitors (1–10nF), are laid across the grooves to maintain high-frequency ground loop continuity and suppress electromagnetic leakage from the groove gaps. This design ensures both thermal isolation performance and control of electromagnetic leakage from the groove gaps, balancing thermal insulation and shielding integrity.

[0029] Specifically, the test connector can be a four-pin connector, facilitating the insertion and removal of the power supply under test. Furthermore, the test connector supports high-precision measurement modes, including single-channel testing or dual-channel parallel connection.

[0030] Furthermore, the output of the reference voltage source under test is equipped with a decoupling capacitor and an RC filter circuit. This allows for the configuration of a multi-stage electromagnetic noise suppression network at the output of the reference voltage source to eliminate noise interference. For example, a ceramic decoupling capacitor (100nF) can be used to filter out high-frequency noise ≥100MHz, and an RC filter network (R=5Ω, C=1μF) can attenuate low-to-medium frequency conducted interference.

[0031] The operational amplifier has capacitor banks at both its input and output terminals to suppress common-mode noise conduction. For example, 0.047μF and 4.7μF capacitor banks can be deployed at the input / output terminals of the operational amplifier, following the near-end layout principle to minimize lead inductance and suppress common-mode noise conduction.

[0032] In one embodiment of the present invention, the ADC is located between the core board and the reference voltage source, and the reference input terminal of the ADC is equipped with a large-capacity capacitor (e.g., 47μF) to stabilize the low-frequency reference potential, and the analog input channel is equipped with a large-capacity capacitor (e.g., 10μF) to suppress intermediate frequency ripple; the input and output terminals of the ADC are respectively provided with large and small capacitor groups, and the large and small capacitor groups adopt a star grounding topology.

[0033] In a preferred embodiment of the present invention, in order to achieve better electromagnetic compatibility performance, the reference voltage evaluation board is designed around four dimensions: circuit layout design, grounding loop design, wiring design, and integrated heat insulation and shielding design. The detailed scheme is as follows.

[0034] 1) Circuit layout like Figure 1 As shown, this invention adopts a core board-baseboard split architecture, achieving electromagnetic compatibility (EMC) optimization between digital and analog circuits through physical isolation. The core board integrates high-speed digital circuits (the main control SoC), while the baseboard centrally houses high-precision analog chips, including an LDO linear regulator, a reference voltage source, a voltage divider module (which can use voltage divider resistors), an operational amplifier, and an ADC. This architecture achieves physical isolation between the digital and analog areas, blocking the conduction and radiation interference of digital noise to sensitive analog signals at the source, conforming to the interference source isolation principle in EMC design. The core board can be vertically mounted on the baseboard via high-density board-to-board connectors, significantly shortening the high-speed signal transmission path, minimizing the signal return loop area, effectively suppressing high-frequency radiated emissions (>1GHz band), and directly reducing the risk of electromagnetic interference (EMI).

[0035] In the baseboard design, the reference voltage source under test adopts a four-pin mounting structure, supporting high-precision measurement modes of single-channel detection or dual-channel parallel connection. The output of the reference voltage source under test is equipped with a multi-stage electromagnetic noise suppression network: a ceramic decoupling capacitor (100nF) filters out high-frequency noise ≥100MHz, and an RC filter network (R=5Ω, C=1μF) attenuates low-to-medium frequency conducted interference. High-precision resistors are used in the voltage divider module to ensure signal integrity, and further block high-frequency crosstalk before feeding into the ADC via a buffer amplifier. Key sensitive components (reference source, ADC) are placed on the bottom surface of the baseboard in an electromagnetically quiet zone away from the core board to avoid radiated coupling of switching noise from digital circuits. 0.047μF and 4.7μF capacitor banks are deployed at the input / output terminals of the operational amplifier, following a near-end layout principle to minimize lead inductance and suppress common-mode noise conduction.

[0036] The high-precision ADC employs an electromagnetic isolation layout strategy, positioned between the core board and the reference source to avoid the superposition effect of digital noise radiation and thermal conduction interference. The ADC requires both analog and digital power supplies. A capacitor at the digital power supply terminal filters high-frequency noise, and a 0.1μF ceramic capacitor at the digital power supply terminal can filter high-frequency noise ≥10MHz, forming a full-band electromagnetic filtering system. The ADC requires a voltage reference, which can be an ADR1001. A 47μF capacitor can be configured at the ADC's voltage reference input to stabilize the low-frequency reference potential, and a 10μF capacitor in the analog input channel suppresses intermediate-frequency ripple. Figure 2 As shown, an annular slotted structure is set around the reference voltage source to block the heat conduction path, while... Figure 3 As shown, the continuity of the high-frequency ground plane is maintained by an array of grounding vias on both sides of the slot, preventing electromagnetic leakage caused by the slot antenna effect. The input and output terminals of the ADC are equipped with 0.1μF and 1μF capacitor banks respectively, using a star grounding topology to eliminate ground bounce noise and ensure the purity of the reference voltage. Similarly, as... Figure 4 As shown, an annular heat insulation groove can also be opened around the reference voltage source to be tested to form an air heat insulation layer.

[0037] The power module uses an LDO linear regulator to convert the input voltage into the low-noise operating voltage required by each chip. The LDO module is located away from the digital core board and analog sensitive circuits, physically blocking the transmission path of digital noise and avoiding interference from the power module's heat radiation to the analog sensitive circuits. A 4.7μF ceramic capacitor (to suppress low-frequency ripple) and a 0.1μF ceramic capacitor (to absorb high-frequency noise ≥1MHz) are connected in parallel on the input side to form a full-band filtering network. On the output side, a combination of a 10μF capacitor (to optimize load transient response) and a 0.1μF ceramic capacitor (to attenuate ultra-high-frequency interference) is used, balancing mid-frequency load stability and wideband noise suppression. A 0.47μF ceramic capacitor is configured at the voltage setting terminal to stabilize the feedback loop reference voltage and suppress thermal noise disturbances from the configuration resistor to within ±0.05%. All capacitor grounding terminals are converged to a single grounding point in a star topology to eliminate ground bounce noise, and lead inductance is reduced through short-path copper plating.

[0038] The power module achieves deep electromagnetic interference suppression through a multi-stage LDO cascade architecture. The LDO modules are located away from sensitive digital and analog areas, physically blocking conducted interference paths. The input side features a combination of 4.7μF and 0.1μF ceramic capacitors to suppress low-frequency ripple and high-frequency noise, respectively. The output side uses a network of 10μF and 0.1μF capacitors to optimize transient response and attenuate ultra-wideband interference. A 0.47μF capacitor stabilizes the feedback loop at the voltage setting terminal, and combined with a low-impedance copper-plated grounding design, achieves a PSRR ≥ 70dB@100kHz and an output voltage ripple ≤ 10μVpp, meeting the electromagnetic compatibility requirements of precision measurement equipment.

[0039] This design incorporates electromagnetic compatibility into the system architecture, circuit layout, and device-level design through four measures: spatial isolation, frequency band coverage filtering, ground plane optimization, and thermal-electrical synergistic shielding.

[0040] 2) Grounding circuit design This design deploys complete power and ground planes on both the core board and the baseboard to create a low-impedance return path. The baseboard adopts a four-layer stack-up structure (top signal layer → ground plane → power layer → bottom signal layer), ensuring that the signal layer and the reference ground plane are closely adjacent, shortening the return path and minimizing the loop area, effectively suppressing high-frequency radiated emissions (>1GHz band), and directly reducing the risk of electromagnetic interference (EMI). Direct grounding reinforcement is implemented on the bottom of the IC, with a via array set in the device projection area. At least two metallized vias are used to connect to the ground plane nearby, significantly reducing ground inductance and thermal resistance, while meeting both EMI suppression and heat dissipation requirements. At the same time, the ground line width is thickened to 20mil, and a closed-loop ground plane design is adopted to avoid return path breaks caused by comb-shaped traces.

[0041] In the interconnect architecture between the core board and the baseboard, the connector mounting posts adopt a copper-clad structure to achieve double-ended grounding: the mounting posts penetrate the core board and the baseboard stack, with their upper ends forming a low-impedance connection (impedance ≤20mΩ) with the grounding plane of the core board, and their lower ends connecting to the grounding layer of the baseboard using the same process, constructing a through-grounding path, such as... Figure 6 As shown. In terms of mechanical reinforcement, the structure improves the peel strength of the fixing posts by thickening the copper layer (copper thickness ≥ 2oz), increasing the peel force by 60% compared to conventional designs. In terms of electrical performance, a low-resistance grounding path is formed in the vertical direction, controlling the inductance of the in-circuit grounding loop between boards to ≤ 3nH, effectively suppressing high-frequency noise caused by grounding potential difference (ground bounce voltage ≤ 10mV@1GHz).

[0042] 3) Cable routing design In multilayer PCB routing design, the interconnection traces between ICs must adhere to electromagnetic compatibility and signal integrity principles. This design ensures that power supply voltage lines have sufficient width to meet current carrying requirements and reduce DC resistance; the width of other lines is controlled within a reasonable range according to IC requirements. Sensitive lines such as CLK, reset, and interrupt circuits are grounded. All traces avoid 90° bends and should be routed as short as possible. To prevent crosstalk caused by parallel signal traces on adjacent layers, traces on adjacent layers cross perpendicularly, avoiding parallel routing. The number and length of leads and connections between components are minimized and shortened. Synchronous high-speed signal lines are matched to the same length, with a length tolerance controlled within ±50mil; differential signal lines are routed with differential matching to the same length, with a length tolerance controlled within ±5mil. 4) Integrated heat insulation and shielding design In the design of the reference voltage source evaluation board, the synergistic optimization of thermal management and electromagnetic compatibility constitutes a core challenge. Since the reference voltage source and its associated critical components such as the ADC and operational amplifiers are extremely sensitive to temperature fluctuations, thermal insulation design is crucial to ensuring their long-term stability. However, traditional thermal insulation solutions (such as creating annular thermal slots to form an air thermal barrier) disrupt ground plane continuity, especially in the GHz high-frequency band (such as 5G / millimeter wave), where slot lengths approaching λ / 4 wavelength can easily induce slot antenna effects, leading to a sharp increase in the risk of electromagnetic radiation leakage. To resolve this contradiction, the design employs a triple physical isolation strategy: Partitioned layout of heat-sensitive devices: The reference chip, ADC and operational amplifier are arranged in a dedicated area on the bottom layer of the baseboard, maintaining a physical distance from the core board digital system (such as the main control SoC), blocking the heat radiation conduction path of the digital circuit, and reducing thermal interference from the source; Enhanced electromagnetic compatibility of the thermal insulation groove: While forming an air insulation layer by creating an annular thermal insulation groove around the reference voltage source, a high-density array of grounding vias (spacing ≤ λ / 10) is deployed on both sides of the groove, and ceramic bridging capacitors (1–10nF) are laid across the groove. Capacitive coupling maintains the continuity of the high-frequency ground loop and suppresses electromagnetic leakage from the groove. This design ensures both thermal barrier performance and electromagnetic leakage control, balancing thermal insulation and shielding integrity. Thermal-electric synergistic isolation barrier: A via array isolation strip is set around the board-to-board connector between the core board and the base plate. The difference in thermal conductivity of the materials is used to block the transfer of heat from the core board to the base plate. At the same time, the dense via array is equivalent to a waveguide cutoff structure, which attenuates high-frequency noise of ≥1GHz by more than 20dB and suppresses the propagation of digital noise to the analog sensitive area.

[0043] These three measures, through structural isolation, control of material dielectric properties, and optimization of electromagnetic field topology, achieve synergistic enhancement of thermal management and electromagnetic shielding: the thermal insulation design does not sacrifice EMC, but instead transforms the thermal isolation structure into an electromagnetic compatibility enhancement carrier through cross-scale integration.

[0044] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0045] The order of the steps in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0046] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A voltage reference evaluation board with electromagnetic compatibility, characterized in that, It includes a separate core board and a baseboard, wherein the core board integrates high-speed digital circuits and the baseboard centrally arranges high-precision analog chips; and the core board and the baseboard form an in-board ground loop through a vertically penetrating connector. The base plate consists of a four-layer stacked structure, from top to bottom: top signal layer, ground layer, power layer, and bottom signal layer. The bottom signal layer has a reference voltage source, ADC, operational amplifier, voltage divider module, and test terminals for the reference voltage source under test, which are located away from the main control area of ​​the core board. Among them, the reference voltage source is surrounded by annular heat insulation grooves to form an air heat insulation layer, and a high-density grounding via array is deployed on both sides of the heat insulation groove, with bridging capacitors laid across the grooves.

2. The voltage reference evaluation board with electromagnetic compatibility according to claim 1, characterized in that, The test connection is specifically a four-pin connector.

3. The voltage reference evaluation board with electromagnetic compatibility according to claim 1, characterized in that, The output of the reference voltage source under test is equipped with a decoupling capacitor and an RC filter circuit.

4. The voltage reference evaluation board with electromagnetic compatibility according to claim 1, characterized in that, The operational amplifier has capacitor banks at both its input and output terminals to suppress common-mode noise conduction.

5. The voltage reference evaluation board with electromagnetic compatibility according to claim 1, characterized in that, The bridging capacitors laid across the trenches are ceramic bridging capacitors with a capacitance value of 1–10 nF.

6. The voltage reference evaluation board with electromagnetic compatibility according to claim 1, characterized in that, The spacing of the high-density grounding via array is ≤λ / 10.

7. The voltage reference evaluation board with electromagnetic compatibility according to claim 1, characterized in that, The ADC is located between the core board and the reference voltage source, and the reference input terminal of the ADC is equipped with a large-capacity capacitor to stabilize the low-frequency reference potential. The analog input channel is equipped with a large-capacity capacitor to suppress intermediate frequency ripple. The input and output terminals of the ADC are equipped with large and small capacitor banks respectively, and the large and small capacitor banks adopt a star grounding topology.

8. An electromagnetic compatibility design method for a voltage reference evaluation board, characterized in that, Includes the following steps: The system is designed with separate core board and baseboard. The core board integrates high-speed digital circuits, while the baseboard centrally houses high-precision analog chips. The core board and baseboard are connected by a vertically penetrating connector to form an in-board ground loop. The baseboard is designed as a four-layer stacked structure, consisting of a top signal layer, a ground layer, a power layer, and a bottom signal layer from top to bottom. The bottom signal layer has test holes for a reference voltage source, ADC, operational amplifier, voltage divider module, and voltage source under test, which are located away from the main control area of ​​the core board. An annular heat insulation groove is opened around the reference voltage source to form an air heat insulation layer, and a high-density grounding via array is deployed on both sides of the heat insulation groove, with bridging capacitors laid across the groove.

9. The electromagnetic compatibility design method for the voltage reference evaluation board according to claim 8, characterized in that, In the multilayer PCB routing design of the voltage reference evaluation board, the interconnection traces between each IC follow the principles of electromagnetic compatibility and signal integrity.

10. The electromagnetic compatibility design method for the voltage reference evaluation board according to claim 8, characterized in that, In the interconnect architecture between the core board and the baseboard, the connector adopts a copper layer covering structure and is grounded at both ends: the connector passes through the stacked structure of the core board and the baseboard, the upper end of the connector forms a low impedance connection with the ground plane of the core board with an impedance ≤20mΩ, and the lower end is connected to the ground layer of the baseboard using the same process to build a through grounding path.

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