Array substrate

Abstract

The array substrate comprises a substrate, M scanning lines, N data lines, M * N pixel units and a plurality of shielding units. The M scanning lines and the N data lines are arranged on the substrate and are arranged in a staggered mode to define M * N pixel units. Each pixel unit comprises a switch element with an active layer, and the vertical projection of the active layer of each pixel unit on the substrate completely falls into the vertical projection of one shielding unit on the substrate. The first to sixth pixel units arranged in sequence in the same column are respectively provided with first to sixth shielding units. The first shielding unit is electrically connected with the fourth shielding unit, the second shielding unit is electrically connected with the fifth shielding unit, and the third shielding unit is electrically connected with the sixth shielding unit.

Description

Technical Field

[0001] This disclosure relates to an array substrate, and more particularly to an array substrate for a display panel. Background Technology

[0002] Generally, thin-film transistors (TFTs) in the array substrate of display panels typically use silicon semiconductors as the active layer material, which can be further divided into amorphous silicon, polysilicon, or monocrystalline silicon. Amorphous silicon semiconductors are widely used in various TFTs due to their simple manufacturing process and low cost. However, amorphous silicon semiconductors have low electron mobility, making it difficult to miniaturize the transistor size and resulting in slow switching speeds, thus limiting their application in high-resolution, high-end display panels. In contrast, polycrystalline or monocrystalline silicon semiconductors have much higher electron mobility, thus exhibiting excellent switching characteristics, but their manufacturing costs are relatively higher. Furthermore, due to the lower energy levels of polycrystalline or monocrystalline silicon semiconductors, they are prone to generating carrier pairs (electron-hole pairs) when illuminated, leading to photocurrent and leakage current, which affects display quality. Summary of the Invention

[0003] The purpose of this disclosure is to provide an array substrate that can reduce the photocurrent generated by illumination in polycrystalline silicon or monocrystalline silicon semiconductor transistors and reduce flicker.

[0004] To achieve the above objectives, one embodiment of this disclosure provides an array substrate comprising a substrate, M scan lines, N data lines, M×N pixel units, and a plurality of masking units. The M scan lines and N data lines are disposed on the substrate. The M×N pixel units are defined by an alternating arrangement of the M scan lines and N data lines. Each pixel unit includes a switching element having an active layer. Each masking unit corresponds to one of the pixel units. The vertical projection of the active layer of each pixel unit onto the substrate completely falls within the vertical projection of a corresponding masking unit onto the substrate. A first pixel unit, a second pixel unit, a third pixel unit, a fourth pixel unit, a fifth pixel unit, and a sixth pixel unit arranged sequentially in the same column are respectively provided with a first masking unit, a second masking unit, a third masking unit, a fourth masking unit, a fifth masking unit, and a sixth masking unit. The first masking unit is electrically connected to the fourth masking unit, the second masking unit is electrically connected to the fifth masking unit, and the third masking unit is electrically connected to the sixth masking unit.

[0005] According to some embodiments of this disclosure, the first shielding unit, the second shielding unit, and the third shielding unit are electrically isolated from each other.

[0006] According to some embodiments of this disclosure, the first shielding unit, the second shielding unit, the third shielding unit, the fourth shielding unit, the fifth shielding unit, and the sixth shielding unit are electrically connected.

[0007] According to some embodiments of this disclosure, in the same column of pixel units, the seventh, eighth, ninth, tenth, eleventh, and twelfth pixel units, arranged sequentially on the side opposite to the sixth and fifth pixel units, are respectively provided with a seventh masking unit, an eighth masking unit, a ninth masking unit, a tenth masking unit, an eleventh masking unit, and a twelfth masking unit. The seventh, eighth, ninth, tenth, eleventh, and twelfth masking units are electrically connected, and the first masking unit and the seventh masking unit are electrically isolated.

[0008] According to some embodiments of this disclosure, each switching element includes a first electrode electrically connected to a corresponding counterpart of the N data lines. The vertical projection of each shielding unit onto the substrate overlaps the vertical projection of the data lines electrically connected to the corresponding switching element of the M×N pixel units onto the substrate.

[0009] According to some embodiments of this disclosure, each pixel unit includes a pixel electrode, and each switching element further includes a second electrode electrically connected to the pixel electrode. The vertical projection of each masking unit onto the substrate overlaps with the vertical projection of the second electrode of the corresponding switching element of the M×N pixel units onto the substrate.

[0010] According to some embodiments of this disclosure, the vertical projection of each masking unit onto the substrate and the vertical projection of the pixel electrode electrically connected to the switching element corresponding to the M×N pixel units onto the substrate are offset.

[0011] According to some embodiments of this disclosure, each masking unit is disposed between the substrate and the active layer of the switching element corresponding to the M×N pixel units.

[0012] According to some embodiments of this disclosure, the array substrate further includes a first multiplexing unit and a second multiplexing unit. The first multiplexing unit is electrically connected to a first data line, a second data line, and a third data line. The second multiplexing unit is electrically connected to a fourth data line, a fifth data line, and a sixth data line. The first data line, the second data line, the third data line, the fourth data line, the fifth data line, and the sixth data line are respectively electrically connected to a first pixel unit, a second pixel unit, a third pixel unit, a fourth pixel unit, a fifth pixel unit, and a sixth pixel unit.

[0013] According to some embodiments of this disclosure, the first data line is electrically connected to a pixel unit in the same row as and adjacent to the second pixel unit, the second data line is electrically connected to a pixel unit in the same row as and adjacent to the third pixel unit, the third data line is electrically connected to a pixel unit in the same row as and adjacent to the fourth pixel unit, and the fifth data line is electrically connected to a pixel unit in the same row as and adjacent to the sixth pixel unit.

[0014] In the various embodiments described above, by providing a shielding unit between the substrate included in the array substrate and the active layer of the switching element of the pixel unit, the optical leakage current formed by illumination in the active layer can be reduced. Furthermore, depending on the order and polarity of the data voltage received by the pixel units, by electrically connecting the shielding units configured for each row of pixel units in the same row in different ways, the flickering during frame switching caused by the parasitic capacitive coupling effect formed by the shielding units can be effectively improved. Attached Figure Description

[0015] The embodiments of this disclosure can be understood from the following detailed description and accompanying drawings. It should be noted that many features are not drawn to industry-standard scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0016] Figure 1 This is a schematic diagram of a display panel shown according to an embodiment of the present disclosure.

[0017] Figure 2 This is a circuit diagram of an array substrate shown according to an embodiment of the present disclosure.

[0018] Figure 3 This is illustrated in one embodiment based on the present disclosure. Figure 2 A schematic diagram of the layout of a switching element and its corresponding shielding unit.

[0019] Figure 4 It is based on Figure 3 The structure is shown in the cross-sectional view along the tangent AA'.

[0020] Figure 5 This is a schematic diagram of an array substrate shown according to another embodiment of the present disclosure.

[0021] Figure 6 This is a schematic diagram illustrating the configuration of a shielding unit according to an embodiment of the present disclosure.

[0022] Figure 7 This is a schematic diagram illustrating the configuration of a shielding unit according to another embodiment of the present disclosure.

[0023] Explanation of reference numerals in the attached figures: 100: Display panel 110, 200, 500: Array substrate 130: Opposing substrate 150: Display medium 210: Substrate 220,510: pixel unit 221: Switching element 222: Pixel Electrode 230, 610, 620, 630, 640, 650, 660, 710, 720, 730, 740, 750, 760: Shielding units 310: Buffer layer 320: Active Layer 330: Insulation layer 340: Flattening layer AA': Tangent C1, C2: Parasitic capacitance DDL: Dummy Data Cable DL1,DL2,DL3,DL4, DL5,DL6,DL7,DL8,DL9, DL10, DL11, DL12, DL(N-2), DL(N-1), DLN: Data cables E1: First electrode E2: Second electrode GE: Gate electrode MUX1, MUX2, MUX3, MUX4, MUXP: Multiplexing Unit PA,PA',PB,PB',PC,PC': Data voltage SL1, SL2, SL3, SLM: Scan lines Detailed Implementation

[0024] This disclosure will be described in detail with reference to the following embodiments. It should be noted that the descriptions of the embodiments in this disclosure are for illustrative purposes only and are not intended to disclose all possible implementations or limit the specific implementations of this disclosure. For example, the phrase "a first feature is formed on a second feature" includes various implementations, ranging from situations where the first and second features are in direct contact to situations where an additional feature is formed between the first and second features so that they are not in direct contact. Furthermore, the same element symbols used in the drawings and specification will, as far as possible, represent the same or similar elements.

[0025] It is understood that while terms such as "first" and "second" may be used in this document to describe various features, these terms should not limit these features. These terms are only used to distinguish one feature from another.

[0026] The language used herein is for the purpose of describing particular embodiments only and is not intended to limit the claims. Unless otherwise limited, the singular forms of "a" or "the" may also be used to denote the plural forms.

[0027] In the following text, to clearly present the technical features of this disclosure, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of this disclosure are primarily illustrative and not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of this disclosure.

[0028] Please refer to Figure 1 . Figure 1 This is a schematic diagram of a display panel 100 according to an embodiment of the present disclosure. The display panel 100 may include an array substrate 110, a counter substrate 130, and a display medium 150. The display medium 150 is disposed between the array substrate 110 and the counter substrate 130, and may be, for example, liquid crystal, electrophoretic material, electrowetting material, organic light-emitting material, or inorganic light-emitting material. A plurality of switching elements may be formed on the array substrate 110 to serve as pixel units. The switching elements are turned on and off to control whether the pixel unit displays a corresponding color, such as red, green, blue, yellow, white, etc. The counter substrate 130 may have different forms depending on the type of display medium 150. For example, if the display medium 150 is liquid crystal, the counter substrate 130 may be a substrate with a color filter layer formed thereon to display various colors. If the display medium 150 is an organic light-emitting material or an inorganic light-emitting material, the counter substrate 130 may be a transparent substrate.

[0029] Please refer to the above as well. Figure 2 . Figure 2 This is a circuit diagram of an array substrate 200 according to an embodiment of the present disclosure. The array substrate 200 can be applied to... Figure 1The display panel 100 has an array substrate 110. The array substrate 200 may include a substrate 210, M scan lines SL1, SL2, SL3, ..., SLM, N data lines DL1, DL2, DL3, ..., DLN, and M×N pixel units 220. The scan lines SL1 to SLM and the data lines DL1 to DLN are disposed on the substrate 210 and are staggered to define the M×N pixel units 220. Each pixel unit 220 includes a switching element 221 and a pixel electrode 222. The switching element 221 may include a gate electrode GE electrically connected to a scan line, a first electrode E1 electrically connected to a data line, a second electrode E2 electrically connected to the pixel electrode 222, and an active layer (not shown). The first electrode E1 and the second electrode E2 are coupled to the active layer. The scan lines SL1 to SLM are configured to provide scan signals. The data lines DL1 to DLN are configured to provide data voltages. When the switching element 221 is turned on according to the scan signal, the active layer of the switching element 221 can form a channel region. The data voltage provided by the data line can be transmitted to the pixel electrode 222 via the first electrode E1 of the switching element 221, the channel region of the active layer and the second electrode E2, so that the pixel electrode 222 has a corresponding data voltage to drive the pixel unit 220 to display the corresponding grayscale.

[0030] In this embodiment, the switching element 221 may be, for example, a thin-film transistor comprising an active layer formed of polycrystalline silicon or monocrystalline silicon semiconductor. To prevent leakage current from the thin-film transistor due to illumination (e.g., a light source provided by a backlight module), the array substrate 200 may also include a plurality of shielding units 230, each shielding unit 230 corresponding to a pixel unit 220. Specifically, the shielding unit 230 may be formed of metal and is disposed corresponding to the active layer in the switching element 221 of the pixel unit 220 to block the light source from directly illuminating the active layer of the switching element 221.

[0031] Please refer to the above as well. Figure 3 and Figure 4 . Figure 3 This is illustrated in one embodiment based on the present disclosure. Figure 2 A schematic diagram of the layout of a switching element 221 and a corresponding shielding unit 230. Figure 4 It is based on Figure 3The structure is shown in the cross-sectional view along tangent AA'. Specifically, a first metal layer is first formed on substrate 210 and patterned to form a shielding unit 230. Next, a buffer layer 310 is formed on the shielding unit 230. Then, a semiconductor layer is formed on the buffer layer 310 and patterned to form the active layer 320 of the switching element 221. The material of the semiconductor layer can be, for example, polysilicon or monocrystalline silicon. Next, an insulating layer 330 is formed on the active layer 320 and patterned to form a first through-hole. Then, a second metal layer is formed on the insulating layer 330, which can be directly connected to the active layer 320 via the first through-hole. Next, the second metal layer is patterned to form the first electrode E1 and the second electrode E2 of the switching element 221, as well as a data line (e.g., a data line DLN) electrically connected to the switching element 221. Then, a planarization layer 340 is formed on the insulating layer 330, the first electrode E1, the second electrode E2, and the data line, and the planarization layer 340 is patterned to form a second via in the region corresponding to the second electrode E2. Figure 4 (Not shown). Next, a transparent conductive layer is formed on the planarization layer 340. Figure 4 (Not shown), the transparent conductive layer can be directly connected to the second electrode E2 via the second through-hole, and then the transparent conductive layer is patterned to form a pixel electrode electrically connected to the switching element 221. Figure 3 and Figure 4 (Not shown). In one embodiment, the switching element 221 may be, for example, a top-gate transistor. Therefore, before forming a planarization layer on the second metal layer, a third metal layer may be formed on the insulating layer 330 and patterned to form the gate electrode GE of the switching element 221. Figure 4 (not shown) and scan lines (e.g., scan lines SLM) electrically connected to the switching element 221. Figure 4 (Not shown). Optionally, at least one insulating layer may be formed on the insulating layer 330 before forming the gate electrode GE and the scan line. Alternatively, the gate electrode GE and the scan line may be formed on the insulating layer 330 first, followed by forming at least one insulating layer on the gate electrode GE and the scan line before forming the first electrode E1, the second electrode E2, and the data line.

[0032] like Figure 3 As shown, in order to prevent the active layer 320 of the switching element 221 from being illuminated by a light source (e.g., a backlight module) located below the substrate 210, the vertical projection of the active layer 320 of each pixel unit 220 onto the substrate 210 completely falls within the vertical projection of a corresponding shielding unit 230 onto the substrate 210. In other words, the area of ​​the shielding unit 230 can cover the entire area of ​​the active layer 320, thereby preventing the formation of optical leakage current.

[0033] To improve the shielding effect, in one embodiment, the vertical projection of each shielding unit 230 onto the substrate 210 partially or completely overlaps with the vertical projection of the data line electrically connected to the corresponding switching element 221 and / or the first electrode E1 of the switching element 221 onto the substrate 210. Optionally, the vertical projection of each shielding unit 230 onto the substrate 210 partially or completely overlaps with the vertical projection of the second electrode E2 of the corresponding switching element 221 onto the substrate 210. In other words, the area of ​​the shielding unit 250 can cover the entire area of ​​the first electrode E1 and / or the second electrode E2 of the switching element 221, as well as the area of ​​the data line covered.

[0034] In another embodiment, the vertical projection of each masking unit 230 onto the substrate 210 is offset from the vertical projection of the pixel electrode electrically connected to the switching element 221 onto the substrate 210. In other words, the area of ​​the second perforation formed in the planarization layer 340 is offset from the masking unit 230, so that the area of ​​the masking unit 230 does not cover the area of ​​the pixel electrode, thereby avoiding affecting the aperture ratio of the pixel unit 220.

[0035] like Figure 4 As shown, although a larger area of ​​the shielding unit 230 covering the switching element 221 results in better shielding, since the shielding unit 230, the first electrode E1, and the second electrode E2 are all made of metal, the parasitic capacitance C1 formed between the shielding unit 230 and the first electrode E1, and the parasitic capacitance C2 formed between the shielding unit 230 and the second electrode E2, will also increase. Therefore, when the switching element 221 is turned on according to the scan signal, the data voltage is transmitted to the pixel electrode 222 not only through the first electrode E1, the channel region of the active layer 320, and the second electrode E2, but also coupled to the pixel electrode 222 through the parasitic capacitances C1 and C2. On the other hand, to avoid polarization of the liquid crystal molecules, the polarity of the data voltage received by the pixel unit during the display phase of two consecutive frames will be opposite; this is also known as polarity inversion. However, due to the parasitic capacitances C1 and C2 coupling path between the first electrode E1 (and the data line) and the second electrode E2, the potential of the masking unit 230 changes when polarity is reversed, thereby affecting the actual data voltage received by the pixel electrode electrically connected to the second electrode E2, resulting in flickering during frame switching.

[0036] To improve the flickering issue that occurs when displaying images on the array substrate with the aforementioned shielding unit, this disclosure provides an array substrate with an alternative configuration. Please refer to... Figure 5 , Figure 5This is a schematic diagram of an array substrate 500 according to another embodiment of the present disclosure. For ease of explanation, the array substrate 500 omits the drawings showing the substrate, scan lines, switching elements, pixel electrodes, and masking units. The array substrate 500 may include N data lines DL1 to DLN and M×N pixel units 510. In this embodiment, the array substrate 500 may also include P multiplexing units MUX1 to MUXP, where P is a positive integer less than N. These multiplexing units MUX1 to MUXP are configured to integrate several data lines together. Each multiplexing unit can be connected to an output pin of a source driver IC. In this way, an output pin of the source driver IC is not electrically connected to only one data line, but is electrically connected to multiple data lines through multiplexing units, thereby providing data voltage using time-division multiplexing, thereby reducing the number of required pins, for example, from N to P. For high-resolution array substrates, the number of required source driver ICs can be significantly reduced.

[0037] In this embodiment, the multiplexing unit adopts a three-to-one design. For example, data lines DL1, DL2, and DL3 can be electrically connected to the first output pin via multiplexing unit MUX1; data lines DL4, DL5, and DL6 can be electrically connected to the second output pin via multiplexing unit MUX2; data lines DL7, DL8, and DL9 can be electrically connected to the third output pin via multiplexing unit MUX3; data lines DL10, DL11, and DL12 can be electrically connected to the fourth output pin via multiplexing unit MUX4, and so on. Data lines DL(N-2), DL(N-1), and DLN can be electrically connected to the Pth output pin via multiplexing unit MUXP, where N = 3 × P. For ease of explanation, Figure 5 The source driver chip and the output pins electrically connected to the multiplexing unit are not shown.

[0038] In addition, with Figure 2Compared to the array substrate 200, in this embodiment, the polarity reversal of the pixel units 510 is configured using a zigzag reversal method to avoid polarization of the liquid crystal molecules. Besides achieving a similar effect to dot reversal, zigzag reversal is also more energy-efficient. Specifically, data line DL1 is not directly electrically connected to all pixel units 510 in the first row, but rather to the odd-numbered columns of pixel units 510 in the first row and the even-numbered columns of pixel units 510 in the second row. Data line DL2 is electrically connected to the odd-numbered columns of pixel units 510 in the second row and the even-numbered columns of pixel units 510 in the third row. Data line DL3 is electrically connected to the odd-numbered columns of pixel units 510 in the third row and the even-numbered columns of pixel units 510 in the fourth row, and so on. Data line DLN is electrically connected to the odd-numbered columns of pixel units 510 in the Nth row. It is worth mentioning that in the zigzag inversion configuration, for the even-numbered column pixel units 510 in the first row, a dummy data line (DDL) can be additionally provided to provide the corresponding data voltage to the pixel unit 510. The dummy data line DDL does not need to be connected to one of the output pins of the source driver chip via a multiplexing unit.

[0039] exist Figure 5 In the example, data voltages PA and PA', data voltages PB and PB', and data voltages PC and PC' can each represent signals of different polarities received at the same time. In other words, data voltages PA, PB, and PC can have a first polarity, and data voltages PA', PB', and PC' can have a second polarity, with the first polarity being opposite to the second polarity. Furthermore, pixel units 510 in rows 1, 4, 7, ..., (N-2) are all used to display a first color (e.g., red). Pixel units 510 in rows 2, 5, 8, ..., (N-1) are all used to display a second color (e.g., green). Pixel units 510 in rows 3, 6, 9, ..., N are all used to display a third color (e.g., blue).

[0040] In one operation, when the switching elements of all pixel units 510 in the same column (e.g., column 1) are turned on via the scan line, the multiplexing units MUX1, MUX3, ..., MUX(P-1) ( Figure 5 (Not shown) can be controlled separately to be transmitted via data lines DL1, DL7, ..., DL(N-5) during a first period of a scan time in a frame display phase. Figure 5(Not shown) A data voltage PA of first polarity is transmitted to the corresponding connected pixel unit 510. Simultaneously, multiplexing units MUX2, MUX4, ..., MUXP can be controlled to transmit a data voltage PA' of second polarity to the corresponding connected pixel unit 510 via data lines DL4, DL10, ..., DL(N-2) during the same first period. Next, for pixel units 510 in the same column (i.e., the first column), multiplexing units MUX1, MUX3, ..., MUX(P-1) can be controlled to transmit a data voltage PA' of second polarity to the corresponding connected pixel unit 510 via data lines DL2, DL8, ..., DL(N-4) during the second period of the same scan time. Figure 5 (Not shown) A data voltage PB' of the second polarity is transmitted to the corresponding connected pixel unit 510. Simultaneously, multiplexing units MUX2, MUX4, ..., MUXP can be controlled to transmit a data voltage PB of the first polarity to the corresponding connected pixel unit 510 via data lines DL5, DL11, ..., DL(N-1) during the same second period. Next, for pixel units 510 still in the same column (i.e., the first column), multiplexing units MUX1, MUX3, ..., MUX(P-1) can be controlled to transmit a data voltage PB of the first polarity to the corresponding connected pixel unit 510 via data lines DL3, DL9, ..., DL(N-3) during the same third period of the same scan time. Figure 5 (Not shown) A data voltage PC of the first polarity is transmitted to the corresponding connected pixel unit 510. At the same time, multiplexing units MUX2, MUX4, ..., MUXP can be controlled to transmit a data voltage PC' of the second polarity to the corresponding connected pixel unit 510 via data lines DL6, DL12, ..., DLN during the same third period. Thus, the reception of the data voltage of one column of pixels is completed.

[0041] Once all pixel units 510 in the same column (e.g., the first column) have received data voltage, the switching elements of all pixel units 510 in the next column (i.e., the second column) are activated via a scan signal. Data voltage is then transmitted sequentially through different data lines of the same multiplexing unit during the first, second, and third periods of this scan time, according to the time-division multiplexing method described above. This process continues until all pixel units 510 in each column of the array substrate 500 have completed receiving data voltage. Then, the display phase of the next frame begins.

[0042] It is worth mentioning that, in response to the switching element of the odd-numbered column pixel unit 510 being turned on, the pixel unit 510 in the Nth row can receive data voltage via the data line DLN. In response to the switching element of the even-numbered column pixel unit 510 being turned on, the pixel unit 510 in the first row can receive data voltage via the dummy data line DDL.

[0043] exist Figure 5In the architecture, for pixel units 510 in the same column, pixel units 510 in the i-th row and pixel units 510 in the (i+3)-th row can simultaneously receive data voltages of opposite polarities, where 1 ≤ i ≤ (N-3). Accordingly, for each column of pixel units 510, if the masking unit (e.g., the one set for the pixel unit in the i-th row) is... Figure 6 The masking unit 610) and the masking unit set for the pixel unit corresponding to the (i+3)th row (e.g., Figure 6 If the masking unit 640 is electrically connected, then when the data voltage with a first polarity received by the pixel unit 510 in the i-th row is coupled to the masking unit 610 via the parasitic capacitor C1, it can simultaneously cancel each other out through the data voltage with a second polarity received by the pixel unit 510 in the (i+3)-th row being coupled to the masking unit 640 via the parasitic capacitor C1 (because the masking units 610 and 640 are electrically connected together), so that the potential change of the entire masking unit is reduced, thereby avoiding flickering when switching from one frame to the next.

[0044] For example, such as Figure 6 As shown, Figure 6 This is a schematic diagram illustrating the configuration of a shielding unit according to an embodiment of the present disclosure. Figure 6 The shielding units 610-660 can be, for example, Figure 3 The shielding unit 230, and corresponding to Figure 5 The pixel units 510 are configured. For each column of six sequentially arranged pixel units 510, for example, the masking unit 610 corresponding to the pixel unit 510 in the first row of the first column can be electrically connected to the masking unit 640 corresponding to the pixel unit 510 in the fourth row, the masking unit 620 corresponding to the pixel unit 510 in the second row can be electrically connected to the masking unit 650 corresponding to the pixel unit 510 in the fifth row, and the masking unit 630 corresponding to the pixel unit 510 in the third row can be electrically connected to the masking unit 660 corresponding to the pixel unit 510 in the sixth row. Furthermore, the masking units 610, 620, and 630 are electrically isolated from each other. In other words, the masking units 640, 650, and 660 are also electrically isolated from each other. Similarly, the masking units provided in the first column of pixel units 510 corresponding to the 7th to 12th rows of pixel units 510, and so on, the masking units provided in the (N-5)th to Nth rows of pixel units 510 can all be connected in the manner described above, so as to cancel the parasitic capacitive coupling charge between the first electrode of the switching element and the masking unit by simultaneously receiving data voltages of different polarities.

[0045] Please refer to Figure 7 , Figure 7This is a schematic diagram illustrating the configuration of a shielding unit according to another embodiment of the present disclosure. Figure 7 The shielding units 710-760 can be, for example, Figure 3 The shielding unit 230, and corresponding to Figure 5 The pixel units 510 are configured. For each column of six sequentially arranged pixel units 510, for example, in the first column of pixel units 510, the masking unit 710 corresponding to the pixel units 510 in the first row, the masking unit 720 corresponding to the pixel units 510 in the second row, the masking unit 730 corresponding to the pixel units 510 in the third row, the masking unit 740 corresponding to the pixel units 510 in the fourth row, the masking unit 750 corresponding to the pixel units 510 in the fifth row, and the masking unit 760 corresponding to the pixel units 510 in the sixth row can be electrically connected to form a masking unit group. Similarly, the masking units corresponding to the pixel units 510 in the first column of pixel units 510 in rows 7 to 12 can be electrically connected to form another masking unit group, and so on, the masking units corresponding to the pixel units 510 in rows (N-5) to N can be electrically connected to form another masking unit group. All shielding units are electrically isolated from each other.

[0046] In a pixel unit structure with a three-to-one multiplexing unit and zigzag inversion, the time and polarity of the data voltage received by pixel units arranged in the same column and six rows in sequence constitute one cycle. Therefore, by electrically connecting the masking units of corresponding six sequentially arranged pixel units in the same column into a masking unit group, the charges coupled by the parasitic capacitance between the six masking units in a masking unit group can cancel each other out, thus reducing the potential change of the masking unit group and preventing flickering when switching from one frame to the next.

[0047] In summary, in the various embodiments presented in this disclosure, by providing a shielding unit between the substrate included in the array substrate and the active layer of the switching element of the pixel unit, the optical leakage current formed by illumination in the active layer can be reduced. Furthermore, depending on the arrangement of the order and polarity of the data voltage received by the pixel unit, such as a configuration with three-to-one multiplexing units and zigzag inversion, by electrically connecting the shielding units configured for each row of pixel units in the same column in different ways, the flickering during frame switching caused by the parasitic capacitive coupling effect formed by the shielding units can be effectively improved.

[0048] Although the embodiments of this disclosure have been disclosed above, they are not intended to limit the embodiments of this disclosure. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the embodiments of this disclosure. Therefore, the protection scope of the embodiments of this disclosure shall be determined by the claims.

Claims

1. An array substrate, comprising: One substrate; M scan lines are disposed on the substrate; N data lines are arranged on this substrate; M×N pixel units are defined by the M scan lines and the N data lines in an alternating configuration, wherein each of the M×N pixel units includes a switching element having an active layer; and Multiple masking units, each of which is provided in relation to one of the M×N pixel units, wherein the vertical projection of the active layer of each of the M×N pixel units onto the substrate falls entirely within the vertical projection of one of the masking units onto the substrate. In the same column of pixel units, a first pixel unit, a second pixel unit, a third pixel unit, a fourth pixel unit, a fifth pixel unit, and a sixth pixel unit arranged in sequence are respectively provided with a first masking unit, a second masking unit, a third masking unit, a fourth masking unit, a fifth masking unit, and a sixth masking unit. The first masking unit is electrically connected to the fourth masking unit, the second masking unit is electrically connected to the fifth masking unit, and the third masking unit is electrically connected to the sixth masking unit.

2. The array substrate as claimed in claim 1, wherein the first shielding unit, the second shielding unit, and the third shielding unit are electrically isolated from each other.

3. The array substrate as claimed in claim 1, wherein the first shielding unit, the second shielding unit, the third shielding unit, the fourth shielding unit, the fifth shielding unit, and the sixth shielding unit are electrically connected.

4. The array substrate as claimed in claim 3, wherein a seventh pixel unit, an eighth pixel unit, a ninth pixel unit, a tenth pixel unit, an eleventh pixel unit, and a twelfth pixel unit arranged sequentially on the side opposite to the sixth pixel unit and the fifth pixel unit in the same column are respectively provided with a seventh masking unit, an eighth masking unit, a ninth masking unit, a tenth masking unit, an eleventh masking unit, and a twelfth masking unit, wherein the seventh masking unit, the eighth masking unit, the ninth masking unit, the tenth masking unit, the eleventh masking unit, and the twelfth masking unit are electrically connected, and the first masking unit and the seventh masking unit are electrically isolated.

5. The array substrate of claim 1, wherein each of the switching elements includes a first electrode electrically connected to a counterpart of the N data lines, wherein the vertical projection portion of each of the shielding units on the substrate overlaps the vertical projection of the data line electrically connected to the switching element corresponding to the M×N pixel units on the substrate.

6. The array substrate of claim 1, wherein each of the M×N pixel units includes a pixel electrode, and each of the switching elements further includes a second electrode electrically connected to the pixel electrode, wherein the vertical projection portion of each of the masking units on the substrate overlaps the vertical projection of the second electrode of the corresponding switching element of the M×N pixel units on the substrate.

7. The array substrate of claim 6, wherein the vertical projection of each of the shielding units onto the substrate and the vertical projection of the pixel electrode electrically connected to the switching element of the corresponding M×N pixel units onto the substrate are offset.

8. The array substrate of claim 1, wherein each of the masking units is disposed between the substrate and the active layer of the switching element of the corresponding M×N pixel units.

9. The array substrate of claim 1, further comprising a first multiplexing unit and a second multiplexing unit, the first multiplexing unit being electrically connected to a first data line, a second data line and a third data line, the second multiplexing unit being electrically connected to a fourth data line, a fifth data line and a sixth data line, wherein the first data line, the second data line, the third data line, the fourth data line, the fifth data line and the sixth data line are respectively electrically connected to the first pixel unit, the second pixel unit, the third pixel unit, the fourth pixel unit, the fifth pixel unit and the sixth pixel unit.

10. The array substrate of claim 9, wherein the first data line is also electrically connected to a pixel unit in the same row as and adjacent to the second pixel unit, the second data line is also electrically connected to a pixel unit in the same row as and adjacent to the third pixel unit, the third data line is also electrically connected to a pixel unit in the same row as and adjacent to the fourth pixel unit, and the fifth data line is also electrically connected to a pixel unit in the same row as and adjacent to the sixth pixel unit.

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