Clock gating control method, chip, device and electronic equipment

Abstract

The embodiment of the invention provides a clock gating control method, a chip, a device and electronic equipment, and relates to the technical field of electronic communication, and the method comprises the steps: obtaining time information which comprises a communication time range of at least one communication module in at least one communication scene; and generating a control signal based on the reference clock signal and the time information, the control signal being used for controlling on or off of a clock gate corresponding to the at least one communication module. According to the method provided by the invention, the time information is configured, so that the control signal can be generated according to the reference clock signal and the time information to dynamically control the transmission of the clock signal of the communication module, the complex time sequence requirements of multiple communication scenes can be met, and dynamic power consumption optimization, multi-module time sequence synchronization and hardware simplification are realized; accurate clock gating control is realized, and the control flexibility is improved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic communication technology, and in particular to a clock gating control method, chip, device, and electronic device. Background Technology

[0002] In communication chips, PPA (Performance / Power / Area) is three very important metrics, among which reducing power consumption is a crucial task, and clock gating is an important means of reducing power consumption. Summary of the Invention

[0003] This disclosure provides a clock gating control method, chip, device, and electronic device, and proposes a hardware and software combined clock gating control method to reduce the power consumption of communication chips.

[0004] A first aspect of this disclosure provides a clock gating control method, the method comprising: acquiring time information, the time information including a communication time range of at least one communication module in at least one communication scenario; and generating a control signal based on a reference clock signal and the time information, the control signal being used to control the opening or closing of the clock gating corresponding to at least one communication module.

[0005] In some embodiments of this disclosure, generating a control signal based on a reference clock signal and time information includes: using a local counter to count based on the reference clock signal and determining a count value; and generating a control signal based on the count value and time information.

[0006] In some embodiments of this disclosure, generating a control signal based on a count value and time information includes: determining that the first control signal corresponding to the first communication module is high level in response to the count value being within a first time range of the first communication module; and determining that the first control signal corresponding to the first communication module is low level in response to the count value not being within the first time range of the first communication module.

[0007] In some embodiments of this disclosure, the method further includes: determining a level value based on a first control signal of the first communication module; and determining whether the clock gating of the first communication module is turned on or off based on the level value.

[0008] In some embodiments of this disclosure, determining a level value based on a first control signal of a first communication module includes: determining a level value as a first value in response to a high level of the first control signal; and determining a level value as a second value in response to a low level of the first control signal.

[0009] In some embodiments of this disclosure, determining whether the clock gating corresponding to the first communication module is turned on or off based on the level value includes: turning on the clock gating corresponding to the first communication module when the level value is a first value, so that a preset clock signal is input to the first communication module; and turning off the clock gating corresponding to the first communication module when the level value is a second value.

[0010] In the above embodiments, by configuring time information including the communication time range of at least one communication module in at least one communication scenario, a control signal can be generated based on the reference clock signal and time information to control the opening or closing of the clock gating corresponding to at least one communication module, dynamically control the transmission of the clock signal of the communication module, realize accurate clock gating control, improve control flexibility, and further reduce power consumption.

[0011] Furthermore, the clock gating control method proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, and realizes dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification. It is especially suitable for modern communication systems that are sensitive to power consumption and timing.

[0012] A second aspect of this disclosure provides a chip comprising: a software control module connected to at least one gating module; the software control module being configured to generate a control signal based on a reference clock signal and time information, the time information including the communication time range of at least one communication module in at least one communication scenario, and the control signal being configured to control the opening or closing of a clock gating corresponding to at least one communication module.

[0013] In some embodiments of this disclosure, at least one gating module is connected to at least one communication module, and the gating module and the communication module have a one-to-one correspondence.

[0014] In some embodiments of this disclosure, the software control module is further configured to: count using a local counter based on a reference clock signal to determine a count value; and generate a control signal based on the count value and time information.

[0015] In some embodiments of this disclosure, at least one gating module is configured to: determine a level value based on a first control signal from a first communication module; and determine whether the clock gating of the first communication module is turned on or off based on the level value.

[0016] In some embodiments of this disclosure, the first gating module is further configured to: determine a level value as a first value in response to a first control signal being high; and determine a level value as a second value in response to a first control signal being low.

[0017] In some embodiments of this disclosure, the first gating module is further configured to: enable the clock gating corresponding to the first communication module when the level value is a first value, so that a preset clock signal is input to the first communication module; and disable the clock gating corresponding to the first communication module when the level value is a second value.

[0018] In the above embodiments, the chip outputs control signals through a software control module, so that the generated control signals are input to the gating modules of the corresponding communication modules. The gating modules judge the control signals to turn the clock gating on or off, and control the input of the preset clock signal to the corresponding communication module, thereby improving the accuracy and flexibility of control and reducing the overall power consumption of the chip.

[0019] Furthermore, the chip proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, and achieves dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification, making it particularly suitable for modern communication systems that are sensitive to power consumption and timing.

[0020] A third aspect of this disclosure provides a clock gating control device, comprising: an acquisition module for acquiring time information, the time information including the communication time range of at least one communication module in at least one communication scenario; and a first control module for generating a control signal based on a reference clock signal and the time information, the control signal being used to control the opening or closing of the clock gating corresponding to at least one communication module.

[0021] In some embodiments of this disclosure, the first control module is further configured to: count using a local counter based on a reference clock signal to determine a count value; and generate a control signal based on the count value and time information.

[0022] In some embodiments of this disclosure, the first control module is further configured to: determine that the first control signal corresponding to the first communication module is high level in response to the count value being within a first time range of the first communication module; and determine that the first control signal corresponding to the first communication module is low level in response to the count value not being within the first time range of the first communication module.

[0023] In some embodiments of this disclosure, the device further includes a second control module, which is configured to: determine a level value based on a first control signal from the first communication module; and determine whether a clock gating corresponding to the first communication module is turned on or off based on the level value, so that a preset clock signal is input to the first communication module.

[0024] In the above embodiments, the clock gating control device acquires time information to generate control signals, which control the opening or closing of the clock gating of the corresponding communication modules, thereby inputting the preset clock signal into the corresponding communication module, improving the accuracy and flexibility of control, and further reducing the overall power consumption.

[0025] Furthermore, the clock gating control device proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, and realizes dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification, making it particularly suitable for modern communication systems that are sensitive to power consumption and timing.

[0026] A fourth aspect of this disclosure provides an electronic device comprising: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method described in any one of the first aspects of this disclosure, or includes the means described in any one of the third aspects of this disclosure.

[0027] A fifth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the methods described in the first aspect of this disclosure.

[0028] A sixth aspect of this disclosure provides a computer program product that, when run on a computer, causes the computer to perform the method described in any one of the first aspects of this disclosure.

[0029] In summary, the clock gating control method, chip, device, and electronic device proposed in this disclosure acquire time information, including the communication time range of at least one communication module in at least one communication scenario; based on a reference clock signal and the time information, a control signal is generated to control the opening or closing of the clock gating corresponding to at least one communication module. The clock gating control method proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, achieving dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification, and is particularly suitable for modern communication systems sensitive to power consumption and timing.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0032] Figure 1 This is a flowchart of a clock gating control method proposed in an embodiment of the present disclosure; Figure 2 This is a flowchart illustrating another clock gating control method proposed in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating another clock gating control method proposed in an embodiment of this disclosure; Figure 4 This is an architecture diagram of the chip proposed in an embodiment of this disclosure; Figure 5A A diagram illustrating the overall framework of the control strategy; Figure 5B A schematic diagram of an event timeline array for a communication scenario; Figure 5C This is a schematic diagram of the output timing of the clock pass-through control signal; Figure 6 This is a schematic diagram of the structure of a clock gating control device according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of an electronic device for implementing the clock gating control method described above, according to an exemplary embodiment. Detailed Implementation

[0033] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0034] In related technologies, clock gating is controlled by selecting either a software branch or a hardware branch. If software branch control is selected, the software is enabled before initialization or module startup, and disabled when the system finishes running or the module goes to sleep. If hardware branch control is selected, clock gating is enabled or disabled by an enable control signal generated by hardware. Software control has a coarser granularity, which is somewhat lacking for achieving precise control of low-power clock gating solutions; hardware control has a finer granularity, but its design complexity is higher, it is not easy to cover scenario-level boundaries, and the verification cycle is longer.

[0035] Therefore, in order to solve the above-mentioned technical problems, this disclosure provides a linkage scheme that combines software fitting with the hardware clock gating of submodules when dealing with low-power solutions in the system, in order to solve the problem of inaccurate clock gating scheme of communication hardware module at the scene level.

[0036] The clock gating control method, chip, and device proposed in this application will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 This is a flowchart of a clock gating control method proposed in an embodiment of this disclosure, as shown below. Figure 1 As shown, the method includes the following steps: Step 101: Obtain time information.

[0038] In some embodiments, the time information includes the communication time range of at least one communication module in at least one communication scenario.

[0039] In some embodiments, at least one communication module may include one or more communication modules, and each communication module may have a small module within it that can be gated by a hardware clock.

[0040] In some embodiments, at least one communication scenario may include one or more communication scenarios. In each communication scenario, the communication time range of each communication module may be the same or different, and this disclosure does not limit this.

[0041] Specifically, the communication scenario can be a predefined communication window template for each module on the timeline, or a communication module selected and configured by the software according to the current operating mode for automatic clock gating.

[0042] For example, scenario A corresponds to the "system initialization + low-speed data acquisition" stage; scenario B corresponds to the "high-speed data processing + peripheral interaction" stage. Different software programs or drivers may trigger a switch to different communication scenarios. In some embodiments, the communication time range of different communication modules in different communication scenarios may be the same or different, and this disclosure does not limit this.

[0043] In some embodiments, the communication time range represents the operating time of the communication module in the corresponding communication scenario. That is, within the communication time range, a working clock needs to be provided for the communication module and its hardware accelerator to ensure normal operation. Outside the communication time range, a working clock is not required for the communication module and its hardware accelerator.

[0044] In some embodiments, the time information may be a time schedule array or an event time schedule array, including multiple time intervals. For example, the communication time range of the first communication module in the first communication scenario is [A1, B1], the communication time range in the second communication scenario is [A2, B2], and the communication time range in the third communication scenario is [A3, B3]; the communication time range of the second communication module in the first communication scenario is [C1, D1], the communication time range in the second communication scenario is [C2, D2], and the communication time range in the third communication scenario is [C3, D3]; the communication time range of the third communication module in the first communication scenario is [E1, F1], the communication time range in the second communication scenario is [E2, F2], and the communication time range in the third communication scenario is [E3, F3].

[0045] In some embodiments, the time information can be pre-configured according to the communication time range of the communication module in different communication scenarios. It can flexibly configure the time information for different communication modules and different communication scenarios, thereby meeting the complex timing requirements of multiple communication scenarios.

[0046] For example, such as Figure 5B This is a schematic diagram of the event timeline array for a communication scenario. In communication scenario A, the communication time range of module A is [0, 200], the communication time range of module B is [5, 150], and the communication time range of module C is [20, 100]. In communication scenario B, the communication time range of module A is [250, 300], the communication time range of module B is [205, 350], and the communication time range of module C is [220, 280].

[0047] In the above embodiments, by setting the communication time window of each communication module to be fixed in each communication scenario, it is beneficial to avoid conflicts and meet real-time requirements. On the other hand, by configuring a time schedule array, the hardware automatically matches the switching clock according to time, without the need for frequent software intervention, which can reduce scheduling overhead; the proportion of active time of modules varies in different scenarios, which can be used to optimize dynamic power consumption and adapt to multi-mode energy saving.

[0048] Step 102: Generate control signals based on the reference clock signal and time information.

[0049] In some embodiments, the control signal is used to control the opening or closing of the clock gating corresponding to at least one communication module.

[0050] In some embodiments, the reference clock signal may be a general-purpose clock. The reference clock signal is used as a module for software control, such as a module that generates control signals based on the reference clock signal and time information through the startup and normal operation of the module.

[0051] In some embodiments, the reference clock signal is a high-precision, high-stability periodic signal that may be generated by a device such as a quartz crystal oscillator, an atomic clock, or GPS.

[0052] In some embodiments, generating control signals based on reference clock signals and time information can be achieved by generating control signals corresponding to each communication module according to the communication time range of each communication module in different communication scenarios in the time information.

[0053] In some embodiments, for different communication modules, control signals for the communication module can be generated based on a reference clock signal and the corresponding time information of the communication module.

[0054] In some embodiments, for a first communication module in at least one communication module, a first control signal for the first communication module is generated based on a reference clock signal and first time information corresponding to the first communication module.

[0055] In some embodiments, for at least one communication module, control signals for each communication module can be generated specifically based on a reference clock signal and the time information corresponding to each communication module.

[0056] In some embodiments, the control signal generated for each communication module can be used as the input signal for the clock gating of the corresponding communication module to control the opening or closing of the corresponding clock gating. In the open state, the corresponding clock signal can be input to the communication module, and in the closed state, the corresponding clock signal is not input to the communication module.

[0057] For example, such as Figure 5A The overall block diagram shown indicates that the local counter counts the general-purpose clock, and the software adaptive module outputs a clock penetration control signal when the count value meets the time interval according to the configured event schedule array.

[0058] In the above embodiments, by configuring time information including the communication time range of at least one communication module in at least one communication scenario, a control signal can be generated based on the reference clock signal and time information to control the opening or closing of the clock gating corresponding to at least one communication module, dynamically control the transmission of the clock signal of the communication module, realize accurate clock gating control, improve control flexibility, and further reduce power consumption.

[0059] Figure 2 This is a flowchart illustrating the clock gating control method proposed in an embodiment of this disclosure. Based on Figure 1 The embodiment shown, Figure 2 Step 102 is further defined, such as Figure 2 As shown, the method includes the following steps: Step 201: Based on the reference clock signal, use a local counter to count and determine the count value.

[0060] In some embodiments, a local counter is used to count based on a reference clock signal. This can be a local counter counting the reference clock signal in real time to obtain a real-time count value, i.e., a continuous sequence of natural values.

[0061] In some embodiments, a local counter is used to count and determine the count value based on a reference clock signal. This can be achieved by connecting the reference clock signal to the clock input of the local counter, triggering the counter via an edge. Specifically, the counter is triggered at each rising (or falling) edge of the reference clock signal to accumulate the count. For example, with a 10MHz reference clock, the count value increments by 1 every 100ns.

[0062] In some embodiments, the count value obtained by counting using a local counter can be stored in a register and read via the bus.

[0063] For example, such as Figure 5A The diagram shows the overall framework of the control strategy. The software configuration path configures the event schedule array, and the local counter of the software adaptive module counts the general clock to obtain the value of the local counter.

[0064] Step 202: Generate a control signal based on the count value and time information.

[0065] In some embodiments, a control signal is generated based on the count value and time information. This can be achieved by generating a control signal for the communication module at the corresponding count value when the count value meets the communication time range corresponding to the communication module, and by generating a control signal for the communication module as the count value increases.

[0066] In some embodiments, generating a control signal based on a count value and time information includes: determining that a first control signal corresponding to the first communication module is high level in response to the count value being within a first time range of the first communication module; and determining that a first control signal corresponding to the first communication module is low level in response to the count value not being within the first time range of the first communication module.

[0067] In some embodiments, the first communication module may be any one of at least one communication module.

[0068] In some embodiments, for the first communication module, the time information includes a corresponding first time range, which is the communication time range of the first communication module in at least one communication scenario.

[0069] For example, taking three communication scenarios as an example, the first time range includes the communication time range of the first communication module in the first communication scenario [A1,B1], the communication time range in the second communication scenario [A2,B2], and the communication time range in the third communication scenario [A3,B3].

[0070] In some embodiments, in response to the count value being within a first time range of the first communication module, the first control signal corresponding to the first communication module is determined to be high level, that is, when the count value satisfies any time interval in the first time range, the first control signal is high level at the corresponding count value.

[0071] In some embodiments, in response to the count value not being within the first time range of the first communication module, the first control signal corresponding to the first communication module is determined to be low. That is, when the count value does not satisfy all time intervals within the first time range, the first control signal is low at the corresponding count value.

[0072] For example, in communication scenario A, the communication time range of module A is [0, 200], and in communication scenario B, the communication time range of module A is [250, 300]. When the count value is in the range of [0, 200], the clock penetration control signal of module A outputs a high level. When the count value is 201, the clock penetration control signal of module A outputs a low level. When the count value is in the range of [201, 249], the clock penetration control signal of module A outputs a low level. When the count value reaches 250, the clock penetration control signal outputs a high level. When the count value is in the range of [250, 300], it outputs a high level. As the count value continues to increase, the clock penetration control signal outputs a low level.

[0073] For example, Table 1 shows the penetration results of each module based on local counters. Only a portion of the counter values ​​are used as examples for illustration.

[0074] Table 1

[0075] For module B, the communication time range of module B in communication scenario A is [5, 150], and the communication time range of module B in communication scenario B is [205, 350]. Therefore, a low-level clock penetration control signal is output when the count value is in [0, 4], [151, 204] and after exceeding 350, and a high-level clock penetration control signal is output in [5, 150] and [205, 350].

[0076] For module C, the communication time range of module C in communication scenario A is [20, 100], and the communication time range of module C in communication scenario B is [220, 280]. Therefore, a low-level clock penetration control signal is output when the count value is in [0, 19], [101, 219], and after exceeding 280. A high-level clock penetration control signal is output when the count value is in [20, 100] and [220, 280].

[0077] For example, such as Figure 5CThe output timing of the clock penetration control signal shown can be used to obtain the output timing of penetration result A of communication module A, the output timing of penetration result B of communication module B, and the output timing of penetration result C of communication module C.

[0078] In the above embodiments, the first control signal of the first communication module can control the opening or closing of the clock gate corresponding to the first communication module. That is, when the first control signal controls the clock gate to be opened, the clock signal before the gate can be output accordingly. When the first control signal controls the clock gate to be closed, the corresponding clock signal before the gate is not output, thereby further controlling the first communication module to work under the input clock signal.

[0079] In the above embodiments, by counting the reference clock signal according to the real-time counter, it is determined whether the communication time range of the communication module is met, so as to output the control signal corresponding to the communication module. This can meet the communication timing requirements of different communication modules in multiple communication scenarios, thereby improving the control accuracy and flexibility of clock gating and further reducing the overall power consumption.

[0080] Figure 3 This is a flowchart illustrating another clock gating control method proposed in an embodiment of this disclosure. Based on Figures 1-2 The embodiment shown, Figure 3 To further define, such as Figure 3 As shown, it includes the following steps: Step 301: Determine the level value based on the first control signal of the first communication module.

[0081] In some embodiments, determining a level value based on a first control signal of a first communication module includes: determining a level value as a first value in response to a high level of the first control signal; and determining a level value as a second value in response to a low level of the first control signal.

[0082] In some embodiments, the first control signal is judged to be high or low level, thereby obtaining the corresponding control level value.

[0083] Specifically, when the first control signal is high, the level value of the first control signal is a first value, which can be 1; when the first control signal is low, the level value of the first control signal is a second value, which can be 0.

[0084] For example, the clock penetration control signal of communication module A is input to the automatic clock gating of communication module A, the clock penetration control signal of communication module B is input to the automatic clock gating of communication module B, and the clock penetration control signal of communication module C is input to the automatic clock gating of communication module C. The automatic clock gating can determine the high or low level of the clock penetration control signal to obtain the real-time level value of the first control signal.

[0085] Step 302: Based on the level value, determine whether the clock gating of the first communication module is turned on or off.

[0086] In some embodiments, determining whether the clock gating corresponding to the first communication module is turned on or off based on the level value includes: turning on the clock gating corresponding to the first communication module when the level value is a first value, so that a preset clock signal is input to the first communication module; and turning off the clock gating corresponding to the first communication module when the level value is a second value.

[0087] In some embodiments, based on the level value corresponding to the first control signal, the opening or closing of the clock gating corresponding to the first communication module can be controlled in real time.

[0088] In some embodiments, the preset clock signal may be a pre-set clock signal, which may be the same as or different from the reference clock signal.

[0089] In some embodiments, when the level value of the first control signal is a first value, the clock gating corresponding to the first communication module is enabled, and in the state where the clock gating is enabled, the preset clock signal can be input to the first communication module.

[0090] In some embodiments, when the level value of the first control signal is the second value, the clock gating corresponding to the first communication module is turned off. When the clock gating is turned off, the preset clock signal cannot be input to the first communication module through the clock gating, and the input clock of the first communication module can be a fixed low level.

[0091] In some embodiments, the internal sub-modules of the first communication module can perform hardware clock gating based on the input clock signal to enable the hardware accelerator to start or stop.

[0092] In some embodiments, each communication module can control the opening or closing of the corresponding clock gating through its own control signal to obtain the input clock signal. When a preset clock signal is input to the communication module, the communication module can start or stop the hardware accelerator based on the input preset clock through hardware clock gating.

[0093] For example, such as Figure 5AThe overall framework diagram shown indicates that the clock pass-through control signal is input to the automatic clock gating of communication module A, communication module B, and communication module C, respectively. The automatic clock gating of communication module A controls the clock gating to open or close based on the input signal and the clock before gating, thereby inputting the clock after gating to communication module A. The internal small module of communication module A performs hardware clock gating. The control process of communication modules B and C is the same as that of communication module A.

[0094] In summary, the clock gating control method proposed in this disclosure configures time information containing the communication time range of at least one communication module in at least one communication scenario. This allows the generation of control signals based on a reference clock signal and the time information to control the opening or closing of the clock gating corresponding to at least one communication module. This dynamically controls the transmission of the clock signal of the communication module, achieving accurate clock gating control, improving control flexibility, and further reducing power consumption.

[0095] Furthermore, the clock gating control method proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, and realizes dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification. It is especially suitable for modern communication systems that are sensitive to power consumption and timing.

[0096] Figure 4 This is an architectural diagram of the chip proposed in an embodiment of this disclosure. Chip 400 includes a software control module 410.

[0097] The software control module is connected to at least one gating module 420; the software control module is used to generate control signals based on a reference clock signal and time information, the time information including the communication time range of at least one communication module in at least one communication scenario, and the control signals are used to control the opening or closing of the clock gating corresponding to at least one communication module.

[0098] In some embodiments, at least one gate control module is connected to at least one communication module 430, and the gate control module and the communication module have a one-to-one correspondence.

[0099] In some embodiments, the control signals output by the software control module are output to the corresponding gating module of the communication module to realize the opening or closing of the clock gating in the gating module.

[0100] In some embodiments, the software control module is further configured to: count using a local counter based on a reference clock signal to determine a count value; and generate a control signal based on the count value and time information.

[0101] For example, such as Figure 5AThe diagram shows the overall framework of the control strategy. The software control module is, for example, the software adaptive module in the diagram, and the gating module is, for example, the automatic clock gating module in the diagram.

[0102] In some embodiments, the specific implementation of the software control module generating control signals can be found in [reference needed]. Figure 1 and Figure 2 The embodiments shown are not described in detail here.

[0103] In some embodiments, the first gating module in at least one gating module is used to: determine a level value based on a first control signal of the first communication module; and determine whether the clock gating of the first communication module is turned on or off based on the level value.

[0104] In some embodiments, the first gating module is further configured to: determine a level value as a first value in response to a first control signal being high; and determine a level value as a second value in response to a first control signal being low.

[0105] In some embodiments, the first gating module is further configured to: enable the clock gating corresponding to the first communication module when the level value is a first value, so that a preset clock signal is input to the first communication module; and disable the clock gating corresponding to the first communication module when the level value is a second value.

[0106] In some embodiments, the first gating module is, for example, Figure 5A The automatic clock gating corresponding to communication module A, or communication module B, or communication module C in the overall framework diagram shown.

[0107] In some embodiments, the specific implementation of the first gate control module can be found in [reference needed]. Figure 3 The specific implementation details of the embodiments shown will not be repeated here.

[0108] In summary, the chip described above outputs control signals through a software control module, which then input the generated control signals into the gating modules of the corresponding communication modules. The gating modules judge the control signals to enable or disable clock gating, thereby controlling the input of preset clock signals into the corresponding communication modules. This improves the accuracy and flexibility of control and reduces the overall power consumption of the chip.

[0109] Furthermore, the chip proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, and achieves dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification, making it particularly suitable for modern communication systems that are sensitive to power consumption and timing.

[0110] The following is a specific implementation method of a control strategy using software fitting: This fitting scheme simulates the timing diagram of the hardware module from the upper software layer by controlling the clock gating through the control signal interface, thereby precisely controlling the clock switching of the hardware module at the scene level. Combined with the hardware clock gating scheme inside the hardware module, it saves power consumption.

[0111] Specifically, a penetration control signal was added to the traditional gating module, and a software adaptive module was added to fit the input clock of the hardware accelerator to enable or disable the hardware gating related timing.

[0112] like Figure 5A The diagram shown is an overall framework diagram of the control strategy.

[0113] Module 1 (Software Adaptive Module): The software configuration path configures the event timetable array. The local counter of the software adaptive module counts the general-purpose clock. The event timetable array and the counter output value are input to the pulse output circuit, which outputs a clock pass-through control signal to the automatic clock gating. Each automatic clock gating has a corresponding communication module; that is, the first automatic clock gating corresponds to communication module A, the second to communication module B, and the third to communication module C. The inputs of the automatic clock module are the clock pass-through control signal and the pre-gating clock. The output is the post-gating clock of the corresponding communication module to control the start-up of the hardware accelerator of the subsequent communication module.

[0114] like Figure 5B This is a schematic diagram of the event timeline array for a communication scenario. In communication scenario A, the communication time range of module A is [0, 200], the communication time range of module B is [5, 150], and the communication time range of module C is [20, 100]. In communication scenario B, the communication time range of module A is [250, 300], the communication time range of module B is [205, 350], and the communication time range of module C is [220, 280].

[0115] The software needs to configure an event timetable array into a register based on the actual timing of the communication scenario. It then generates a software-fitted pulse edge using a local counter as a clock pass-through signal, which is output to the automatic clock gating module to activate the corresponding clock-gated accelerator module. Table 1 shows the pass-through results of each module based on the local counter. Only a portion of the counter values ​​are used as examples for illustration.

[0116] Table 1

[0117] like Figure 5C The output timing of the clock pass-through control signal is shown.

[0118] In summary, the beneficial effects of this solution are as follows: 1. Enhanced flexibility: This solution enables continuous optimization during the chip design phase and after the chip is returned to the manufacturer. 2. It can cover the entire scene boundary at the system level; 3. It can simplify the design and verification of hardware clock gating schemes; 4. Reduced power consumption.

[0119] Figure 6 This is a schematic diagram of the structure of a clock gating control device 600 according to an embodiment of this disclosure. Figure 6 As shown, the device includes: The acquisition module 610 is used to acquire time information, which includes the communication time range of at least one communication module in at least one communication scenario. The first control module 620 is used to generate a control signal based on a reference clock signal and time information. The control signal is used to control the opening or closing of the clock gating corresponding to at least one communication module.

[0120] In some embodiments, the first control module is further configured to: count using a local counter based on a reference clock signal to determine a count value; and generate a control signal based on the count value and time information.

[0121] In some embodiments, the first control module is further configured to: determine that the first control signal corresponding to the first communication module is high level in response to the count value being within a first time range of the first communication module; and determine that the first control signal corresponding to the first communication module is low level in response to the count value not being within the first time range of the first communication module.

[0122] In some embodiments, the device further includes a second control module, which is configured to: determine a level value based on a first control signal from the first communication module; and determine whether the clock gating corresponding to the first communication module is turned on or off based on the level value.

[0123] In some embodiments, the second control module is further configured to: determine a level value as a first value in response to a first control signal being high; and determine a level value as a second value in response to a first control signal being low.

[0124] In some embodiments, the second control module is further configured to: enable the clock gating corresponding to the first communication module when the level value is a first value, so that a preset clock signal is input to the first communication module; and disable the clock gating corresponding to the first communication module when the level value is a second value.

[0125] In summary, the clock gating control device proposed in this disclosure, by configuring time information including the communication time range of at least one communication module in at least one communication scenario, can generate a control signal based on the reference clock signal and the time information to control the opening or closing of the clock gating corresponding to at least one communication module, dynamically control the transmission of the clock signal of the communication module, achieve accurate clock gating control, improve control flexibility, and further reduce power consumption.

[0126] Furthermore, the clock gating control method proposed in this disclosure can adapt to the complex timing requirements of multiple communication scenarios, and realizes dynamic power consumption optimization, multi-module timing synchronization, and hardware simplification. It is especially suitable for modern communication systems that are sensitive to power consumption and timing.

[0127] Regarding the clock gating control device in the above embodiments, the specific methods by which each module performs its operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0128] Figure 7 This is a schematic diagram of the structure of an electronic device 700 for implementing the above-described clock gating control method, according to an exemplary embodiment.

[0129] Reference Figure 7 The electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, an input / output (I / O) interface 708, a sensor component 710, and a communication component 712.

[0130] Processing component 702 typically controls the overall operation of electronic device 700, such as operations associated with display, telephone calls, data communication, battery management, and recording. Processing component 702 may include one or more processors 720 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 702 may include one or more modules to facilitate interaction between processing component 702 and other components. For example, processing component 702 may include an equalization module to facilitate interaction between power supply component 706 and processing component 702.

[0131] Memory 704 is configured to store various types of data to support the operation of electronic device 700. Examples of this data include instructions for any application or method operating on electronic device 700, contact data, phonebook data, messages, pictures, videos, etc. Memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0132] Power supply component 706 provides power to various components of electronic device 700. Power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 700.

[0133] I / O interface 708 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0134] Sensor assembly 710 includes one or more sensors for providing state assessments of various aspects of electronic device 700. For example, sensor assembly 710 can detect the on / off state of electronic device 700, the relative positioning of components such as the display and keypad of electronic device 700, changes in position of electronic device 700 or a component of electronic device 700, the presence or absence of user contact with electronic device 700, orientation or acceleration / deceleration of electronic device 700, and temperature changes of electronic device 700. Sensor assembly 710 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 710 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications.

[0135] In some embodiments, the sensor assembly 710 may further include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0136] Communication component 712 is configured to facilitate wired or wireless communication between electronic device 700 and other devices. Electronic device 700 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 712 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 712 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0137] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0138] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, which can be executed by a processor 720 of an electronic device 700 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0139] This disclosure also provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the steps of the clock gating control method provided in this disclosure.

[0140] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the clock gating control method described in the above embodiments of this disclosure.

[0141] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0142] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0143] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0144] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0145] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0146] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0147] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0148] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0149] It should be understood that various parts of the embodiments of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0150] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0151] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The aforementioned storage medium can be a read-only memory, a hard disk, or an optical disk, etc.

[0152] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A clock gating control method, characterized in that, The method includes: Obtain time information, the time information including the communication time range of at least one communication module in at least one communication scenario; Based on the reference clock signal and the time information, a control signal is generated, which is used to control the opening or closing of the clock gating corresponding to the at least one communication module.

2. The method according to claim 1, characterized in that, The generation of control signals based on the reference clock signal and the time information includes: Based on the reference clock signal, a local counter is used to count and determine the count value; The control signal is generated based on the count value and the time information.

3. The method according to claim 2, characterized in that, The step of generating the control signal based on the count value and the time information includes: In response to the count value being within a first time range of the first communication module, the first control signal corresponding to the first communication module is determined to be high level; In response to the count value not being within the first time range of the first communication module, the first control signal corresponding to the first communication module is determined to be low.

4. The method according to claim 3, characterized in that, The method further includes: The voltage level is determined based on the first control signal from the first communication module. Based on the level value, determine whether the clock gating of the first communication module is turned on or off.

5. The method according to claim 4, characterized in that, Determining the level value based on the first control signal of the first communication module includes: In response to the first control signal being high, the level value is determined to be a first value; In response to the first control signal being low, the level value is determined to be a second value.

6. The method according to claim 5, characterized in that, The step of determining whether the clock gating of the first communication module is turned on or off based on the level value includes: When the level value is the first value, the clock gating corresponding to the first communication module is activated so that a preset clock signal is input to the first communication module. When the level value is the second value, the clock gating corresponding to the first communication module is turned off.

7. A chip, characterized in that, The chip includes a software control module. The software control module is connected to at least one gating module; The software control module is used to generate control signals based on a reference clock signal and time information. The time information includes the communication time range of at least one communication module in at least one communication scenario. The control signals are used to control the opening or closing of the clock gating corresponding to the at least one communication module.

8. The chip according to claim 7, characterized in that, The at least one gate control module is connected to the at least one communication module, and there is a one-to-one correspondence between the gate control module and the communication module.

9. The chip according to claim 7, characterized in that, The software control module is also used for: Based on the reference clock signal, a local counter is used to count and determine the count value; The control signal is generated based on the count value and the time information.

10. The chip according to claim 9, characterized in that, The first gate module in the at least one gate module is used for: The voltage level is determined based on the first control signal from the first communication module. Based on the level value, determine whether the clock gating of the first communication module is turned on or off.

11. The chip according to claim 10, characterized in that, The first gating module is also used for: In response to the first control signal being high, the level value is determined to be a first value; In response to the first control signal being low, the level value is determined to be a second value.

12. The chip according to claim 11, characterized in that, The first gating module is also used for: When the level value is the first value, the clock gating corresponding to the first communication module is activated so that a preset clock signal is input to the first communication module. When the level value is the second value, the clock gating corresponding to the first communication module is turned off.

13. A clock gating control device, characterized in that, include: An acquisition module is used to acquire time information, the time information including the communication time range of at least one communication module in at least one communication scenario; The first control module is used to generate a control signal based on a reference clock signal and the time information, the control signal being used to control the opening or closing of the clock gating corresponding to the at least one communication module.

14. The clock gating control device according to claim 13, characterized in that, The first control module is also used for: Based on the reference clock signal, a local counter is used to count and determine the count value; The control signal is generated based on the count value and the time information.

15. The clock gating control device according to claim 14, characterized in that, The first control module is also used for: In response to the count value being within a first time range of the first communication module, the first control signal corresponding to the first communication module is determined to be high level; In response to the count value not being within the first time range of the first communication module, the first control signal corresponding to the first communication module is determined to be low.

16. The clock gating control device according to claim 15, characterized in that, The device further includes a second control module, the second control module being used for: The voltage level is determined based on the first control signal from the first communication module. Based on the level value, the clock gating corresponding to the first communication module is turned on or off, so that a preset clock signal is input to the first communication module.

17. An electronic device, characterized in that, include: A processor and a memory for storing a computer program capable of running on the processor, wherein, when the processor is used to run the computer program, it performs the method of any one of claims 1-6, or includes the clock gating control device of any one of claims 13-16.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

19. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method as described in any one of claims 1-6.

Images