PLC system power failure data emergency storage method, system, device and medium

Abstract

The invention discloses a PLC (Programmable Logic Controller) system power failure data emergency storage method, system, equipment and medium, and particularly relates to the technical field of industrial data storage, the technical key points are as follows: a CPU (Central Processing Unit) control unit reads and obtains a current capacitor voltage value from a capacitor electric quantity detection circuit, calculates and obtains system remaining time according to the current capacitor voltage value, and sends the system remaining time to a PLC control unit; judging whether the estimated write-in time of the current to-be-stored data packet with the highest priority meets a write-in condition or not; if the estimated write-in time of the current to-be-stored data packet with the highest priority meets a first write-in condition, an EMMC rapid write-in command is sent to the EMMC, the EMMC controller reads the to-be-stored data packet from the DDR and writes the to-be-stored data packet into an EMMC physical block, and whether the estimated write-in time of the next to-be-stored data packet with the highest priority meets the write-in condition or not is continuously judged after write-in; and the pre-estimated write-in time of the next to-be-stored data packet with the highest priority does not meet the write-in condition until all the to-be-stored data packets are written into the EMMC.

Description

Technical Field

[0001] This invention relates to the field of industrial data storage technology, specifically to a method, system, device, and medium for emergency data storage in a PLC system during power failure. Background Technology

[0002] PLCs are the main controller devices in industrial automation, and are commonly used in the control of equipment in industrial manufacturing, aviation, power and other fields. They use programmable controllers to execute logic operations, timing, motion control and other operation instructions internally. During operation, a large amount of real-time data is exchanged in volatile memory.

[0003] In existing PLC solutions, to prevent data loss due to abnormal power outages, the PLC writes critical real-time data into non-volatile memory (FREM / EMMC) in real time; however, existing solutions have the following drawbacks:

[0004] 1. Non-volatile memory FREM / EMMC is refreshed frequently during operation, which leads to reduced product reliability and lifespan;

[0005] 2. There is no distinction between different regions and storage priorities between the DDR and eMMC memory. Abnormal power failures cause data to be written to the eMMC indiscriminately, resulting in low efficiency of effective data storage.

[0006] 3. Data storage does not differentiate between priorities, and data priorities are not linked to the health status of the backup power supply.

[0007] Therefore, the present invention provides a method, system, device and medium for emergency storage of PLC system data in the event of power failure, in order to solve the aforementioned problems. Summary of the Invention

[0008] The technical problem this invention aims to solve is that there is no distinction between different regions and storage priorities between the DDR and eMMC memory. Abnormal power failures cause data to be written to the eMMC indiscriminately, resulting in low efficiency of effective data storage. The purpose is to provide a method, system, device, and medium for emergency data storage in PLC systems during power failures. Through the technical means of coordinated emergency data storage between DDR and eMMC, when the main power supply fails, the system is triggered to enter an emergency state. Within the limited time provided by the supercapacitor, the most critical data packets are saved from the volatile DDR to the non-volatile eMMC according to data priority. At the same time, the estimated write time of the highest priority data packet to be saved is compared with the remaining system time, and the highest priority data packet that meets the write time requirement is stored in the eMMC first, thereby efficiently storing critical data in an emergency.

[0009] This invention is achieved through the following technical solution:

[0010] A method for emergency data storage in a PLC system during power failure, the method comprising:

[0011] After the power failure detection circuit detects that the main power supply voltage has reached the preset power failure condition, it sends an interrupt signal to the CPU control unit. The CPU control unit responds to the interrupt signal and starts the emergency save program.

[0012] After the emergency save procedure is initiated, the CPU control unit obtains the priority list of data to be saved from the data management server, and reads the corresponding data from the specified address of DDR according to the list of data to be saved, and packages it to obtain multiple data packets to be saved with different priorities.

[0013] Determine whether the estimated write time of the highest priority data packet to be saved meets the write conditions; wherein, the write conditions include a first write condition and a second write condition;

[0014] If the estimated write time of the highest priority data packet to be saved meets the first write condition, an EMMC fast write command is sent to the EMMC. The EMMC controller reads the data packet to be saved from the DDR and writes it to the EMMC physical block. After writing, it continues to determine whether the estimated write time of the next highest priority data packet to be saved meets the write condition. This continues until all data packets to be saved are written to the EMMC, or the estimated write time of the next highest priority data packet to be saved does not meet the write condition.

[0015] If the estimated write time of the highest priority data packet to be saved meets the second write condition, then an EMMC fast write command is sent to the EMMC. The EMMC controller reads the data packet to be saved from the DDR and writes it into the EMMC physical block, and then directly enters the system shutdown procedure after writing.

[0016] If the estimated write time of the highest priority data packet to be saved does not meet the write conditions, the system will directly enter the shutdown process.

[0017] Furthermore, after the power failure detection circuit detects that the main power supply voltage has reached the preset power failure condition and sends an interrupt signal to the CPU control unit, the method also includes:

[0018] The CPU control unit suspends all currently running tasks based on the interrupt signal and sends an interrupt mask register setting command to the interrupt controller; the interrupt controller responds to the interrupt mask register setting command and masks all non-critical interrupts; wherein, the non-critical interrupts refer to interrupt tasks with lower priority;

[0019] The CPU control unit sends critical contents from the registers to a specific secure area in the DDR;

[0020] The CPU control unit sends a DMA stop command to the DMA controller, which then suspends all external data transfer tasks.

[0021] Furthermore, the priority list of data to be saved includes the location of the data to be saved, the size of the data to be saved, and the priority of the data to be saved.

[0022] Furthermore, before determining whether the estimated write time of the highest priority data packet to be saved meets the write condition, the method also includes:

[0023] The remaining capacitor voltage of the supercapacitor backup power supply is monitored in real time by a capacitor power detection circuit. The CPU control unit reads the current capacitor voltage value from the capacitor power detection circuit and calculates the remaining system time based on the current capacitor voltage value.

[0024] Furthermore, the first write condition is that the difference between the estimated write time of the data packet to be saved and the remaining system time is greater than a first time threshold; the second write condition is that the difference between the estimated write time of the data packet to be saved and the remaining system time is between the first time threshold and the second time threshold; wherein, the first time threshold is greater than the second time threshold.

[0025] Furthermore, the first time threshold is 100ms, and the second time threshold is 30ms.

[0026] The present invention also provides a PLC system power failure data emergency storage system, which is used in the PLC system power failure data emergency storage method described in any one of the above claims, the system comprising:

[0027] The power failure detection circuit is used to monitor whether the main power supply voltage has reached the preset power failure condition and send an interrupt signal to the CPU control unit.

[0028] The CPU control unit is used to start the emergency save program in response to the interrupt signal, obtain the priority list of data to be saved from the data management server, and read the corresponding data from the specified address of DDR according to the list of data to be saved, package it, and obtain multiple data packets to be saved with different priorities.

[0029] It is also used to read the current capacitor voltage value from the capacitor charge detection circuit, calculate the remaining system time based on the current capacitor voltage value, and determine whether the difference between the estimated write time of the highest priority data packet to be saved and the remaining system time meets the write condition; if the write condition is met, an EMMC fast write command is sent to the EMMC.

[0030] It is also used to determine whether the estimated write time of the highest priority data packet to be saved meets the write condition; if the estimated write time of the highest priority data packet to be saved meets the first write condition, an EMMC fast write command is sent to the EMMC, and after writing, it continues to determine whether the estimated write time of the next highest priority data packet to be saved meets the write condition; until all data packets to be saved are written to the EMMC, or the estimated write time of the next highest priority data packet to be saved does not meet the write condition; if the estimated write time of the highest priority data packet to be saved meets the second write condition, an EMMC fast write command is sent to the EMMC, and after writing, the system shutdown procedure is entered directly; if the estimated write time of the highest priority data packet to be saved does not meet the write condition, the system shutdown procedure is entered directly.

[0031] Supercapacitor backup power supply is used to provide power support after the PLC system loses power;

[0032] The capacitor charge detection circuit is used to detect the current capacitor voltage value of the supercapacitor backup power supply and send the detected current capacitor voltage value to the CPU control unit.

[0033] The present invention also provides a computer device, including a system memory and a processor, wherein the system memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described above.

[0034] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the methods described above.

[0035] The present invention also provides a computer program product containing instructions that, when executed by a cluster of computer devices, cause the cluster of computer devices to perform the method described in any of the preceding claims.

[0036] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0037] In this invention, by using the technical means of emergency data storage in collaboration between DDR and EMMC, when the main power supply fails, the system is triggered to enter an emergency state. Within the limited time provided by the supercapacitor, the most critical data packets are saved from the volatile DDR to the non-volatile EMMC according to data priority. At the same time, the estimated write time of the highest priority data packet to be saved is judged with the remaining system time, and the highest priority data packet that meets the write time requirement is stored in the EMMC first, thereby efficiently storing critical data in an emergency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0039] Figure 1 For existing PLC system storage systems;

[0040] Figure 2 This is a schematic diagram of the module connection of a PLC system power failure emergency data storage system in this embodiment;

[0041] Figure 3 This is a flowchart illustrating a method for emergency data storage in a PLC system during power failure, as described in this embodiment.

[0042] Figure 4 This is a schematic diagram of the structure of a computer device in this embodiment. Detailed Implementation

[0043] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0044] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0045] The terminology used in the description of the various examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0046] Example 1

[0047] As described in the background section, see [link to background section]. Figure 1 , Figure 1This paper illustrates a prior art PLC system storage system. To prevent data loss during abnormal power outages, existing solutions store real-time data in non-volatile memory (NRAM). Due to the very high data refresh rate, expensive, highly reliable, and high-refresh-rate FRAM must be used. Even with FRAM, its theoretical lifespan is only 1-2 years. Therefore, this approach presents significant challenges in terms of reliability, lifespan, and cost, which is a major pain point preventing the significant increase in non-volatile data storage capacity in PLCs. Based on these shortcomings, this paper offers the following technical solution:

[0048] See Figure 2 , Figure 2 A schematic diagram of the module connection of a PLC system power failure data emergency storage system is shown. The system includes a supercapacitor backup power supply, a power failure detection circuit, and a capacitor charge detection circuit. The supercapacitor backup power supply is connected to an external power input to provide power support after the PLC system loses power. At the same time, under normal operating conditions, the external power input first charges the supercapacitor backup power supply, and then supplies power to subsequent modules through the supercapacitor backup power supply.

[0049] The output of the supercapacitor backup power supply is connected to a power management integrated circuit (PMIC). The PMIC is connected to each module unit and is used to transmit the working power supply voltage to each module unit. It is also used to detect the current capacitor voltage value of the supercapacitor backup power supply. The PMIC is also connected to the CPU control unit through the IIC bus and sends the detected current capacitor voltage value to the CPU control unit.

[0050] The CPU control unit is connected to the DDR via a DDR bus, to the eMMC via a bus interface, to the FRAM via an SPI bus, and to the peripheral interface via a peripheral interface bus. Simultaneously, one end of the power failure detection circuit is connected to the input of an external power supply, and the other end is connected to the CPU control unit. One end of the capacitor charge detection circuit is connected to the supercapacitor backup power supply, and the other end is connected to the CPU control unit. This system is used in any of the above-described PLC system power failure data emergency storage methods, see [link to relevant documentation]. Figure 3 , Figure 3 A flowchart illustrating a method for emergency data storage in a PLC system during power failure is shown, wherein the method includes:

[0051] S1: After the power failure detection circuit detects that the main power supply voltage has reached the preset power failure condition, it sends an interrupt signal to the CPU control unit. The CPU control unit responds to the interrupt signal and starts the emergency save program.

[0052] Specifically, in this embodiment, when the power failure detection circuit detects that the main power supply voltage is lower than a preset voltage threshold, indicating an external power supply failure, it sends an interrupt signal to a specific high-priority pin of the CPU control unit. Upon receiving the interrupt signal, the CPU control unit suspends all currently running tasks and sends an interrupt mask register setting command to the interrupt controller. The interrupt controller responds to the interrupt mask register setting command by masking all non-critical interrupts. Herein, non-critical interrupts refer to interrupt tasks with lower priority. Simultaneously, the CPU control unit also sends the critical contents of the register to a specific secure area in the DDR. At the same time, the CPU control unit also sends a DMA stop command to the DMA controller, which suspends all external data transfer tasks. Thus, the system state is instantly frozen and preserved, creating a stable environment for emergency data preservation.

[0053] It should be noted that in this embodiment, the preset voltage threshold is determined according to the actual situation and is not subject to much restriction here; at the same time, the specific security area in DDR is pre-built, and the construction of the specific security area is a conventional technical means in the field, which will not be described in detail here.

[0054] S2: After the emergency save procedure is started, the CPU control unit obtains the priority list of data to be saved from the data management server, and reads the corresponding data from the specified address of DDR according to the list of data to be saved, and packages it to obtain multiple data packets to be saved with different priorities.

[0055] Specifically, in this embodiment, after the emergency save procedure is initiated, the CPU control unit sends a query request to the data management server. Upon responding to the query request, the data management server sends a priority list of data to be saved to the CPU control unit. This priority list includes the location, size, and priority of the data to be saved. The data to be saved refers to critical data that has been modified in the DDR cache, is inconsistent with the eMMC persistent storage, and faces the risk of loss due to power failure. The CPU control unit reads the corresponding data from the specified address in the DDR cache according to the list, adds header information such as checksum, data type, and timestamp, and packages the corresponding data and header information into a packet area in the DDR cache. This organizes the scattered data into continuous data packets with metadata, facilitating fast and reliable data packet writing. Simultaneously, the priority of the data packets to be saved is determined based on the priority of the saved data.

[0056] S3: Determine whether the estimated write time of the highest priority data packet to be saved meets the write conditions; wherein, the write conditions include a first write condition and a second write condition; if the estimated write time of the highest priority data packet to be saved meets the first write condition, then send an EMMC fast write command to the EMMC, the EMMC controller reads the data packet to be saved from the DDR and writes it to the EMMC physical block, and after writing, continue to determine whether the estimated write time of the next highest priority data packet to be saved meets the write conditions; until all data packets to be saved are written to the EMMC, or the estimated write time of the next highest priority data packet to be saved does not meet the write conditions;

[0057] If the estimated write time of the highest priority data packet to be saved meets the second write condition, then an EMMC fast write command is sent to the EMMC. The EMMC controller reads the data packet to be saved from the DDR and writes it into the EMMC physical block, and then directly enters the system shutdown procedure after writing.

[0058] If the estimated write time of the highest priority data packet to be saved does not meet the write conditions, the system will directly enter the shutdown process.

[0059] It should be noted that, in this embodiment, the first writing condition is that the difference between the estimated writing time of the data packet to be saved and the remaining system time is greater than the first time threshold; the second writing condition is that the difference between the estimated writing time of the data packet to be saved and the remaining system time is between the first time threshold and the second time threshold; at the same time, in this embodiment, the first time threshold is 100ms and the second time threshold is 30ms. Other time thresholds can also be used in other embodiments, which will not be elaborated on here.

[0060] Specifically, in this embodiment, the capacitor power detection circuit detects the capacitor voltage value of the supercapacitor backup power supply in real time. The CPU control unit reads the current capacitor voltage value from the capacitor power detection circuit, then converts the current capacitor voltage value into the remaining capacitor power value, and uses the remaining capacitor power value to calculate the remaining system time.

[0061] Then, the system will start judging from the highest priority data packet to be saved. If the estimated write time of the highest priority data packet to be saved meets the first write condition, then the system will send an EMMC fast write command to the EMMC. The EMMC controller will read the data packet to be saved from the DDR and write it into the EMMC physical block. After writing, the system will continue to judge whether the estimated write time of the next highest priority data packet to be saved meets the write condition.

[0062] If the estimated write time of the highest priority data packet to be saved meets the second write condition, then an EMMC fast write command is sent to the EMMC. The EMMC controller reads the data packet to be saved from the DDR and writes it into the EMMC physical block. After writing, it directly enters the system shutdown program and no longer checks whether the next data packet to be saved meets the write condition.

[0063] If the estimated write time of the highest priority data packet to be saved does not meet the write conditions, that is, it does not meet either the first write adjustment or the second write condition, then the system will directly close the program and will not perform a write operation on the data packet to be saved.

[0064] It should also be noted that the capacitor voltage may fluctuate during the data packet writing process, which may cause the data to fail to write. If the write failure is recoverable, try to rewrite; if the error is not recoverable, discard the data packet directly.

[0065] Specifically, in this embodiment, through the technical means of emergency data storage in collaboration between DDR and EMMC, when the main power supply fails, the system is triggered to enter an emergency state. Within the limited time provided by the supercapacitor, the most critical data packets are saved from the volatile DDR to the non-volatile EMMC according to data priority. At the same time, the estimated write time of the highest priority data packet to be saved is compared with the remaining system time, and the highest priority data packet that meets the write time requirement is stored in the EMMC first, thereby efficiently storing critical data in an emergency.

[0066] Example 2

[0067] See Figure 4 This embodiment also provides a computer device, including a system memory 1005 and a processor 1001. The system memory 1005 stores a computer program, and the processor 1001 executes the computer program to implement the steps of any of the methods described above.

[0068] It should be noted that the processor 1001 is used to execute the steps in the above method embodiments according to the instructions in the program code. Alternatively, when the processor 1001 executes the computer program, it implements the functions of each module / unit in the above system / device embodiments.

[0069] Specifically, in this embodiment, the computer program can be divided into one or more modules / units. One or more modules / units are stored in the system memory 1005 and executed by the processor 1001 to complete this application. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the terminal device.

[0070] The terminal device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor 1001 and a system memory 1005. Those skilled in the art will understand that this does not constitute a limitation on the terminal device, which may include more or fewer components than shown, or a combination of certain components, or different components. For example, the terminal device may also include an input / output device 1003, a network access device 1002, a bus 1006, etc.

[0071] The processor 1001 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0072] System memory 1005 can be an internal storage unit of the terminal device, such as a hard drive or RAM. System memory 1005 can also be a storage device 1004 of the terminal device, such as an external hard drive, SmartMedia Card (SMC), Secure Digital (SD) card, or FlashCard. Furthermore, system memory 1005 can include both internal storage units and storage device 1004. System memory 1005 is used to store computer programs and other programs and data required by the terminal device. System memory 1005 can also be used to temporarily store data that has been output or will be output.

[0073] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0074] Example 3

[0075] This embodiment provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0076] The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), registers, hard disks, optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof, or any other form of computer-readable storage medium in the art.

[0077] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside within an application-specific integrated circuit (ASIC). In embodiments of the invention, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device.

[0078] Example 4

[0079] This embodiment also provides a computer program product containing instructions that, when executed by a cluster of computer devices, cause the cluster of computer devices to perform the method described in Embodiment 1.

[0080] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for emergency data storage in a PLC system during power failure, characterized in that, The methods include: After the power failure detection circuit detects that the main power supply voltage has reached the preset power failure condition, it sends an interrupt signal to the CPU control unit. The CPU control unit responds to the interrupt signal and starts the emergency save program. After the emergency save procedure is initiated, the CPU control unit obtains the priority list of data to be saved from the data management server, and reads the corresponding data from the specified address of DDR according to the list of data to be saved, and packages it to obtain multiple data packets to be saved with different priorities. Determine whether the estimated write time of the highest priority data packet to be saved meets the write conditions; wherein, the write conditions include a first write condition and a second write condition; If the estimated write time of the highest priority data packet to be saved meets the first write condition, an EMMC fast write command is sent to the EMMC. The EMMC controller reads the data packet to be saved from the DDR and writes it to the EMMC physical block. After writing, it continues to determine whether the estimated write time of the next highest priority data packet to be saved meets the write condition. This continues until all data packets to be saved are written to the EMMC, or the estimated write time of the next highest priority data packet to be saved does not meet the write condition. If the estimated write time of the highest priority data packet to be saved meets the second write condition, then an EMMC fast write command is sent to the EMMC. The EMMC controller reads the data packet to be saved from the DDR and writes it into the EMMC physical block, and then directly enters the system shutdown procedure after writing. If the estimated write time of the highest priority data packet to be saved does not meet the write conditions, the system will directly enter the shutdown process.

2. The method for emergency data storage in a PLC system during power failure according to claim 1, characterized in that, After the power failure detection circuit detects that the main power supply voltage has reached the preset power failure condition and sends an interrupt signal to the CPU control unit, the method further includes: The CPU control unit suspends all currently running tasks based on the interrupt signal and sends an interrupt mask register setting command to the interrupt controller; the interrupt controller responds to the interrupt mask register setting command and masks all non-critical interrupts; wherein, the non-critical interrupts refer to interrupt tasks with lower priority; The CPU control unit sends critical contents from the registers to a specific secure area in the DDR; The CPU control unit sends a DMA stop command to the DMA controller, which then suspends all external data transfer tasks.

3. The method for emergency data storage in a PLC system during power failure according to claim 1, characterized in that, The priority list of data to be saved includes the location of the data to be saved, the size of the data to be saved, and the priority of the data to be saved.

4. The method for emergency data storage in a PLC system during power failure according to claim 1, characterized in that, Before determining whether the estimated write time of the highest priority data packet to be saved meets the write conditions, the method also includes: The remaining capacitor voltage of the supercapacitor backup power supply is monitored in real time by a capacitor power detection circuit. The CPU control unit reads the current capacitor voltage value from the capacitor power detection circuit and calculates the remaining system time based on the current capacitor voltage value.

5. A method for emergency data storage in a PLC system during power failure according to claim 4, characterized in that, The first write condition is that the difference between the estimated write time of the data packet to be saved and the remaining system time is greater than a first time threshold; the second write condition is that the difference between the estimated write time of the data packet to be saved and the remaining system time is between a first time threshold and a second time threshold; wherein, the first time threshold is greater than the second time threshold.

6. The method for emergency data storage in a PLC system during power failure according to claim 5, characterized in that, The first time threshold is 100ms, and the second time threshold is 30ms.

7. A PLC system power failure emergency data storage system, characterized in that, This system is used in the emergency data storage method for a PLC system in the event of power failure as described in any one of claims 1-6, wherein the system comprises: The power failure detection circuit is used to monitor whether the main power supply voltage has reached the preset power failure condition and send an interrupt signal to the CPU control unit. The CPU control unit is used to start the emergency save program in response to the interrupt signal, obtain the priority list of data to be saved from the data management server, and read the corresponding data from the specified address of DDR according to the list of data to be saved, package it, and obtain multiple data packets to be saved with different priorities. It is also used to read the current capacitor voltage value from the capacitor charge detection circuit, calculate the remaining system time based on the current capacitor voltage value, and determine whether the difference between the estimated write time of the highest priority data packet to be saved and the remaining system time meets the write condition; if the write condition is met, an EMMC fast write command is sent to the EMMC. It is also used to determine whether the estimated write time of the highest priority data packet to be saved meets the write condition; if the estimated write time of the highest priority data packet to be saved meets the first write condition, an EMMC fast write command is sent to the EMMC, and after writing, it continues to determine whether the estimated write time of the next highest priority data packet to be saved meets the write condition; until all data packets to be saved are written to the EMMC, or the estimated write time of the next highest priority data packet to be saved does not meet the write condition; if the estimated write time of the highest priority data packet to be saved meets the second write condition, an EMMC fast write command is sent to the EMMC, and after writing, the system shutdown procedure is entered directly; if the estimated write time of the highest priority data packet to be saved does not meet the write condition, the system shutdown procedure is entered directly. Supercapacitor backup power supply is used to provide power support after the PLC system loses power; The capacitor charge detection circuit is used to detect the current capacitor voltage value of the supercapacitor backup power supply and send the detected current capacitor voltage value to the CPU control unit.

8. A computer device comprising a system memory and a processor, wherein the system memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 6.

10. A computer program product containing instructions, characterized in that, When the instructions are executed by a cluster of computer devices, the cluster of computer devices causes the cluster of computer devices to perform the method as described in any one of claims 1 to 6.

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