Mean addition calculation device and method based on random calculation

Abstract

The invention provides a mean value addition calculation device and method based on random calculation, and belongs to the field of integrated circuit design. The device comprises a random bit stream generation unit, a DD-MAX unit and a mean value addition units, the mean value addition unit comprises two AND gates and an OR gate, and the output ends of the two AND gates in the mean value addition unit are respectively connected with the two input ends of the OR gate; the division series n of the mean value addition unit is calculated, and X represents the number of binary numbers to be calculated; dividing the mean value addition unit into n levels of mean value addition units; the n levels of mean value addition units are called a first-level mean value addition unit, a second-level mean value addition unit,..., and an n-level mean value addition unit respectively. When the mean value addition calculation device is used for carrying out mean value addition calculation, the obtained MSE is low, and it is indicated that the mean value addition calculation device can have high calculation precision.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and is a mean addition calculation device and method based on random calculation. Background Technology

[0002] With the rise of new technologies such as big data, cloud computing, and the Internet of Things (IoT), the interaction between computer systems and the physical world is becoming increasingly frequent, and the amount of information to be processed is growing exponentially. Computer systems have shifted from "simply processing massive amounts of data" to "processing massive amounts of data with high precision"—whether it's industrial parameters collected by IoT sensors, scientific simulations supported by cloud computing, or physiological signals generated by edge devices, all place stringent demands on computational accuracy. Therefore, improving the accuracy of random computation has become a key focus for researchers. Adders are the cornerstone of complex computations; for example, multiplication relies on iterative accumulation of addition, convolution is essentially a weighted combination of multiple input additions, and polynomial solving requires merging polynomials through addition. Therefore, a mean addition computation device (i.e., adder) based on random computation directly affects the accuracy of subsequent operations. However, most existing mean addition computation devices (i.e., adders) based on random computation suffer from low accuracy. To address this, this embodiment proposes a mean addition computation device and method based on random computation. Summary of the Invention

[0003] To address the above problems, the present invention provides a mean addition calculation device and method based on random calculation.

[0004] The technical solution of this invention is as follows: A mean addition calculation device based on random computation includes a random bitstream generation unit, a DD-MAX unit, and... a The unit includes a mean addition unit; the random bit stream generation unit includes a first counter and a comparator, the number of comparators being the same as the number of binary numbers to be calculated, X. The mean addition unit includes two AND gates and one OR gate. The outputs of the two AND gates in the mean addition unit are respectively connected to the two inputs of the OR gate in the mean addition unit. Calculate the number of division levels for the mean addition unit. n , , X Indicates the number of binary numbers to be calculated; a The mean addition unit is divided into n levels of mean addition units; n The mean addition units at each level are respectively called the first-level mean addition unit, the second-level mean addition unit, ..., the nth-level mean addition unit; When the number of binary numbers to be calculated, X=2, n=1 and a=1. The outputs of the two comparators in the random bit stream generation unit are respectively connected to the first inputs of the two AND gates in the first-stage average addition unit; the second inputs of the two AND gates in the first-stage average addition unit are also respectively connected to the least significant bit D flip-flop in the first counter. D 1 of End and Connect the ends to obtain a periodic bit stream with a numerical equivalent of 0.5; When the number of binary numbers to be calculated X≥4, n≥2, the outputs of the X comparators in the random bit stream generation unit are respectively connected to the first input of the AND gate in different first-stage average addition units; the least significant bit D flip-flop in the first counter... D 1 of Q End and Each terminal is connected to the second input terminal of two AND gates in each first-level average addition unit; two first-level average addition units form a group, and the output terminal of a group of first-level average addition units is connected to the first input terminal of two AND gates in a second-level average addition unit, and the flip-flop in the first counter... D 2 of Q End and Each terminal is connected to the second input terminal of the two AND gates in each of the two second-stage mean-adding units; and so on, until the output terminal of each of the two (n-1)-stage mean-adding units is connected to the first input terminal of the two AND gates in the n-stage mean-adding unit, and the trigger in the first counter... D n of Q End and The terminals are respectively connected to the second input terminals of two AND gates in the n-stage mean addition unit; The outputs of all comparators are connected to the input ports of the DD-MAX unit; the outputs of the mean addition unit and the DD-MAX unit are connected to the input and enable terminals of the second counter, respectively; the second counter outputs the mean addition calculation result.

[0005] Preferably, the DD-MAX unit includes a The number of OR gates is the same as the number of mean addition units.

[0006] Preferably, when X=2, n=1 and a=1, all mean addition units are treated as one level of mean addition unit, i.e., first-level mean addition unit.

[0007] Preferably, when X=4, n=2 and a=3, the three mean addition units are divided into two levels of mean addition units: a first-level mean addition unit and a second-level mean addition unit. The first-level and second-level mean addition units are formed by dividing the three mean addition units according to the ratio of the number of mean addition units. : It is obtained by dividing it into proportions.

[0008] Preferably, when X≥8, the mean addition unit is divided into n levels of mean addition units; the n levels of mean addition units are respectively called first-level mean addition units, second-level mean addition units, ..., n-level mean addition units; the first-level to n-level mean addition units are formed by dividing all mean addition units according to the ratio of the number of mean addition units. : :...... It is obtained by dividing it into proportions.

[0009] Preferably, when X=2, a=1; when X=4, a=3; when X≥8, the number of mean addition units is... .

[0010] Preferably, when the number of binary numbers to be calculated, X, is 2, then n = 1. a =1, the output of the comparator in the random bit stream generation unit is connected to the first input of the two AND gates in the first-stage average addition unit; the other input of the two AND gates in the first-stage average addition unit is also connected to the least significant bit in the first counter. D trigger D 1 of Q End and Terminal connection.

[0011] Preferably, when the number of binary numbers to be calculated, X=4, then n=2 and a=3. The output of the comparator in the random bit stream generation unit is connected to the first input of the AND gate in different first-stage average addition units; the second input of one of the AND gates in each first-stage average addition unit is connected to a flip-flop. D 1 of Q In each first-level mean addition unit, the second input of another AND gate is connected to a flip-flop. D 1 of The outputs of both first-level mean-adding units are connected to the inputs of two AND gates in the second-level mean-adding unit. The other input of one of the AND gates in the second-level mean-adding unit is connected to a flip-flop. D 2 of QThe other input of another AND gate in the second-level average adder unit is connected to a flip-flop. D 2 of end.

[0012] Preferably, when the number of binary numbers to be calculated, X ≥ 8, then n ≥ 3. The output of the comparator in the random bit stream generation unit is connected to the first input of the AND gate in different first-stage average addition units; the second input of one of the AND gates in each first-stage average addition unit is connected to a flip-flop. D 1 of In each first-level mean addition unit, the second input of another AND gate is connected to a flip-flop. D 1 of The outputs of the two first-level mean-adding units are respectively connected to the first inputs of two AND gates in a second-level mean-adding unit. The other input of one of the AND gates in each second-level mean-adding unit is connected to a flip-flop. D 2 of Q At the other input of each AND gate in the second-level mean addition unit, a flip-flop is connected. D 2 of The process continues until the outputs of the two (n-1)-stage mean-adding units are connected to the first inputs of the two AND gates in the n-stage mean-adding unit, and the other input of one of the AND gates in the n-stage mean-adding unit is connected to a flip-flop. D n of Q The other input of another AND gate in the n-stage mean adder unit is connected to a flip-flop. D n of end.

[0013] Preferably, the first input terminal of each comparator serves as the external signal input terminal of the mean addition calculation device based on random calculation of this application, and is used to input the binary number to be calculated; the second input port of each comparator is connected to all the flip-flop Q terminals of the first counter in a bit-by-bit correspondence, and is used to access the corresponding bits of the incrementing binary sequence output by the first counter.

[0014] A calculation method for a mean addition calculation device based on random calculation, wherein the mean addition calculation device based on random calculation is the aforementioned mean addition calculation device based on random calculation, and the calculation method for the mean addition calculation device based on random calculation includes the following steps: S1. The first counter in the random bit stream generation unit generates a random number source and transmits the bits to the comparators respectively, so that all comparators share the random number source; S2. Input the binary number to be calculated into the comparator respectively; the comparator compares the digital signal output from the first counter with the digital signal input from the first input terminal of the comparator. When the digital signal input from the first input terminal of the comparator is greater than the binary digital signal output from the first counter, the comparator outputs bit "1"; when the digital signal input from the first input terminal of the comparator is less than the binary digital signal output from the first counter, the comparator outputs bit "0". S3. Perform mean addition calculation using the mean addition unit; S4. The second counter receives the bits output by the n-stage average addition unit and the DD-MAX unit. When the second counter detects that the bit output by the DD-MAX unit is "0", the second counter terminates the calculation of the subsequent output bits of the n-stage average addition unit and obtains the average addition calculation result.

[0015] Preferably, step S3 specifically includes the following steps: when n=1, the mean addition calculation is performed using the first-level mean addition unit; when n is greater than or equal to 2, the mean addition calculation is performed sequentially using the first-level mean addition unit to the nth-level mean addition unit.

[0016] Compared with the prior art, the beneficial technical effects of this application are as follows: Since this application uses a counter as the random number source, from the perspective of all clock cycles, the Q output of each flip-flop of the counter and The bit streams output from each terminal have the maximum negative correlation, and the Q-terminus of each flip-flop and The bit streams output by each terminal are periodic bit streams with an equivalent value of 0.5. These bit streams are used to perform addition operations based on the logic gates in the mean addition unit, which makes this application have better accuracy. Moreover, when using this application to perform mean addition calculation on multiple binary numbers to be calculated, this application adopts a multi-level cascaded mean addition unit to perform mean addition calculation. This setting can also ensure the accuracy of the mean addition calculation result of multiple binary numbers to be calculated. In addition, this application statistics X max The number of "1" bits in the middle is defined as EBL. From all clock cycles, the second counter in this application is based on the bit stream X output by the DD-MAX unit. maxAfter truncating the bitstream output by the mean-add unit connected to the second counter, the number of times bit "1" appears in the bitstream output by the mean-add unit connected to the second counter is still limited to the EBL range. That is to say, the number of EBLs has covered all the valid bits (valid bits refer to bit "1") of the input bitstream. Therefore, when the second counter of this application detects a bit "0" output by the DD-MAX unit, it immediately terminates the processing of subsequent output bits of the mean-add unit connected to the second counter, and only retains the bits output by the mean-add unit connected to the second counter within the EBL length to participate in the calculation of the second counter, truncating (2 m The calculation of invalid bits (-EBL, m is the number of counter bits) can not only save calculation time, but also ensure the accuracy of the calculation result. In this application, the mean addition calculation result y calculated by the second counter is equal to the probability of bit "1" appearing in the bit stream output by the mean addition unit connected to the second counter. Attached Figure Description

[0017] Figure 1 This refers to the mean addition calculation device based on random calculation described in Embodiment 1; Figure 2 This refers to the mean addition calculation device based on random calculation described in Example 4; Figure 3 This refers to the mean addition calculation device based on random calculation described in Example 7; Figure 4 for Figure 3 A schematic diagram of the circuit structure of the DD-MAX unit; Figure 5 This refers to the mean addition calculation device based on random calculation described in Example 10; Figure 6 for Figure 5 A schematic diagram of the circuit structure of the DD-MAX unit. Detailed Implementation To facilitate understanding of the technical content of this invention by those skilled in the art, the invention will be further explained below with reference to the accompanying drawings. The description herein is merely illustrative and not intended to limit the scope of the invention.

[0018] Example 1: A mean addition calculation device based on random calculation, such as Figure 1 As shown, it includes a random bitstream generation unit, a mean addition unit, and a DD-MAX unit; in Example 4, the input is the binary number to be calculated. x 1 and x 2 This mean addition unit serves as a first-level mean addition unit. The random bit stream generation unit includes a first counter and two comparators; the mean addition unit includes two AND gates and one OR gate, with the outputs of the two AND gates in the mean addition unit connected to the two inputs of the OR gate in the mean addition unit; the DD-MAX unit includes an OR gate, which is a two-input OR gate. The first input terminals of both comparators serve as external signal input terminals for the mean addition calculation device based on random calculation in this embodiment, and are used to input the binary numbers to be calculated. x 1 and the binary number to be calculated x 2 The second input port of each comparator is connected to all the flip-flops of the first counter. Q The terminals are connected bit-by-bit to receive the corresponding bits of the incrementing binary sequence output by the first counter. The outputs of the two comparators are connected to the first inputs of the two AND gates in the mean addition unit, respectively; the second inputs of the two AND gates are connected to the least significant bit of the first counter, respectively. D trigger D 1 of Q End and With the terminals connected, from the perspective of all clock cycles, the above configuration enables this embodiment to obtain a periodic bit stream with an equivalent value of 0.5; Since this application uses a counter as the random number source, from the perspective of all clock cycles, the counter's value for each flip-flop is... Q End and The bit streams output from each terminal have the maximum negative correlation, and each flip-flop's Q End and The bit streams output by each terminal are also periodic bit streams with an equivalent value of 0.5, and these bit streams are used to perform addition operations based on the logic gates in the mean addition unit, which makes this application have better accuracy. The reason why this application obtains a periodic bit stream with an equivalent value of 0.5 is as follows: the random number source output by the counter consists of m bits. D triggers Q The output bits of each flip-flop are composed of... Q The output bits have only two states: 0 and 1, therefore there are a total of 2 m Different combinations, from 000…00 to 111…11. For the flip-flops in the counter. D 1 The trigger is activated in each clock cycle. D 1 of Q The output toggles once, either from 0 to 1 or from 1 to 0, therefore its output pattern is a fixed "01010101...", including 2.m-1 1 and 2 m-1 A zero. That is to say, no matter how large m is, the trigger... D 1 "01" repeats once every two clock cycles, and at counter 2 m Repeat 2 within a period m-1 Therefore, it exhibits strict periodicity, enabling this embodiment to obtain a periodic bit stream with an equivalent value of 0.5; higher bit in the counter D The toggling frequency of the trigger is halved with each subsequent stage. For example, the trigger... D 2 In each of 2 1 The clock cycle reverses once, the mode changes to "00110011...", and the cycle length is 4; trigger. D 3 In each of 2 2 Each clock cycle inverts once, changing the pattern to "00001111...", with a cycle length of 8. This recursive relationship ensures that each... D The outputs of the flip-flops all exhibit periodicity, that is, the i-th bit... D trigger D i 2 i The clock cycle, and the frequency of bit "0" and bit "1" is 50% each.

[0019] The outputs of the two comparators are also connected to the two inputs of the OR gate in the DD-MAX unit, respectively; the output of the OR gate in the average addition unit is connected to the input of the second counter, and the output of the OR gate in the DD-MAX unit is connected to the enable terminal of the second counter.

[0020] The first and second counters used in this application have the same structure, both consistent with the M-bit Counter structure disclosed in the paper "Power and Area Efficient Sorting Networks using Unary Processing".

[0021] The first counter is used to generate a random number source; from all clock cycles, the second counter, based on the bits output by the DD-MAX unit, only calculates the valid bits in the bitstream output by the mean addition unit, ultimately obtaining the mean addition calculation result. In Example 1, both the first and second counters are 8-bit counters.

[0022] In this embodiment, the second counter calculates only the valid bits in the bit stream output by the mean addition unit based on the bits output by the DD-MAX unit. Specifically, when the second counter detects a "0" in the bit output by the DD-MAX unit, the second counter terminates the calculation of subsequent output bits of the mean addition unit, obtaining the mean addition calculation result. This mean addition calculation result is the mean addition calculation result of the mean addition calculation device. The above-described configuration in this embodiment can effectively truncate invalid bits during computation, performing calculations only on the valid bits (i.e., valid computation bits) in the bit stream output by the mean addition unit, thus achieving a significant reduction in power consumption.

[0023] In this embodiment, to reduce the processing time of invalid bit streams, the mean addition calculation device described in this application embeds a DD-MAX unit. Specifically, from the perspective of all clock cycles, the DD-MAX unit can connect the random bit stream output by the comparator in the random bit stream generation unit to the OR gate in the DD-MAX unit, and the OR gate outputs the bit stream through OR logic operation. X max Bitstream X max The probability of bit 1 appearing is consistent with the maximum probability of bit 1 appearing in the random bit stream output by all comparators. Specifically, in this first embodiment, from the perspective of all clock cycles, the two comparators in the random bit stream generation unit output bit 1 first and then bit 0. The bits output by the two comparators in the random bit stream generation unit in all clock cycles form a random bit stream in chronological order. X 1 、 Random Bit Stream X 2 Therefore, from all clock cycles, the OR gate in the DD-MAX unit also outputs bit 1 first and then bit 0; statistics X maxThe number of "1" bits in the input bitstream B1 is defined as EBL. Since bitstream B1 is obtained by ORing bitstream A1 and bitstream A2, according to the OR logic rules, if any bit in bitstream A1 or bitstream A2 has a "1" at a certain position, then the bit in bitstream B1 at that position must also have a "1". Therefore, the positions of all "1" bits in bitstream B1 are the union of the positions of "1" bits in bitstream A1 and bitstream A2. Furthermore, since bitstream A1 is obtained by ANDing a periodic bitstream from bitstream X1 with the output of a D flip-flop, and bitstream A2 is obtained by ANDing a periodic bitstream from bitstream X2 with the output of a D flip-flop, the positions of "1" bits in bitstream A1 and bitstream A2 are subsets of the input bitstreams X1 and X2.

[0024] Since the positions of the bits "1" in bit streams A1, A2, and B1 depend entirely on the distribution of bits "1" in all input bit streams (in this embodiment, all input bit streams refer to bit streams X1 and X2), and bit stream X... max This represents the maximum possible range of bits "1" in all input bit streams.

[0025] Therefore, from the perspective of all clock cycles, the second counter is based on the bit stream X output by the DD-MAX unit. max After truncating the bitstream output by the average addition unit connected to the second counter (in this embodiment, the bitstream output by the average addition unit connected to the second counter is bitstream B1), the number of times bit "1" appears in the bitstream output by the average addition unit connected to the second counter (i.e., bitstream B1) is still limited to the EBL range. That is to say, the number of EBLs has covered all the valid bits of the input bitstream (valid bits refer to bit "1"). Therefore, when the second counter of this application detects the output bit "0" of the DD-MAX unit, it immediately terminates the processing of the subsequent output bits of the average addition unit connected to the second counter, and only retains the bits output by the average addition unit connected to the second counter within the EBL length to participate in the calculation of the second counter. The bitstream is truncated (2). m The calculation of -EBL) invalid bits, the average addition result y calculated by the second counter is equal to the probability of bit "1" appearing in bit stream B1, and does not affect the accuracy of the calculation result.

[0026] A calculation method for a mean addition calculation device based on random calculation includes the following steps: S1. The first counter in the random bit stream generation unit generates a random number source and transmits the bits to two comparators respectively, so that the two comparators share the random number source; From all clock cycles, the first counter in the random bit stream generation unit is used to generate the random number source required for the random bit stream; In the first counter of this embodiment, any one D trigger D i of Q Random bit stream output by the terminal in all clock cycles And the D flip-flop D i of Random bit stream output by the terminal in all clock cycles The probability of a bit "1" appearing in the middle is 0.5, where 1 ≤ i ≤ m, m This indicates the number of D flip-flops; and, due to the random bit stream It is a random bit stream The bit-by-bit reversal, therefore, the bit stream With bit stream It exhibits the largest negative correlation, which means that the bit 1s between two random bit streams do not overlap; S2, the binary number to be calculated x 1 and the binary number to be calculated x 2 The binary number is input to each comparator via its first input terminal. x 1 and binary numbers x 2 The number of bits is the same as the number of bits in the counter. m The comparator compares the digital signal output from the first counter with the digital signal input from the first input terminal of the comparator. If the digital signal input from the first input terminal of the comparator is greater than the digital signal output from the first counter, the comparator outputs a bit "1". If the digital signal input from the first input terminal of the comparator is less than the digital signal output from the first counter, the comparator outputs a bit "0".

[0027] From all clock cycles, the comparator in this embodiment performs the function of comparing the bits output by the first counter with the binary digital signal of the binary number input through the first input terminal of the comparator bit by bit, and outputs a random bit stream. Specifically, in this embodiment, the comparator compares the digital signal output by the first counter with the digital signal input through the first input terminal of the comparator in each clock cycle. If the digital signal input through the first input terminal of the comparator is greater than the digital signal output by the counter, the comparator outputs a bit "1". If the digital signal input through the first input terminal of the comparator is less than the digital signal output by the counter, the comparator outputs a bit "0". After all clock cycles are completed, the bits output by the comparator in all clock cycles are arranged in a random bit stream according to the timing sequence. Specifically, in this embodiment, after all clock cycles have ended, the two comparators output random bit streams X1 and X2, respectively. The probability of a bit "1" appearing in random bit stream X1 is the same as the value represented by the binary number x1 input to the first input of the comparator. Similarly, the probability of a bit "1" appearing in random bit stream X2 is the same as the value represented by the binary number x2 input to the first input of the other comparator. Therefore, the random bit streams... X 1 and random bit stream X 2 can be used to represent the binary number x1 and the binary number x2 to be calculated, respectively; S3. Perform mean addition using the mean addition unit. Specifically: use two AND gates in the mean addition unit to receive the bits output from two comparators (the two comparators share a random number source), and simultaneously, the least significant bit flip-flop... D 1 of Q The output bits and the least significant bit flip-flop D 1 of The bits output from the terminals are also input into two AND gates, and the two AND gates perform AND logic operations on the input bits respectively; then the OR gate in the mean addition unit performs OR logic operations on the bits output from the two AND gates; at the same time, the bits output from the two comparators are input into the OR gate in the DD-MAX unit through the two input terminals of the OR gate, and the OR gate performs OR logic operations on the bits output from the two comparators. In this embodiment, the bit streams formed by arranging the bits output by the two AND gates in timing order throughout all clock cycles are referred to as scaled bit streams. A 1 and scaling bitstream A 2 ; Throughout all clock cycles, the two AND gates of the mean-add unit receive the bit streams output from the two comparators, respectively.X 1 and bitstream X 2 At the same time, the least significant bit flip-flop D 1 of Q random bit stream output from the terminal and the least significant bit flip-flop D 1 of random bit stream output from the terminal Input two AND gates respectively; after performing AND logic operations on the two AND gates, output scaled bitstreams respectively. A 1 and scaling bitstream A 2 .

[0028] In this embodiment, the bit stream X 1 It is generated by one of the comparators. Looking at all the clock cycles, the comparator outputs bit 1 first, then bit 0. Therefore, the bit stream... X 1 The middle bits "1" are all distributed at one end, while the least significant bit flip-flop... D 1 of Q End and Random bit streams output by each end and random bit stream It is a periodic bitstream with a numerical equivalent of 0.5, so the scaling bitstream... A 1 The probability P(bit 1) A 1 =1) and the bit stream output by the comparator X 1 The probability P(bit 1) X 1 The relationship between =1) is P( A 1 =1)=P( X 1 =1) 0.5; similarly, scaling the bitstream. A 2 The probability P(bit 1) A 2 =1) and the bit stream output by another comparator X 2 The probability P(bit 1) X 2 The relationship between =1) is P( A 2 =1)=P( X2 =1) 0.5; This setting achieves the effect of scaling down the probability value of bit 1 in the bit stream output by the comparator by a factor of 0.5.

[0029] In this embodiment, the scaling bitstream is used. A 1 and scaling bitstream A 2 It has the largest negative correlation, and the addition operation is performed by an OR gate in the mean addition unit, bit stream. B 1 The probability value P(bit 1) B 1 =1) is;

[0030] S4. The second counter receives the bits output from the OR gate in the average addition unit and the bits output from the OR gate in the DD-MAX unit. When the second counter detects a "0" in the bit output from the DD-MAX unit, it terminates the calculation of the bits output from the OR gate in the subsequent average addition unit, thus obtaining the average addition calculation result, which is the binary number to be calculated. x 1 and the binary number to be calculated x 2 The result of the mean addition calculation; the result of the mean addition calculation y calculated by the second counter is equal to the probability of bit "1" appearing in bit stream B1.

[0031] Example 2: A mean addition calculation device based on random calculation is provided in Embodiment 2. The difference between the mean addition calculation device based on random calculation in Embodiment 1 and the mean addition calculation device based on random calculation in Embodiment 2 is that both the first counter and the second counter in Embodiment 2 are 9-bit counters.

[0032] Example 3: A mean addition calculation device based on random calculation is provided in Embodiment 3. The difference between the mean addition calculation device based on random calculation described in Embodiment 1 and the mean addition calculation device based on random calculation described in Embodiment 3 is that both the first counter and the second counter in Embodiment 3 are 10-bit counters.

[0033] Example 4: A mean addition calculation device based on random calculation, such as Figure 2 As shown, it includes a random bitstream generation unit, three mean addition units, and one DD-MAX unit; in Example 4, the input is the binary number to be calculated. x 1 , x2 , x 3 and x 4 That is to say, in Example 4, the number of binary numbers to be calculated is 4; The random bit stream generation unit in this embodiment four has the same structure as the random bit stream generation unit in this embodiment one. That is, in embodiment four, the random bit stream generation unit includes a first counter and four comparators. In this fourth embodiment, the number of division levels n of the mean addition unit is calculated. X represents the number of binary numbers to be calculated; the mean addition unit is divided into level one to level n mean addition units, where level one to level n mean addition units are all mean addition units in proportion to the number of mean addition units. : :...... The division is based on the proportion. When X=4, i.e., n=2, the first-level mean addition unit and the second-level mean addition unit are obtained by dividing all mean addition units according to the ratio of the number of mean addition units. : The proportions were used to divide the data. Specifically, in this fourth embodiment, the number of binary numbers to be calculated, X=4, and in this fourth embodiment, the number of division levels of the mean addition unit... In other words, in this embodiment, the mean addition unit is divided into a first-level mean addition unit and a second-level mean addition unit, and the first-level mean addition unit and the second-level mean addition unit are formed by dividing all mean addition units in a ratio of the number of mean addition units. : The average addition unit is divided into units with a ratio of 2:1; in this fourth embodiment, the output of the OR gate in the average addition unit is the output of the average addition unit. In Example 4, the structure of the mean addition unit is the same as that of the mean addition unit in Example 1. That is, each mean addition unit in Example 4 includes two AND gates and one OR gate. The output terminals of the two AND gates in the mean addition unit are respectively connected to the two input terminals of the OR gate in the mean addition unit. The output of the OR gate in the mean addition unit is the output of the mean addition unit. In this fourth embodiment, the DD-MAX unit includes three OR gates. In this fourth embodiment, the three OR gates are also divided into levels. In other words, in this fourth embodiment, the three OR gates are divided into first-level OR gates and second-level OR gates, and the first-level OR gates and second-level OR gates are determined by the ratio of the number of OR gates of the three OR gates. : It was obtained by dividing it in a ratio of 2:1.

[0034] In this fourth embodiment, the first input terminals of the four comparators are all used as external signal input terminals of the mean addition calculation device based on random calculation in this embodiment, and are respectively used to input the binary number to be calculated. x 1 , x 2 , x 3 and x 4 The second input port of each comparator is connected bit-by-bit to the Q terminals of all the flip-flops of the first counter, and is used to receive the corresponding bits of the incrementing binary sequence output by the first counter. The four comparators are grouped into two pairs, and the output of one group of comparators is connected to the first input of the two AND gates in a first-level average addition unit. This embodiment aims to perform mean addition calculation by cascading multiple levels of mean addition units. Therefore, this embodiment is configured as follows: the second input of one of the AND gates in each first-level mean addition unit is connected to the least significant bit of the first counter. D trigger D 1 of The terminals are connected, and the second input terminal of the other AND gate in each first-level average addition unit is connected to the least significant bit in the first counter. D trigger D 1 of The terminals are connected; the outputs of the OR gates in the two first-level average addition units are respectively connected to the inputs of the two AND gates in the second-level addition unit, and the other input of each AND gate in the second-level addition unit is respectively connected to the flip-flop. D 2 of End and The terminals are connected, where the trigger is... D 2 The least significant bit D trigger D 1 Adjacent flip-flops; from all clock cycles, the above settings enable this embodiment to obtain a periodic bit stream with a numerical equivalent of 0.5; In this embodiment's DD-MAX unit, the two inputs of a single-stage OR gate are connected to the two outputs of a set of comparators, and the two single-stage OR gates are connected to a single-stage OR gate. The output of the OR gate in the single-stage average adder unit is connected to the input of the second counter, and the output of the single-stage OR gate in the DD-MAX unit is connected to the enable terminal of the second counter. In Embodiment Four, both the first and second counters are 8-bit counters.

[0035] In this embodiment, the first counter is used to generate a random number source; the second counter calculates only the valid bits in the bit stream output by the second-level mean addition unit based on the bits output by the DD-MAX unit. Specifically, when the second counter detects a "0" in the bits output by the DD-MAX unit, the second counter terminates the calculation of subsequent bits output by the second-level mean addition unit, and obtains the mean addition calculation result. This mean addition calculation result is the mean addition calculation result of the mean addition calculation device. The above-described configuration in this embodiment can effectively truncate invalid bits during computation, performing calculations only on the valid bits (i.e., valid computation bits) in the bit stream output by the mean addition unit, thus achieving a significant reduction in power consumption.

[0036] A calculation method for a mean addition calculation device based on random calculation includes the following steps: S1. The first counter in the random bit stream generation unit generates a random number source and transmits the bits to four comparators respectively, so that the four comparators share the random number source. S2. Input the four binary numbers to be calculated. x 1 , x 2 , x 3 and x 4 Divide into pairs, specifically, x 1 and x 2 As a group, x 3 and x 4 As a group, the two sets of binary numbers to be calculated are input into the two sets of comparators respectively. The comparators compare the digital signal output from the first counter with the digital signal input from the first input terminal of the comparator. If the digital signal input from the first input terminal of the comparator is greater than the digital signal output from the first counter, the comparator outputs a bit "1". If the digital signal input from the first input terminal of the comparator is less than the digital signal output from the first counter, the comparator outputs a bit "0".

[0037] From all clock cycles, the comparator in this embodiment performs the function of comparing the bit stream output by the counter with the binary number input through the first input terminal of the comparator bit by bit, and outputs a random bit stream. In this embodiment, after all clock cycles, the four comparators output random bit streams X1, X2, X3 and X4 respectively. The probability value of the bit "1" in random bit stream X1 is the same as the value represented by the binary number x1 input through the first input terminal of the comparator. The probability value of the bit "1" in random bit stream X2 is the same as the value represented by the binary number x2 input through the first input terminal of another comparator. The probability value of the bit "1" in random bit stream X3 is the same as the value represented by the binary number x3 input through the first input terminal of the comparator. The probability value of the bit "1" in random bit stream X4 is the same as the value represented by the binary number x4 input through the first input terminal of another comparator. Therefore, random bit streams X1, X2, X3 and X4 can be used to represent the binary numbers x1, x2, x3 and x4 to be calculated, respectively. S3. Perform mean addition calculation using the mean addition unit. Specifically, perform mean addition calculation sequentially using the first-level mean addition unit and the second-level mean addition unit; this includes the following steps: S3-1: Perform mean addition calculation using the first-level mean addition unit. The specific steps are as follows: Each first-stage average addition unit receives a set of bits from the comparator output. Specifically, the two AND gates in each first-stage average addition unit each receive a set of bits from the comparator output; simultaneously, the least significant bit flip-flop... D 1 of Q The output bits and the least significant bit flip-flop D 1 of The bits output from the terminal are also input into the two AND gates mentioned above; the two AND gates perform AND logic operations on the input bits respectively; at the same time, the bits output from the two sets of comparators are input into the DD-MAX unit respectively, and the DD-MAX unit performs OR logic operations on the bits output from the eight sets of comparators. In this embodiment, from the perspective of all clock cycles, the bitstream formed by the bits output by the two AND gates in each first-level average addition unit in all clock cycles arranged in timing order is called the scaled bitstream; specifically, the bitstream formed by the bits output by the two AND gates in one first-level average addition unit (hereinafter referred to as the first first-level average addition unit) in all clock cycles arranged in timing order is called the scaled bitstream. A 1 and scaling bitstream A 2In another first-level average addition unit (hereinafter referred to as the second first-level average addition unit), the bits output by the two AND gates in all clock cycles are arranged in timing order to form a scaled bit stream. A 3 and scaling bitstream A 4 .

[0038] In this embodiment, the bit stream X 1 It is generated by one of the comparators. Looking at all the clock cycles, the comparator outputs bit 1 first, then bit 0. Therefore, the bit stream... X 1 The middle bits "1" are all distributed at one end, while the least significant bit flip-flop... D 1 of Q End and Random bit streams output by each end and random bit stream It is a periodic bitstream with a numerical equivalent of 0.5, so the scaling bitstream... A 1 The probability P(bit 1) A 1 =1) and the bit stream output by the comparator X 1 The probability P(bit 1) X 1 The relationship between =1) is P( A 1 =1)=P( X 1 =1) 0.5; similarly, scaling the bitstream. A 2 The probability P(bit 1) A 2 =1) and the bit stream output by another comparator X 2 The probability P(bit 1) X 2 The relationship between =1) is P( A 2 =1)=P( X 2 =1) 0.5; scaling bitstream A 3 The probability P(bit 1) A 3 =1) and the bit stream output by another comparator X 3 The probability P(bit 1) X 3The relationship between =1) is P( A 3 =1)=P( X 3 =1) 0.5; scaling bitstream A 4 The probability P(bit 1) A 4 =1) and the bit stream output by another comparator X 4 The probability P(bit 1) X 4 The relationship between =1) is P( A 4 =1)=P( X 4 =1) 0.5; This setting achieves the effect of scaling down the probability value of bit 1 in the bit stream output by the comparator by a factor of 0.5.

[0039] In this embodiment, the scaling bitstream is used. A 1 and scaling bitstream A 2 With the largest negative correlation, scaled bitstream A 3 and scaling bitstream A 4 With the highest negative correlation, both the first and second level-one average addition units perform addition operations via OR gates. After all clock cycles, the OR gates in the first and second level-one average addition units output bit streams respectively. B 1 and bitstream B 2 Among them, bit stream B 1 The probability value P(bit 1) B 1 =1) is:

[0040] The probability P(B2=1) of bit 1 in bit stream B2 is:

[0041] S3-2: Perform mean addition calculation using the second-level mean addition unit. The specific steps are as follows: The two AND gates in the second-level mean-add unit receive bits from the outputs of the two first-level mean-add units, respectively. Simultaneously, the flip-flops... D 2 of Q The output bits and flip-flopsD 2 of The bits output from the terminal are also input to the two AND gates in the second-level average addition unit. The two AND gates perform AND logic operations on the input bits, and the OR gate in the second-level average addition unit performs OR logic operations on the bits output from the two AND gates. From the perspective of all clock cycles, the bits output by the two AND gates in the second-level average addition unit in all clock cycles form bit streams C1 and C2 in the timing order; the bits output by the OR gate in the second-level average addition unit in all clock cycles form bit stream Y in the timing order. S4. The second counter receives the bits output from the OR gate in the second-level average addition unit and the bits output from the OR gate in the DD-MAX unit. When the second counter detects a "0" in the bit output from the DD-MAX unit, it terminates the calculation of the bits output from the OR gate in the subsequent second-level average addition unit, thus obtaining the average addition calculation result, which is the binary number to be calculated. x 1 , x 2 , x 3 and x 4 The result of the mean addition calculation; the result of the mean addition calculation y calculated by the second counter is equal to the probability of bit "1" appearing in bit stream Y; the probability of bit "1" appearing in bit stream Y is: Example 5: A mean addition calculation device based on random calculation is provided in Embodiment 5. The difference between the mean addition calculation device based on random calculation in Embodiment 4 and the mean addition calculation device based on random calculation in Embodiment 5 is that both the first counter and the second counter in Embodiment 5 are 9-bit counters.

[0042] Example 6: A mean addition calculation device based on random calculation is provided in Embodiment Six. The difference between the mean addition calculation device based on random calculation described in Embodiment Four and the mean addition calculation device based on random calculation described in Embodiment Six is ​​that both the first counter and the second counter in Embodiment Six are 10-bit counters.

[0043] Example 7: A mean addition calculation device based on random calculation, such as Figure 3 and Figure 4 As shown, it includes a random bitstream generation unit, seven mean addition units, and one DD-MAX unit; in Example 7, the input is a binary number to be calculated. x 1, x 2 , x 3 , x 4 , x 5 , x 6 , x 7 and x 8 That is, the number of binary numbers to be calculated, which is 8; The random bitstream generation unit in this embodiment seven has the same structure as the random bitstream generation unit in this embodiment one. In this seventh embodiment, the number of binary numbers to be calculated, X=8, and the number of levels in the mean addition unit is also specified. In other words, in this embodiment, the mean addition unit is divided into a first-level mean addition unit, a second-level mean addition unit, and a third-level mean addition unit. Furthermore, the first-level, second-level, and third-level mean addition units are formed by dividing all mean addition units according to the ratio of the number of mean addition units. : : The average addition units are divided into units with a ratio of 4:2:1. In this seventh embodiment, the structure of the average addition units is the same as that of the average addition units in the first embodiment. The output of the OR gate in the average addition unit is the output of the average addition unit. In this seventh embodiment, the seven OR gates are also divided into levels, and the levels are... In other words, in this embodiment ten, the seven OR gates are divided into first-level OR gates, second-level OR gates, and third-level OR gates, and the first-level OR gates, second-level OR gates, and third-level OR gates are determined by the ratio of the number of OR gates of the above seven OR gates. : : The ratio of 4:2:1 was used to divide the area.

[0044] In this seventh embodiment, the first input terminals of the eight comparators are all used as external signal input terminals of the mean addition calculation device based on random calculation in this embodiment, and are respectively used to input the binary number to be calculated. x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 andx 8 The second input port of each comparator is connected bit-by-bit to the Q terminals of all the flip-flops of the first counter, and is used to receive the corresponding bits of the incrementing binary sequence output by the first counter. The eight comparators are grouped into four groups of two, and the output of each comparator is connected to the first input of the two AND gates in a single-stage average addition unit. This embodiment aims to perform mean addition calculation by cascading multiple levels of mean addition units. Therefore, this embodiment is configured as follows: the second input of one of the AND gates in each first-level mean addition unit is connected to the least significant bit of the first counter. D trigger D 1 of The terminals are connected, and the second input terminal of the other AND gate in each first-level average addition unit is connected to the least significant bit in the first counter. D trigger D 1 of The terminals are connected; in this embodiment, two first-level average addition units form a group, and the output terminal of the OR gate in a group of first-level average addition units is respectively connected to the input terminals of two AND gates in a second-level addition unit; the other input terminal of the two AND gates in each second-level addition unit is also respectively connected to a flip-flop. D 2 of End and Terminal connection; trigger D 2 The least significant bit D trigger D 1 Adjacent flip-flops; the outputs of the OR gates in the two secondary average adder units are respectively connected to the inputs of the two AND gates in the tertiary adder unit; the other input of each AND gate in the tertiary adder unit is also connected to the flip-flops. D 3 of End and Terminal connection; trigger D 3 For triggers D 2 Adjacent triggers; From all clock cycles, the above settings enable this embodiment to obtain a periodic bit stream with a numerical equivalent of 0.5; In this embodiment's DD-MAX unit, the two inputs of a single-stage OR gate are connected to the two outputs of a set of comparators, respectively. Two single-stage OR gates form a set, and a set of single-stage OR gates is connected to a second-stage OR gate. The two second-stage OR gates are connected to a third-stage OR gate. In the third-stage average adder unit, the output of the OR gate is connected to the input of the second counter, and the output of the third-stage OR gate in the DD-MAX unit is connected to the enable terminal of the second counter. In Embodiment Seven, both the first and second counters are 8-bit counters.

[0045] A calculation method for a mean addition calculation device based on random calculation includes the following steps: S1. The first counter in the random bit stream generation unit generates a random number source and transmits the bits to eight comparators respectively, so that the eight comparators share the random number source; S2. Input the eight-way binary number to be calculated. x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 Divide into pairs, specifically x 1 and x 2 As a group, x 3 and x 4 As a group, x 5 and x 6 As a group, x 7 and x 8 As a group, there are four groups in total. The four groups of binary numbers to be calculated are input into the four comparators respectively. The comparators compare the digital signal output from the first counter with the digital signal input from the first input terminal of the comparator. If the digital signal input from the first input terminal of the comparator is greater than the digital signal output from the first counter, the comparator outputs a bit "1". If the digital signal input from the first input terminal of the comparator is less than the digital signal output from the first counter, the comparator outputs a bit "0".

[0046] In this embodiment, after all clock cycles have ended, the eight comparators output random bit streams X1, X2, X3, X4, X5, X6, X7, and X8, respectively. The probability values ​​of bit "1" appearing in random bit streams X1, X2, X3, X4, X5, X6, X7, and X8 are respectively related to the probability values ​​of the binary number... x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 Since they represent the same numerical value, random bit streams X1, X2, X3, X4, X5, X6, X7, and X8 can each be used to represent the binary number to be calculated. x 1 、x 2 、x 3 、x 4 、x 5 、x 6 、x 7 、x 8 ; S3. Perform mean addition calculations using the mean addition unit. Specifically, perform mean addition calculations sequentially using the first-level mean addition unit, the second-level mean addition unit, and the third-level mean addition unit; this includes the following steps: S3-1: Perform mean addition calculation using the first-level mean addition unit. The specific steps are as follows: Each first-stage average addition unit receives a set of bits from the comparator output. Specifically, the two AND gates in each first-stage average addition unit each receive a set of bits from the comparator output; simultaneously, the least significant bit flip-flop... D 1 of Q The output bits and the least significant bit flip-flop D 1 of The bits output from the terminal are also input into the two AND gates mentioned above; the two AND gates perform AND logic operations on the input bits respectively; at the same time, the bits output from the four sets of comparators are input into the DD-MAX unit respectively, and the DD-MAX unit performs OR logic operations on the bits output from the eight sets of comparators. In this embodiment, from the perspective of all clock cycles, the bitstream formed by the bits output by the two AND gates in each first-level average addition unit in all clock cycles arranged in timing order is called the scaled bitstream; the bits output by the AND gates in the four first-level average addition units in all clock cycles, arranged in timing order, respectively constitute scaled bitstreams. A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 and A 8 .

[0047] In this embodiment, the bit stream X 1 It is generated by one of the comparators. Looking at all the clock cycles, the comparator outputs bit 1 first, then bit 0. Therefore, the bit stream... X 1 The middle bits "1" are all distributed at one end, while the least significant bit flip-flop... D 1 of Q End and Random bit streams output by each end and random bit stream It is a periodic bitstream with a numerical equivalent of 0.5, so the scaling bitstream... A 1 The probability P(bit 1) A 8 =1) are the bit streams X 1 The probability of a 1 in the middle bit is 1 / 2. Similarly, the probability of scaling the bit stream is 1 / 2. A 2 The probability P(bit 1) A 2 =1), Scaling the bitstream A 3 The probability P(bit 1) A 3 =1), Scaling the bitstream A 4 The probability P(bit 1) A 4 =1), Scaling the bitstream A 5 The probability P(bit 1) A 5 =1), Scaling the bitstreamA 6 The probability P(bit 1) A 6 =1), Scaling the bitstream A 7 The probability P(bit 1) A 7 =1), Scaling the bitstream A 8 The probability P(bit 1) A 8 =1) are the bit streams X 2 , X 3 , X 4 , X 5 , X 6 , X 7 and X 8 The probability of bit 1 in the bit stream is 1 / 2; this setting achieves the effect of scaling down the probability value of bit 1 in the bit stream output by the comparator by a factor of 0.5.

[0048] In this embodiment, the scaling bitstream is used. A 1 and A 2 With the largest negative correlation, scaled bitstream A 3 and A 4 It has the largest negative correlation. A 5 and A 6 With the largest negative correlation, scaled bitstream A 7 and A 8 Having the greatest negative correlation, all four first-level average addition units perform addition operations via OR gates. After all clock cycles are completed, the bitstream in Example 7... B 1 , B 2 The probability value P(bit 1) B 1 =1) and P( B 2 =1) respectively with the bit stream in Example 4 B 1 , B 2 The probability value P(bit 1) B 1=1) and P( B 2 =1) is the same, while the bitstream in Example 7 is the same. B 3 and B 4 The probability value P(bit 1) B 3 =1), P( B 4 =1) are respectively: ; ; S3-2: Perform mean addition calculation using the second-level mean addition unit. The specific steps are as follows: The four first-level adder units are divided into two groups of two. The two AND gates in each second-level average adder unit each receive bits from the output of one group of first-level average adder units. Simultaneously, the flip-flops... D 2 of Q The output bits and flip-flops D 2 of The bits output from the terminals are also input to the two AND gates in the two-stage average addition unit, respectively. The two AND gates perform AND logic operations on the input bits. From the perspective of all clock cycles, the bits output by the AND gates in the two-stage average addition units in all clock cycles form bit streams C1, C2, C3, and C4 in timing order. The OR gates in the two-stage average addition unit perform OR logic operations on the bits output by the two AND gates. From the perspective of all clock cycles, the bits output by the OR gates in the two-stage average addition units in all clock cycles form bit streams D1 and D2 in timing order. S3-3: Perform mean addition calculation using a three-level mean addition unit. The specific steps are as follows: The two AND gates in the three-stage mean-add unit receive bits from the outputs of the two two-stage mean-add units, respectively. Simultaneously, the flip-flops... D 3 of Q The output bits and flip-flops D 3 of The bits output from the terminal are also input to the two AND gates in the three-stage average addition unit, and the two AND gates perform AND logic operations on the input bits respectively; the OR gate in the three-stage average addition unit performs OR logic operations on the bits output from the two AND gates; from the perspective of all clock cycles, the bits output by the AND gate in the three-stage average addition unit in all clock cycles form bit streams E1 and E2 in timing order; the bits output by the OR gate in the three-stage average addition unit in all clock cycles form bit stream Y in timing order. S4. The second counter receives the bits output from the OR gates in the three-stage average addition unit and the bits output from the OR gates in the DD-MAX unit. When the second counter detects a "0" in the bit output from the DD-MAX unit, it terminates the calculation of the bits output from the OR gates in the subsequent three-stage average addition unit, thus obtaining the average addition calculation result. That is, the binary number to be calculated x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 The result of the mean addition calculation; the result of the mean addition calculation y calculated by the second counter is equal to the probability of bit "1" appearing in bit stream Y; the probability of bit "1" appearing in bit stream Y is: ; The above-mentioned settings in this embodiment can effectively truncate the operation of invalid bits, and only perform calculations on the valid bits (i.e. valid calculation bits) in the bit stream output by the mean addition unit, thereby achieving a significant reduction in power consumption.

[0049] Example 8: A mean addition calculation device based on random calculation is provided in Embodiment 8. The difference between the mean addition calculation device based on random calculation described in Embodiment 7 and the mean addition calculation device based on random calculation described in Embodiment 8 is that both the first counter and the second counter in Embodiment 8 are 9-bit counters.

[0050] Example 9: A mean addition calculation device based on random calculation is provided in Embodiment 9. The difference between the mean addition calculation device based on random calculation described in Embodiment 7 is that the first counter and the second counter in Embodiment 9 are both 10-bit counters.

[0051] Example 10: A mean addition calculation device based on random calculation, such as Figure 5 and Figure 6 As shown, it includes a random bitstream generation unit, fifteen mean addition units, and one DD-MAX unit; in Example 10, the input is a binary number to be calculated. x1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 , x 9 , x 10 , x 11 , x 12 , x 13 , x 14 , x 15 and x 16 That is, the number of binary numbers to be calculated is 16; The random bitstream generation unit in this embodiment ten has the same structure as the random bitstream generation unit in this embodiment one; In this tenth embodiment, the number of binary numbers to be calculated, X=16, and the number of division levels of the mean addition unit in this tenth embodiment. In other words, in this embodiment ten, the mean addition unit is divided into a first-level mean addition unit, a second-level mean addition unit, a third-level mean addition unit, and a fourth-level mean addition unit. Furthermore, the first-level, second-level, third-level, and fourth-level mean addition units are formed by proportionally dividing all mean addition units according to the ratio of their number of units. : : : The ratio of 8:4:2:1 is used to divide all the mean addition units; in this embodiment ten, the structure of the mean addition unit is the same as that of the mean addition unit in embodiment one, and the output of the OR gate in the mean addition unit is the output of the mean addition unit; In this embodiment ten, the DD-MAX unit includes fifteen OR gates. In this embodiment ten, the fifteen OR gates are also divided into levels. In other words, in this embodiment ten, the fifteen OR gates are divided into first-level OR gates, second-level OR gates, third-level OR gates, and fourth-level OR gates. Furthermore, the first-level, second-level, third-level, and fourth-level OR gates are determined by the ratio of the number of OR gates among the aforementioned fifteen OR gates. : : : The ratio of 8:4:2:1 was used to divide the area.

[0052] In this tenth embodiment, the first input terminals of the sixteen comparators are all used as external signal input terminals of the mean addition calculation device based on random calculation in this embodiment, and are respectively used to input the binary number to be calculated. x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 , x 9 , x 10 , x 11 , x 12 , x 13 , x 14 , x 15 and x 16 The second input port of each comparator is connected bit-by-bit to the Q terminals of all the flip-flops of the first counter, and is used to receive the corresponding bits of the incrementing binary sequence output by the first counter. The sixteen comparators are grouped into eight pairs. The output of each comparator is connected to the first input of two AND gates in a single-stage average addition unit. This embodiment aims to perform mean addition calculation by cascading multiple levels of mean addition units. Therefore, this embodiment is configured as follows: the second input of one of the AND gates in each first-level mean addition unit is connected to the least significant bit of the first counter. D trigger D 1 of The terminals are connected, and the second input terminal of the other AND gate in each first-level average addition unit is connected to the least significant bit in the first counter. D trigger D 1 of The terminals are connected; in this embodiment, two first-level average addition units form a group, and the output terminal of the OR gate in a group of first-level average addition units is respectively connected to the input terminals of two AND gates in a second-level addition unit; for example, in this embodiment ten, there are eight first-level average addition units, respectively called the first first-level average addition unit, the second first-level average addition unit, the third first-level average addition unit... the eighth first-level average addition unit; there are four second-level average addition units, respectively called the first second-level average addition unit, the second second-level average addition unit... the fourth second-level average addition unit; the output terminals of the first and second first-level average addition units are connected to the first second-level average addition unit, the output terminals of the third and fourth first-level average addition units are connected to the second second-level average addition unit, the output terminals of the fifth and sixth first-level average addition units are connected to the third second-level average addition unit, and the output terminals of the seventh and eighth first-level average addition units are connected to the fourth second-level average addition unit; in this embodiment, the other input terminal of each AND gate in each second-level addition unit is respectively connected to a flip-flop. D 2 of End and Terminal connection; trigger D 2 The least significant bit D trigger D 1 Adjacent flip-flops; In this embodiment, two secondary mean-adding units form a group, and the output of the OR gate in a group of secondary mean-adding units is respectively connected to the input of two AND gates in a tertiary adder unit; For example, in this embodiment ten, there are two tertiary mean-adding units, referred to as the first tertiary mean-adding unit and the second tertiary mean-adding unit; the outputs of the first and second secondary mean-adding units are connected to the first tertiary mean-adding unit, and the outputs of the third and fourth secondary mean-adding units are connected to the third secondary mean-adding unit; In this embodiment, the other input of each AND gate in the tertiary adder unit is also connected to a flip-flop. D 3 of End and Terminal connection; trigger D 3 For triggers D 2 Adjacent flip-flops; the outputs of the OR gates in the two three-stage average adder units are respectively connected to the inputs of the two AND gates in the four-stage adder unit; the other input of each AND gate in the four-stage adder unit is also connected to the flip-flops. D 4 of End and Terminal connection; trigger D 4 For triggersD 3 Adjacent triggers; From all clock cycles, the above settings enable this embodiment to obtain a periodic bit stream with a numerical equivalent of 0.5; In this embodiment's DD-MAX unit, the two inputs of a single-stage OR gate are respectively connected to the two outputs of a set of comparators. Two single-stage OR gates form a group, a group of single-stage OR gates is connected to a second-stage OR gate, two second-stage OR gates form a group, a group of second-stage OR gates is connected to a third-stage OR gate, and two third-stage OR gates are connected to a fourth-stage OR gate. The output of the OR gate in the fourth-stage average adder unit is connected to the input of the second counter, and the output of the fourth-stage OR gate in the DD-MAX unit is connected to the enable terminal of the second counter. In Embodiment Ten, both the first and second counters are 8-bit counters.

[0053] A calculation method for a mean addition calculation device based on random calculation includes the following steps: S1. The first counter in the random bit stream generation unit generates a random number source and transmits the bits to sixteen comparators respectively, so that the sixteen comparators share the random number source; S2. Input the sixteen-way binary number to be calculated. x 1 , x 2 to x 16 Divide into pairs, specifically x 1 and x 2 As a group, x 3 and x 4 As a group, x 5 and x 6 As a group, x 7 and x 8 As a group, x 9 and x 10 As a group, x 11 and x 12 As a group, x 13 and x 14 As a group, x 15 and x 16As a group, there are eight groups in total. The eight groups of binary numbers to be calculated are respectively input into eight comparators. In this embodiment, the comparator compares the digital signal output by the first counter with the digital signal input from the first input terminal of the comparator. If the digital signal input from the first input terminal of the comparator is greater than the digital signal output by the first counter, the comparator outputs a bit "1". If the digital signal input from the first input terminal of the comparator is less than the digital signal output by the first counter, the comparator outputs a bit "0".

[0054] In this embodiment, after all clock cycles have ended, the sixteen comparators output random bit streams X1, X2, X3, X4, X5, X6, X7, X8, X9, X... 10 X 11 X 12 X 13 X 14 X 15 X 16 Among them, random bit streams X1, X2, X3, X4, X5, X6, X7, X8, X9, X 10 X 11 X 12 X 13 X 14 X 15 X 16 The probability values ​​of the middle bit "1" appearing are respectively related to the binary number x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 , x 9 , x 10 , x 11 , x 12 , x 13 , x 14 , x 15 , x 16 The values ​​represented are the same; therefore, the random bit streams X1, X2, X3, X4, X5, X6, X7, X8, X9, X...10 X 11 X 12 X 13 X 14 X 15 X 16 They can be used to represent the binary numbers x1, x2, x3, x4, and x5 to be calculated, respectively. x 5 , x 6 , x 7 , x 8 , x 9 , x 10 , x 11 , x 12 , x 13 , x 14 , x 15 , x 16 ; S3. Perform mean addition calculations using the mean addition unit. Specifically, perform mean addition calculations sequentially using the first-level, second-level, third-level, and fourth-level mean addition units; this includes the following steps: S3-1: Perform mean addition calculation using the first-level mean addition unit. The specific steps are as follows: Each first-stage average addition unit receives a set of bits from the comparator output. Specifically, the two AND gates in each first-stage average addition unit each receive a set of bits from the comparator output; simultaneously, the least significant bit flip-flop... D 1 of Q The output bits and the least significant bit flip-flop D 1 of The bits output from the terminal are also input into the two AND gates mentioned above; the two AND gates perform AND logic operations on the input bits respectively; at the same time, the bits output from the eight comparators are input into the DD-MAX unit respectively, and the DD-MAX unit performs OR logic operations on the bits output from the eight comparators. In this embodiment, from the perspective of all clock cycles, the bit stream formed by arranging the bits output by the two AND gates in each first-level average addition unit in all clock cycles according to the timing sequence is called the scaled bit stream; in this embodiment, the bits output by the AND gates in the eight first-level average addition units in all clock cycles are arranged in timing sequence to form scaled bit streams respectively.A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 , A 8 , A 9 , A 10 , A 11 , A 12 , A 13 , A 14 , A 15 , A 16 .

[0055] In this embodiment, the bit stream X 1 It is generated by one of the comparators. Looking at all the clock cycles, the comparator outputs bit 1 first, then bit 0. Therefore, the bit stream... X 1 The middle bits "1" are all distributed at one end, while the least significant bit flip-flop... D 1 of Q End and Random bit streams output by each end and random bit stream It is a periodic bitstream with a numerical equivalent of 0.5, so the scaling bitstream... A 1 The probability P(bit 1) A 8 =1) are the bit streams X 1 The probability of a 1 in the middle bit is 1 / 2. Similarly, the probability of scaling the bit stream is 1 / 2. A 2 The probability P(bit 1) A 2 =1), Scaling the bitstream A 3 The probability P(bit 1) A 3 =1), Scaling the bitstream A 4 The probability P(bit 1)A 4 =1), Scaling the bitstream A 5 The probability P(bit 1) A 5 =1), Scaling the bitstream A 6 The probability P(bit 1) A 6 =1), Scaling the bitstream A 7 The probability P(bit 1) A 7 =1), Scaling the bitstream A 8 The probability P(bit 1) A 8 =1), Scaling the bitstream A 9 The probability P(bit 1) A 9 =1), Scaling the bitstream A 3 The probability P(bit 1) A 10 =1), Scaling the bitstream A 4 The probability P(bit 1) A 10 =1), Scaling the bitstream A 11 The probability P(bit 1) A 11 =1), Scaling the bitstream A 12 The probability P(bit 1) A 12 =1), Scaling the bitstream A 13 The probability P(bit 1) A 13 =1), Scaling the bitstream A 14 The probability P(bit 1) A 14 =1), Scaling the bitstream A 15 The probability P(bit 1) A 15 =1), Scaling the bitstream A 16 The probability P(bit 1) A 16 =1) are the bit streams X 2 , X 3 ,X 4 , X 5 , X 6 , X 7 , X 8 , X 9 , X 10 , X 11 , X 12 , X 13 , X 14 , X 15 , X 16 The probability of bit 1 in the bit stream is 1 / 2; this setting achieves the effect of scaling down the probability value of bit 1 in the bit stream output by the comparator by a factor of 0.5.

[0056] In this embodiment, the scaling bitstream is used. A 1 and A 2 With the largest negative correlation, scaled bitstream A 3 and A 4 It has the largest negative correlation. A 5 and A 6 With the largest negative correlation, scaled bitstream A 7 and A 8 It has the largest negative correlation. A 7 and A 8 With the largest negative correlation, scaled bitstream A 9 and A 10 It has the largest negative correlation. A 11 and A 12 With the largest negative correlation, scaled bitstream A 13 and A 14 With the largest negative correlation, scaled bitstream A 15 and A16 It has the largest negative correlation; all OR gates in the eight first-level average addition units perform addition operations, and after all clock cycles, the bit stream in Example 10... B 1 , B 2 , B 3 , B 4 The probability value P(bit 1) B 1 =1), P( B 2 =1), P( B 3 =1), P( B 4 =1) respectively with the bit stream in Example 7 B 1 , B 2 , B 3 , B 4 The probability value P(bit 1) B 1 =1), P( B 2 =1), P( B 3 =1), P( B 4 =1) are the same, while the bit stream in Example 10 is the same. B 5 and B 6 , B 7 and B 8 The probability value P(bit 1) B 5 =1), P( B 6 =1), P( B 7 =1), P( B 8 =1) is: ; ; ; ; S3-2: Perform mean addition calculation using the second-level mean addition unit. The specific steps are as follows: The eight first-level adder units are divided into four groups of two, and the two AND gates in each second-level average adder unit respectively receive the bits output by one group of first-level average adder units. Simultaneously, the flip-flops... D 2 of Q The output bits and flip-flops D 2 of The bits output from the terminals are also input to the two AND gates in the two-stage average addition unit, and the two AND gates perform AND logic operations on the input bits respectively; the OR gates in the two-stage average addition unit perform OR logic operations on the bits output from the two AND gates; from the perspective of all clock cycles, the bits output by the AND gates in the four-stage average addition units in all clock cycles form bit streams C1, C2, C3, C4, C5, C6, C7, and C8 in the timing order, and the bits output by the OR gates in the four-stage average addition units in all clock cycles form bit streams D1, D2, D3, and D4 in the timing order, respectively; S3-3: Perform mean addition calculation using a three-level mean addition unit. The specific steps are as follows: The four two-stage adder units are divided into two groups of two. Two AND gates in the three-stage mean adder unit each receive bits from the output of one group of two-stage mean adder units. Simultaneously, the flip-flops... D 3 of Q The output bits and flip-flops D 3 of The bits output from the terminals are also input to the two AND gates in the three-stage average addition unit. The two AND gates perform AND logic operations on the input bits, and the OR gate in the three-stage average addition unit performs OR logic operations on the bits output from the two AND gates. From the perspective of all clock cycles, the bits output by the AND gates in the two three-stage average addition units in all clock cycles form bit streams E1, E2, E3, and E4 in the timing order, and the bits output by the OR gates in the two three-stage average addition units in all clock cycles form bit streams F1 and F2 in the timing order. S3-4: Perform mean addition calculation using the four-level mean addition unit. The specific steps are as follows: The two AND gates in the fourth-level mean-add unit respectively receive bits from the outputs of the two third-level mean-add units, while the flip-flops... D 4 of Q The output bits and flip-flops D 4 of The bits output from the terminal are also input to the two AND gates in the four-stage average addition unit, and the two AND gates perform AND logic operations on the input bits respectively; the OR gate in the four-stage average addition unit performs OR logic operations on the bits output from the two AND gates; from the perspective of all clock cycles, the bits output by the AND gates in the four-stage average addition unit in all clock cycles form bit streams G1 and G2 in timing order; the bits output by the OR gate in the three-stage average addition unit in all clock cycles form bit stream Y in timing order. S4. The second counter receives the bits output from the OR gates in the three-stage average addition unit and the bits output from the OR gates in the DD-MAX unit. When the second counter detects a "0" in the bit output from the DD-MAX unit, it terminates the calculation of the bits output from the OR gates in the subsequent three-stage average addition unit, thus obtaining the average addition calculation result. That is, the binary number to be calculated x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 , x 9 , x 10 , x 11 , x 12 , x 13 , x 14 , x 15 , x 16 The result of the mean addition calculation; the result of the mean addition calculation y calculated by the second counter is equal to the probability of bit "1" appearing in bit stream Y; the probability of bit "1" appearing in bit stream Y is: ; The above-mentioned settings in this embodiment can effectively truncate the operation of invalid bits, and only perform calculations on the valid bits (i.e. valid calculation bits) in the bit stream output by the mean addition unit, thereby achieving a significant reduction in power consumption.

[0057] In this embodiment, the second counter calculates only the valid bits in the bitstream output by the four-stage average addition unit based on the bits output by the DD-MAX unit. When a "0" is detected in the bitstream output by the DD-MAX unit, the second counter terminates the calculation of subsequent bits, thus obtaining the average addition calculation result. This setting in this embodiment effectively truncates the operation of invalid bits, calculating only the valid bits (i.e., valid calculation bits) in the bitstream output by the average addition unit, thereby achieving a significant reduction in power consumption.

[0058] Example 11: A mean addition calculation device based on random calculation is provided in Embodiment 11. The difference between the mean addition calculation device based on random calculation described in Embodiment 10 is that the first counter and the second counter in Embodiment 11 are both 9-bit counters.

[0059] Example 12: A mean addition calculation device based on random calculation is provided in Embodiment Twelve. The difference between the mean addition calculation device based on random calculation described in Embodiment Ten is that the first counter and the second counter in Embodiment Twelve are both 10-bit counters.

[0060] test: The mean addition calculation devices described in Examples 1 to 12 were subjected to 20,000 Monte Carlo experiments using MATLAB, and their mean square error (MSE) was calculated. The results are shown in Table 1. This application uses the mean square error as a measure of calculation accuracy. In Table 1, 2 inputs indicate that there are two binary numbers to be calculated, 4 inputs indicate that there are four binary numbers to be calculated, 8 inputs indicate that there are eight binary numbers to be calculated, and 16 inputs indicate that there are sixteen binary numbers to be calculated.

[0061] As can be seen from Table 1, when the length of the input bitstream is 2... 8 When there are eight binary numbers to be calculated, the mean addition calculation device described in this embodiment has a calculation MSE error of 1.08 × 10⁻⁶. -5 When the length of the input bitstream is 2 9 When there are four binary numbers to be calculated, the mean addition calculation device described in this embodiment has a calculation MSE error of 1.41 × 10⁻⁶. -6 When the length of the input bitstream is 2 10 When there are sixteen binary numbers to be calculated, the mean addition calculation device described in this application has a calculation MSE error of 1.18 × 10⁻⁶. -6 Clearly, the mean addition calculation device described in this application has better calculation accuracy.

[0062] Table 1 shows the mean square error (MSE) of the multi-input average adder circuit under different input bitstream lengths.

[0063] Those skilled in the art will recognize that the above examples are intended to help readers understand the principles of the invention and should be understood as not limiting the scope of protection of the invention to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A mean addition calculation device based on random calculation, characterized in that: Including random bit stream generation unit and a The unit includes a mean addition unit; the random bitstream generation unit includes a first counter and comparators, the number of comparators being equal to the number of binary numbers to be calculated. X The same; the mean addition unit includes two AND gates and an OR gate connected to them; Calculate the number of levels based on X. n , ; Will a Each mean-addition unit is divided into n levels; When X=2, the two comparators are connected to a single-stage average addition unit; the flip-flop in the first counter... D 1 of End and The terminal is connected to a first-level mean addition unit; When X ≥ 4, the outputs of the X comparators are connected to different first-stage mean-adder units; flip-flops D 1 of Q End and Each terminal is connected to one of the two input terminals of each first-level mean-adding unit; two first-level mean-adding units are connected to one second-level mean-adding unit, and the trigger in the first counter... D 2 of Q End and Each terminal is connected to one of the two input terminals of each second-level mean-adding unit; and so on, until the output terminals of the two (n-1)-level mean-adding units are connected to the n-level mean-adding units, and the trigger in the first counter... D n of Q End and The terminals are respectively connected to the two input terminals of the n-stage mean addition unit; All comparators are connected to the DD-MAX unit; The mean addition unit and the DD-MAX unit are respectively connected to the input and enable terminals of the second counter; The second counter outputs the result of the mean addition calculation.

2. The mean addition calculation device based on random calculation according to claim 1, characterized in that: DD-MAX units include a One or a door.

3. The mean addition calculation device based on random calculation according to claim 1, characterized in that: When X=2, the mean addition unit is used as the first-level mean addition unit.

4. The mean addition calculation device based on random calculation according to claim 1, characterized in that: When X=4, the three mean addition units are divided into two levels of mean addition units: first-level mean addition units and second-level mean addition units. The first-level and second-level mean addition units are formed by dividing the three mean addition units according to the ratio of the number of mean addition units. : It is obtained by dividing it into proportions.

5. The mean addition calculation device based on random calculation according to claim 1, characterized in that: When X≥8, the mean addition unit is divided into n levels of mean addition units; the n levels of mean addition units are called first-level mean addition units, second-level mean addition units, ..., n-level mean addition units, respectively; the first-level to n-level mean addition units are formed by dividing all mean addition units according to the ratio of the number of mean addition units. : :...... It is obtained by dividing it into proportions.

6. The mean addition calculation device based on random calculation according to claim 1, characterized in that: When X=4, the outputs of the four comparators in the random bit stream generation unit are respectively connected to the first inputs of the AND gates in the four first-level average addition units; the second input of one AND gate in each first-level average addition unit is connected to the Q terminal of flip-flop D1, and the second input of the other AND gate in each first-level average addition unit is connected to the Q terminal of flip-flop D1. The outputs of both first-level average adders are connected to the inputs of the two AND gates in the second-level average adder; the other input of one AND gate in the second-level average adder is connected to the Q input of flip-flop D2, and the other input of the other AND gate is connected to the Q input of flip-flop D2. end.

7. The mean addition calculation device based on random calculation according to claim 1, characterized in that: When the number of binary numbers to be calculated, X, is greater than or equal to 8, the output of the comparator in the random bit stream generation unit is connected to the first input of the AND gate in different first-stage average addition units; the second input of one of the AND gates in each first-stage average addition unit is connected to flip-flop D1. In each first-level average addition unit, the second input of another AND gate is connected to flip-flop D1. The outputs of the two first-level average adder units are each connected to the two inputs of a second-level average adder unit; the other input of one AND gate in each second-level average adder unit is connected to the Q input of flip-flop D2, and the other input of the other AND gate is connected to the Q input of flip-flop D2. The process continues until the outputs of the two (n-1)-stage mean-adder units are connected to the two inputs of the n-stage mean-adder unit, and the other input of the AND gate in one of the n-stage mean-adder units is connected to a flip-flop D. n The Q input of one AND gate is connected to the other input of another AND gate, which is connected to the flip-flop D. n of end.

8. The mean addition calculation device based on random calculation according to claim 1, characterized in that: The second input port of each comparator is connected bit-by-bit to the Q terminals of all the flip-flops of the first counter.

9. A calculation method for a mean addition calculation device based on random calculation, characterized in that: The mean addition calculation device based on random calculation is the mean addition calculation device based on random calculation as described in any one of claims 1 to 8, and the calculation method of the mean addition calculation device based on random calculation includes the following steps: S1. The first counter generates a random number source and transmits the bits to the comparator respectively; S2. Input the binary number to be calculated into the comparator respectively; the comparator compares the digital signal output from the first counter with the digital signal input from the first input terminal of the comparator. When the digital signal input from the first input terminal of the comparator is greater than the digital signal output from the first counter, the comparator outputs bit "1"; when the digital signal input from the first input terminal of the comparator is less than the digital signal output from the first counter, the comparator outputs bit "0". S3. Perform mean addition calculation using the mean addition unit; S4. The second counter receives the bits output by the n-stage average addition unit and the DD-MAX unit. When the second counter detects that the bit output by the DD-MAX unit is "0", the second counter terminates the calculation of the subsequent output bits of the n-stage average addition unit and obtains the average addition calculation result.

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