Dynamic instruction replacement method and device, equipment and storage medium

Abstract

The invention provides a dynamic instruction replacement method and device, equipment and a storage medium, and the method comprises the steps: determining a to-be-optimized instruction group according to instruction operation information of a plurality of instruction groups, and obtaining a replacement instruction group corresponding to the to-be-optimized instruction group, the performance of the replacement instruction group is better than that of the to-be-optimized instruction group, and the performance of the replacement instruction group is better than that of the to-be-optimized instruction group; and storing the replacement instruction group to a pre-occupied virtual address field, if the to-be-processed current instruction stream comprises the to-be-optimized instruction group, skipping to the virtual address field to execute the replacement instruction group when executing to the to-be-optimized instruction group in the current instruction stream, and skipping to the current instruction stream after the execution of the replacement instruction group is finished, and executing instructions behind the instruction group to be optimized. According to the method and the device, function-level instruction replacement is realized, the program optimization cost is reduced, and the program running efficiency can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a dynamic instruction replacement method, apparatus, device, and storage medium. Background Technology

[0002] Dynamic code optimization techniques refer to optimizing code dynamically during runtime. Dynamic instruction replacement schemes are an important means of achieving dynamic code optimization.

[0003] In existing technologies, there are two ways to implement dynamic instruction replacement schemes. The first is a hardware solution, which reserves debugging interfaces during the chip design phase and triggers instruction replacement through hardware breakpoints. The second is through entry point hijacking, which uses jump instructions to jump to the replacement function, thereby achieving function-level replacement.

[0004] However, the first approach is difficult to implement dynamically in a production environment, and the types of instructions that can be modified are limited. The second approach only supports function-level replacement and cannot modify instructions within functions, and it also carries the risk of multi-threaded contention. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a dynamic instruction replacement method, apparatus, device, and storage medium to solve the problem of difficulty in implementing function-level instruction replacement in the prior art.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows: Firstly, this application provides a dynamic instruction replacement method, the method comprising: Based on the instruction execution information of multiple instruction groups, determine the instruction group to be optimized; Obtain the alternative instruction group corresponding to the instruction group to be optimized, wherein the performance of the alternative instruction group is better than that of the instruction group to be optimized; Store the replacement instruction set into a pre-occupied virtual address segment; If the current instruction stream to be processed includes the instruction group to be optimized, when the execution reaches the instruction group to be optimized in the current instruction stream, it jumps to the virtual address segment to execute the alternative instruction group. After the alternative instruction group is executed, it jumps back to the current instruction stream and executes the instructions following the instruction group to be optimized.

[0007] Optionally, determining the instruction group to be optimized based on instruction execution information of multiple instruction groups includes: During code execution, monitor the execution information of each instruction group; Based on the operational information of each instruction group, determine the instruction groups to be optimized from each instruction group.

[0008] Optionally, determining the instruction group to be optimized from each instruction group based on the operation information of each instruction group includes: Based on the operational information of each instruction group, identify the bottleneck instruction; Obtain the virtual address of the bottleneck instruction, and determine the context instruction of the bottleneck instruction based on the virtual address of the bottleneck instruction; The set of instructions to be optimized is generated based on the bottleneck instruction and the context instructions of the bottleneck instruction.

[0009] Optionally, before jumping to the virtual address segment to execute the replacement instruction group when execution reaches the instruction group to be optimized in the current instruction stream, and before jumping back to the current instruction stream and executing the instructions following the instruction group to be optimized after the replacement instruction group has been executed, the method further includes: Determine the starting position of the instruction group to be optimized in the current instruction stream; Insert a first jump instruction before the starting position; Determine the end position of the alternative instruction group within the virtual address segment; Insert a second jump instruction after the said end position.

[0010] Optionally, when execution reaches the instruction group to be optimized in the current instruction stream, the process jumps to the virtual address segment to execute the replacement instruction group, and after the replacement instruction group is executed, jumps back to the current instruction stream and executes the instructions following the instruction group to be optimized, including: When the first jump instruction in the current instruction stream is executed, it jumps to the virtual address segment to execute the alternative instruction group; When the replacement instruction group is completed and the second jump instruction is executed, the system jumps back to the current instruction stream and executes the instruction following the instruction group to be optimized.

[0011] Optionally, it also includes: Based on the instruction group to be optimized and the replacement instruction group, determine whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized; If so, the instruction group to be optimized in the original virtual address segment is replaced according to the replacement instruction group.

[0012] Optionally, determining whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized, based on the instruction group to be optimized and the replacement instruction group, includes: Determine the first instruction length of the instruction group to be optimized and the second instruction length of the replacement instruction group; If the length of the first instruction is greater than or equal to the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will be replaced. If the length of the first instruction is less than the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will not be replaced.

[0013] Optionally, the method further includes: If it is determined that the instruction group to be optimized will not be replaced in the original virtual address segment storing the instruction group to be optimized, then the pre-occupied virtual address segment will be retained; According to the jump relationship between the instruction group to be optimized in the original virtual address segment and the replacement instruction group in the pre-occupied virtual address segment, the instructions in the instruction group are executed sequentially.

[0014] Optionally, replacing the instruction group to be optimized in the original virtual address segment according to the replacement instruction group includes: Based on the usage of the instruction group to be optimized, determine whether the instruction group to be optimized should be replaced at the current time; If so, the instruction group to be optimized in the original virtual address segment is replaced to obtain the optimization result of the instruction group to be optimized.

[0015] Optionally, determining whether the instruction group to be optimized should be replaced at the current time based on its usage includes: Replace each instruction in the instruction group to be optimized with a preset instruction; If the preset instruction is executed, the count value is incremented by 1, the preset instruction is restored to the original instruction, and the original instruction corresponding to the preset instruction in the instruction group to be optimized is executed. If the count value does not change within a preset time, then the instruction group to be optimized is determined to be replaceable at the current time.

[0016] Optionally, replacing the instruction group to be optimized in the original virtual address segment to obtain the optimized result of the instruction group to be optimized includes: Starting from the last instruction of the instruction group to be optimized, each instruction of the instruction group to be optimized in the original virtual address segment is replaced sequentially with the instruction of the replacement instruction group; If the instruction length of the instruction group to be optimized is greater than the instruction length of the replacement instruction group, then the remaining positions of the instruction group to be optimized are replaced with preset filling instructions; Delete the pre-occupied virtual address segment, and use the instruction group in the original virtual address segment as the optimization result of the instruction group to be optimized.

[0017] Secondly, this application provides a dynamic instruction replacement device, the device comprising: The determination module is used to determine the instruction group to be optimized based on the instruction execution information of multiple instruction groups; The acquisition module is used to acquire the alternative instruction group corresponding to the instruction group to be optimized, wherein the performance of the alternative instruction group is better than that of the instruction group to be optimized; A storage module is used to store the replacement instruction set into a pre-occupied virtual address segment; The execution module is configured to, if the current instruction stream to be processed includes the instruction group to be optimized, jump to the virtual address segment when the execution reaches the instruction group to be optimized in the current instruction stream to execute the alternative instruction group, and after the alternative instruction group is executed, jump back to the current instruction stream and execute the instructions following the instruction group to be optimized.

[0018] Optionally, the determining module is specifically used for: During code execution, monitor the execution information of each instruction group; Based on the operational information of each instruction group, determine the instruction groups to be optimized from each instruction group.

[0019] Optionally, the determining module is specifically used for: Based on the operational information of each instruction group, identify the bottleneck instruction; Obtain the virtual address of the bottleneck instruction, and determine the context instruction of the bottleneck instruction based on the virtual address of the bottleneck instruction; The set of instructions to be optimized is generated based on the bottleneck instruction and the context instructions of the bottleneck instruction.

[0020] Optionally, the device further includes an insertion module for: Determine the starting position of the instruction group to be optimized in the current instruction stream; Insert a first jump instruction before the starting position; Determine the end position of the alternative instruction group within the virtual address segment; Insert a second jump instruction after the said end position.

[0021] Optionally, the execution module is specifically used for: When the first jump instruction in the current instruction stream is executed, it jumps to the virtual address segment to execute the alternative instruction group; When the replacement instruction group is completed and the second jump instruction is executed, the system jumps back to the current instruction stream and executes the instruction following the instruction group to be optimized.

[0022] Optionally, the device further includes a replacement module for: Based on the instruction group to be optimized and the replacement instruction group, determine whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized; If so, the instruction group to be optimized in the original virtual address segment is replaced according to the replacement instruction group.

[0023] Optionally, the replacement module is specifically used for: Determine the first instruction length of the instruction group to be optimized and the second instruction length of the replacement instruction group; If the length of the first instruction is greater than or equal to the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will be replaced. If the length of the first instruction is less than the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will not be replaced.

[0024] Optionally, the replacement module is specifically used for: If it is determined that the instruction group to be optimized will not be replaced in the original virtual address segment storing the instruction group to be optimized, then the pre-occupied virtual address segment will be retained; According to the jump relationship between the instruction group to be optimized in the original virtual address segment and the replacement instruction group in the pre-occupied virtual address segment, the instructions in the instruction group are executed sequentially.

[0025] Optionally, the replacement module is specifically used for: Based on the usage of the instruction group to be optimized, determine whether the instruction group to be optimized should be replaced at the current time; If so, the instruction group to be optimized in the original virtual address segment is replaced to obtain the optimization result of the instruction group to be optimized.

[0026] Optionally, the replacement module is specifically used for: Replace each instruction in the instruction group to be optimized with a preset instruction; If the preset instruction is executed, the count value is incremented by 1, the preset instruction is restored to the original instruction, and the original instruction corresponding to the preset instruction in the instruction group to be optimized is executed. If the count value does not change within a preset time, then the instruction group to be optimized is determined to be replaceable at the current time.

[0027] Optionally, the replacement module is specifically used for: Starting from the last instruction of the instruction group to be optimized, each instruction of the instruction group to be optimized in the original virtual address segment is replaced sequentially with the instruction of the replacement instruction group; If the instruction length of the instruction group to be optimized is greater than the instruction length of the replacement instruction group, then the remaining positions of the instruction group to be optimized are replaced with preset filling instructions; Delete the pre-occupied virtual address segment, and use the instruction group in the original virtual address segment as the optimization result of the instruction group to be optimized.

[0028] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of a dynamic instruction replacement method as described in any one of the first aspects.

[0029] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of a dynamic instruction replacement method as described in any one of the first aspects.

[0030] The beneficial effects of this application are as follows: Based on the instruction execution information of the instruction set, instruction sets that are frequently executed and have low performance can be identified as instruction sets to be optimized. By replacing the instruction sets to be optimized with higher-performance alternative instruction sets, the low-performance instructions can be replaced in a timely manner during program execution, thereby improving program efficiency. Furthermore, compared to function replacement in existing technologies, this application can modify any instruction within a function without recompiling, solving the needs of scenarios where the source code of compiled binary files and dynamic libraries cannot be modified. The types of instructions that can be modified are unrestricted, improving the fine-grainedness of instruction replacement. By storing the alternative instruction set in a pre-occupied virtual address segment and establishing a jump relationship between the context instructions of the instruction set to be optimized in the current instruction stream and the pre-occupied virtual address segment, the continuous execution of the instruction stream can be ensured without interrupting the original program logic. It also avoids the overhead of overall code analysis and recompiling, optimizing only the target instruction set, reducing optimization costs, and improving program execution efficiency.

[0031] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A flowchart of a dynamic instruction replacement method provided in an embodiment of this application is shown; Figure 2 This document illustrates a flowchart of a method for determining a group of instructions to be optimized, as provided in an embodiment of this application. Figure 3 This document illustrates a flowchart of generating a set of instructions to be optimized, according to an embodiment of this application. Figure 4 This document illustrates a flowchart illustrating the jump relationship between the current instruction stream and alternative instruction groups, as provided in an embodiment of this application. Figure 5 This application provides a flowchart illustrating the execution of the current instruction stream according to an embodiment. Figure 6 This document illustrates a flowchart of a method for replacing a group of instructions to be optimized, as provided in an embodiment of this application. Figure 7 This application provides a flowchart illustrating a method for determining whether to perform instruction substitution. Figure 8 This illustration shows a flowchart of executing the current instruction stream without execution replacement, according to an embodiment of this application. Figure 9 This application provides a flowchart illustrating how to determine whether to replace an instruction. Figure 10 This document illustrates a flowchart illustrating how to determine whether the current time of an instruction is replaceable, according to an embodiment of this application. Figure 11 This document illustrates a flowchart of an instruction substitution method provided in an embodiment of this application. Figure 12 An example diagram of an instruction substitution provided in an embodiment of this application is shown; Figure 13 This illustration shows a structural schematic diagram of a dynamic instruction replacement device provided in an embodiment of this application; Figure 14 A schematic diagram of the structure of an electronic device 140 provided in an embodiment of this application is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0036] Code optimization techniques include static code optimization and dynamic code optimization. Static code optimization involves converting binary instructions into assembly code for analysis, then analyzing the assembly code to identify the sequences that need to be replaced, replacing these sequences with assembly code, and finally recompiling the replaced assembly code into new binary executable code.

[0037] However, static code optimization relies solely on static information that can be determined at compile time, and cannot utilize dynamic information during program runtime. Furthermore, it requires recompilation to obtain new binary executable code, making it difficult to adapt to dynamic changes during program runtime. In addition, the effectiveness of static code optimization depends on the compiler implementation and code structure, and different compilers may have significantly different static optimization strategies, resulting in insufficient optimization effects.

[0038] Dynamic code optimization technology refers to optimizing the executing code segment during program execution by combining real-time execution data, directly replacing the original binary code, and obtaining new binary executable code without recompilation. Existing technologies implement dynamic instruction replacement schemes in two ways. The first is a hardware solution, which reserves debugging interfaces during the chip design phase and triggers instruction replacement through hardware breakpoints. However, this method requires reserving debugging interfaces during the chip design phase, supports only a limited number of breakpoints, cannot be dynamically deployed in a production environment, and restricts instruction modification.

[0039] The second method involves entry point hijacking, which jumps to the replacement function via a jump instruction and saves the original function using a trampoline mechanism, thus achieving function-level replacement. However, this method only supports function-level replacement and cannot modify the instructions inside the function. Furthermore, if multiple threads simultaneously perform entry point hijacking operations on the same function, thread conflicts may occur if there is no synchronization mechanism, or there may be a risk of multi-threaded contention during the process of saving the original function using the trampoline mechanism.

[0040] Therefore, improving the granularity of instruction substitution and reducing the maintenance overhead of instruction substitution have become problems that need to be solved.

[0041] Based on this, this application proposes a dynamic instruction replacement method. After the program code is compiled, during the runtime, the instructions in the program are monitored to determine the instruction group to be optimized and the replacement instruction group to replace the instruction group to be optimized. The replacement instruction group to be optimized is stored in a virtual address segment, and a jump relationship between the virtual address segment and the original address segment is established. This enables instruction replacement in dynamic code scenarios, reduces the maintenance overhead of instruction replacement, ensures instruction cache consistency, and improves running efficiency.

[0042] Figure 1 This is a flowchart illustrating a dynamic instruction replacement method provided in an embodiment of this application. The method of this application can be applied during program execution, and the executing entity of the method can be an electronic device. The following will combine... Figure 1 The overall process of the above method will be explained.

[0043] S101. Based on the instruction execution information of multiple instruction groups, determine the instruction group to be optimized.

[0044] When the application providing the service is in a high-concurrency scenario, frequent competitive access to a small portion of memory may lead to a performance bottleneck. In this case, there are some frequently executed hot instructions, such as memory access instructions or atomic instructions. These hot instructions can be identified as bottleneck instructions, and the instruction group to be optimized can be determined based on the bottleneck instructions.

[0045] The instruction set to be optimized can be a set of instructions whose performance needs to be optimized, and the instruction set to be optimized includes multiple instructions that are executed consecutively.

[0046] Optionally, instruction execution information may include at least one of the following: memory usage, CPU (Central Processing Unit) utilization, CPU time, number of instructions, number of times instruction memory access misses the cache, etc.

[0047] Optionally, the memory usage and CPU utilization of each instruction can be monitored during program execution. If the memory usage and / or CPU utilization of an instruction are greater than the preset usage threshold and the preset utilization threshold, the instruction can be identified as a bottleneck instruction, and the bottleneck instruction and its context instructions can be identified as a group of instructions to be optimized.

[0048] For example, if the CPU time of instruction A is greater than a preset time threshold, instruction A can be regarded as a bottleneck instruction, and instruction A and the context instructions of instruction A can be regarded as a group of instructions to be optimized.

[0049] The context instruction can be the instruction stored in the N adjacent memory locations above it and the instruction stored in the M adjacent memory locations below it, where M and N are both positive integers. This means that multiple consecutive instructions containing the same instruction can be grouped into an instruction group to be optimized. The instruction group to be optimized can be determined based on the functions it can perform. Each instruction group can complete a full function, and the values ​​of M and N can be determined according to the functions performed by the instruction group. Instruction groups with different functions can have different values ​​of M and N.

[0050] S102. Obtain the alternative instruction group corresponding to the instruction group to be optimized. The performance of the alternative instruction group is better than that of the instruction group to be optimized.

[0051] The replacement instruction group can be an instruction group that has the same function as the instruction group to be optimized, but with better performance. The number of instructions in the replacement instruction group can be the same as or different from the instruction group to be optimized.

[0052] Among them, the performance of the replacement instruction set is better than that of the instruction set to be optimized. This can be because the replacement instruction set has less memory usage, lower CPU utilization, shorter CPU time, or fewer cache misses when executing instructions compared to the instruction set to be optimized.

[0053] In one possible implementation, a correspondence can be pre-established between the instruction group to be optimized and the corresponding alternative instruction group. For example, each instruction group to be optimized can have a unique alternative instruction group, or multiple instruction groups to be optimized can correspond to the same alternative instruction group.

[0054] In one possible implementation, each instruction group to be optimized may also have multiple corresponding alternative instruction groups. When it is necessary to replace the instruction group to be optimized, a selection can be made from the multiple alternative instruction groups based on a preset selection strategy as the alternative instruction group corresponding to the instruction group to be optimized.

[0055] For example, each optional alternative instruction group can be simulated for execution to determine the optimal alternative instruction group under the current system operating state, and this optimal alternative instruction group can be selected as the alternative instruction group corresponding to the instruction group to be optimized. Alternatively, the address lengths of each optional alternative instruction group can be compared, and the alternative instruction group with the shortest address length can be selected as the alternative instruction group corresponding to the instruction group to be optimized.

[0056] S103. Store the replacement instruction set into the pre-occupied virtual address segment.

[0057] Optionally, the pre-occupied virtual address range can be an existing virtual address range that will not be used again during program execution or a newly mapped blank virtual address range.

[0058] In one possible implementation, after determining the instruction group to be optimized, a virtual address segment can be pre-allocated or a blank virtual address segment can be mapped in the virtual address segment, and this part of the virtual address segment can be used as the virtual address segment for storing the alternative instruction group corresponding to the instruction group to be optimized.

[0059] Optionally, the instructions in the substitution instruction group can be stored sequentially in a pre-occupied virtual address segment according to the order of instruction execution. For example, the first instruction in the substitution instruction group can be stored in the pre-occupied virtual address segment first, and then the remaining instructions in the substitution instruction group can be stored sequentially after the location where the first instruction is stored in the pre-occupied virtual address segment. Finally, the last instruction in the substitution instruction group can also be stored after the virtual address segment, thus completing the storage of the substitution instruction group into the virtual address segment.

[0060] Optionally, the length of the virtual address segment to be occupied can be determined based on the length of the alternative instruction group corresponding to the instruction group to be optimized. For example, after determining the instruction group to be optimized, the instruction length of the alternative instruction group corresponding to the instruction group to be optimized can be determined, and then the virtual address segment can be pre-occupied based on the instruction length. If there are multiple alternative instruction groups for the instruction group to be optimized, the virtual address segment can be pre-occupied based on the longest instruction length among the multiple alternative instruction groups.

[0061] S104. If the current instruction stream to be processed includes an instruction group to be optimized, when the execution reaches the instruction group to be optimized in the current instruction stream, jump to the virtual address segment to execute the substitute instruction group, and after the substitute instruction group is executed, jump back to the current instruction stream and execute the instructions after the instruction group to be optimized.

[0062] Optionally, after storing the replacement instruction group into a pre-occupied virtual address segment, a jump relationship can be established from the previous instruction adjacent to the instruction group to be optimized to the replacement instruction group, and a jump relationship can be established from the replacement instruction group to the next instruction adjacent to the instruction group to be optimized, forming a new instruction stream.

[0063] The length of the virtual address segment can be the length of the substitute instruction group plus a preset length value, so that the substitute instruction group and the jump instruction from the substitute instruction group back to the current instruction stream can be stored in the virtual address segment.

[0064] For example, suppose the instruction group to be optimized is instruction group A, which includes three instructions: A1, A2, and A3. The preceding instruction of the instruction group to be optimized in the current instruction stream is A0, and the following instruction is An. Then the current instruction stream can be represented as A0-A1-A2-A3-An. The replacement instruction group B of the instruction group to be optimized includes two instructions: B1 and B2. Therefore, a jump relationship can be established from instruction A0 to instruction B1, and a jump relationship can be established from instruction B2 to instruction An, forming a new instruction stream, which can be represented as A0-B1-B2-An.

[0065] The current instruction stream can be the instruction stream that the program is executing. The instruction stream can include at least one instruction group to be optimized. The number of instruction groups to be optimized can be at least one. Based on the above steps S101-S103, the alternative instruction group corresponding to each instruction group to be optimized is determined, and the jump relationship between each instruction group to be optimized and the alternative instruction group is established, thereby forming a new instruction stream.

[0066] When executing the instruction group to be optimized in the current instruction stream, that is, when executing the instruction adjacent to the previous instruction of the instruction group to be optimized in the current instruction stream, the jump can be made to the virtual address segment according to the constructed jump relationship, and the instructions of the substitute instruction group stored in the virtual address segment are executed in sequence. When executing the last instruction of the substitute instruction group in the virtual address segment, the jump can be made back to the next instruction adjacent to the instruction group to be optimized in the current instruction stream according to the constructed jump relationship.

[0067] As a preferred implementation, after establishing the jump relationship between the preceding and following instructions of the instruction group to be optimized and the alternative instruction group, the instruction group to be optimized can be further directly replaced with the alternative instruction group, that is, the instructions of the alternative instruction group are used to overwrite the instructions of the original instruction group to be optimized in the address range of the instruction group to be optimized.

[0068] In this embodiment, instruction groups with frequent execution and low performance can be identified as instruction groups to be optimized based on instruction execution information. By replacing these instruction groups with higher-performance alternative instruction groups, inefficient instructions can be replaced promptly during program execution, thereby improving program efficiency. Compared to existing static code optimization schemes, this application can modify any part of the instructions within a function without recompiling, solving the problem that the source code of compiled binary files and dynamic libraries cannot be modified. Furthermore, it can determine the instruction groups to be replaced by combining real-time execution information during program runtime, thus adapting to dynamic changes in program runtime scenarios and improving the effectiveness of code optimization. Compared to existing dynamic code optimization methods, this application can modify instructions within functions, and the types of instructions that can be modified are not limited, improving the fine-grainedness of instruction replacement. By storing the alternative instruction set in a pre-occupied virtual address segment, and then establishing the jump relationship between the context instruction of the instruction set to be optimized in the current instruction stream and the pre-occupied virtual address segment, the continuous execution of the instruction stream can be ensured without interrupting the original program logic. Furthermore, the overhead of overall code analysis and recompilation can be avoided. Optimization is only performed on the target instruction set, reducing optimization costs and improving program execution efficiency.

[0069] The following is a further explanation of how the instruction sets to be optimized were determined based on the instruction execution information of multiple instruction sets, such as... Figure 2 As shown, the above step S101 includes: S201. During code execution, monitor the execution information of each instruction group.

[0070] Optionally, functions in the code can be split into at least one basic block or loop body as instruction groups, and hook code can be inserted at the entry or exit of each instruction group to monitor the execution information of the instruction group.

[0071] In one possible implementation, monitoring code can be inserted into the instruction stream of the code to monitor the instructions in the instruction stream and obtain the execution information of each instruction.

[0072] The instruction execution information includes the number of times each instruction in the instruction group is executed, the average execution time of the instruction, the number of instruction cache misses, the memory usage rate during instruction execution, and the CPU utilization rate.

[0073] S202. Based on the operation information of each instruction group, determine the instruction group to be optimized from each instruction group.

[0074] Optionally, the execution information of each instruction group can be compared with preset indicator thresholds to determine the instruction groups that need optimization. These instruction groups are then disassembled to convert binary machine code into assembly instructions, and the resulting functional instruction groups are used as the instruction groups to be optimized. The execution information of an instruction group includes the execution information of each instruction within that group.

[0075] The preset threshold values ​​may include at least one of the following: execution frequency threshold, time consumption percentage threshold, cache miss count threshold, memory usage threshold, and CPU usage threshold.

[0076] In one possible implementation, the instruction groups can be sorted according to their execution information, and instruction groups that simultaneously exceed X thresholds can be filtered out. These instruction groups exceeding X thresholds are then identified as instruction groups to be optimized. For example, if the execution frequency exceeds the execution frequency threshold, the execution time exceeds the time percentage threshold, and the number of cache misses exceeds the number of cache misses threshold, then this instruction group can be identified as an instruction group to be optimized.

[0077] Optionally, the weight values ​​of runtime information can be determined based on actual needs. For example, in scenarios where execution time needs to be monitored, the average execution time of instructions can be given a larger weight, and instruction groups with longer execution times can be prioritized as instruction groups to be optimized.

[0078] In another possible implementation, a library of replaceable inefficient instruction patterns can be predefined, and instruction groups with the same instruction characteristics as those in the inefficient instruction pattern library can be located from the monitored instruction groups through pattern matching as instruction groups to be optimized.

[0079] For example, multiple consecutive load instructions targeting the same address can be added to an inefficient instruction pattern library. Pattern matching can then be used to identify these multiple consecutive load instructions targeting the same address in the current instruction stream as instruction groups to be optimized. During pattern matching, the instruction sequences in the instruction group can be matched with the instruction sequences in the inefficient instruction pattern library, and the number of times each instruction is repeatedly computed can be compared to determine whether the instructions in the current instruction stream are the same as the instruction groups in the inefficient instruction pattern library.

[0080] The following explains the steps for determining the instruction groups to be optimized from each instruction group based on the operational information of each instruction group. Figure 3 As shown, the above step S202 includes: S301. Determine the bottleneck instruction based on the operation information of each instruction group.

[0081] Bottleneck instructions can be those that are executed frequently, take a long time to execute, have a high memory usage rate, or have a high CPU usage rate during code execution.

[0082] The execution information of the instruction group includes the execution information of each instruction in the instruction group. Each instruction can be filtered based on a preset indicator threshold, thereby identifying the instruction that exceeds the indicator threshold as the bottleneck instruction.

[0083] In one possible implementation, different weight values ​​can be assigned to various indicators of the runtime information, and the instructions in the instruction group can be sorted according to the weight values ​​of each indicator, and the bottleneck instruction can be determined according to the sorting order.

[0084] S302. Obtain the virtual address of the bottleneck instruction and determine the context instruction of the bottleneck instruction based on the virtual address of the bottleneck instruction.

[0085] The virtual address of the bottleneck instruction can be the storage location of the bottleneck instruction in the virtual address space.

[0086] Optionally, the context instructions of the bottleneck instruction include the preceding instructions and the following instructions. The preceding instructions may be instructions stored in one or more virtual addresses adjacent to the virtual address of the bottleneck instruction in the virtual address space, and the following instructions may be instructions stored in one or more virtual addresses adjacent to the virtual address of the bottleneck instruction in the virtual address space.

[0087] S303. Generate a group of instructions to be optimized based on the bottleneck instruction and the context instructions of the bottleneck instruction.

[0088] In one possible implementation, the bottleneck instruction and its context instructions can be combined in the order of instruction execution to obtain the instruction group to be optimized.

[0089] In another possible implementation, the N preceding instructions and the M following instructions of the bottleneck instruction can be combined in the order of instruction execution to obtain the instruction group to be optimized.

[0090] When execution reaches the instruction group to be optimized in the current instruction stream, a jump is made to the virtual address segment to execute the alternative instruction group. After the alternative instruction group has been executed, a jump is made back to the current instruction stream, and before the instructions following the instruction group to be optimized are executed, such as... Figure 4 As shown, the method of this application further includes: S401. Determine the starting position of the instruction group to be optimized in the current instruction stream.

[0091] S402, Insert the first jump instruction before the starting position.

[0092] S403. Determine the end position of the substitution instruction group in the virtual address segment.

[0093] S404. Insert a second jump instruction after the end position.

[0094] Optionally, the starting position of the instruction group to be optimized in the current instruction stream can be the position of the first instruction in the instruction group to be optimized in the current instruction stream. After determining the starting position, a first jump instruction can be inserted before the first instruction of the instruction group to be optimized and after the adjacent previous instruction of the instruction group to be optimized in the current instruction stream.

[0095] The first jump instruction is used to jump from the previous instruction adjacent to the instruction group to be optimized in the current instruction stream to the first instruction in the virtual address segment. The instruction parameters of the first jump instruction include the memory address of the first instruction in the virtual address segment, or the offset from the previous instruction adjacent to the instruction group to be optimized in the current instruction stream to the first instruction in the virtual address segment.

[0096] Optionally, the end position of the substitution instruction group in the virtual address segment can be the position of the last instruction in the substitution instruction group within the virtual address segment. After determining the end position, a second jump instruction can be inserted after the last instruction of the substitution instruction group.

[0097] The second jump instruction is used to jump from the last instruction of the virtual address segment to the next instruction adjacent to the instruction group to be optimized in the current instruction stream. The instruction parameters of the second jump instruction include the memory address of the next instruction adjacent to the instruction group to be optimized in the current instruction stream, or the offset from the last instruction of the virtual address segment to the next instruction adjacent to the instruction group to be optimized in the current instruction stream.

[0098] For example, suppose the current instruction stream is A0-A1-A2-A3-An, the instruction group A to be optimized includes three instructions: A1, A2, and A3, and the replacement instruction group B includes two instructions: B1 and B2. The first jump instruction is represented by E, and the second jump instruction is represented by D. First, determine the starting position of the instruction group to be optimized in the current instruction stream as before A1 and after A0. Insert the first jump instruction at the starting position to achieve a jump from the current instruction stream to the virtual address segment where the replacement instruction group is located. Then, determine the ending position of the replacement instruction group in the virtual address segment as after B2. Insert the second jump instruction after the ending position and set the jump back position of the second jump instruction to instruction An after the instruction group A to be optimized in the current instruction stream. Then the new instruction stream can be represented as A0-E-B1-B2-D-An, thereby achieving the replacement of the instruction group to be optimized with the replacement instruction group.

[0099] After adding the first and second jump instructions to the current instruction stream and establishing a jump relationship between the current instruction stream and the replacement instruction group to obtain a new instruction stream, the above steps, when executing to the instruction group to be optimized in the current instruction stream, jump to the virtual address segment to execute the replacement instruction group, and after the replacement instruction group has been executed, jump back to the current instruction stream and execute the instructions following the instruction group to be optimized, as follows: Figure 5 As shown, it includes: S501. When the first jump instruction in the current instruction stream is executed, jump to the virtual address segment to execute the alternative instruction group.

[0100] Optionally, when executing the first jump instruction in the current instruction stream, the target memory address can be determined based on the parameters of the first jump instruction, and the jump can proceed to the target memory address. Here, the target memory address is the address of the first instruction in the virtual address segment, and the parameters of the first jump instruction can be the offset of the target memory address relative to the current instruction, or the target memory address itself.

[0101] S502. When the replacement instruction group is completed and the second jump instruction is executed, jump back to the current instruction stream and execute the instruction after the instruction group to be optimized.

[0102] After executing the first jump instruction and jumping to the virtual address segment, the substitute instruction group can be executed sequentially from the first instruction in the storage order in the virtual address segment. When the last instruction in the substitute instruction group is completed, the substitute instruction group can be considered to have been completed, and the second jump instruction is executed in the order of the instruction flow.

[0103] When executing the second jump instruction, the target memory address can be determined based on the parameters in the second jump instruction. At this time, the target memory address is the memory address of the next instruction adjacent to the instruction group to be optimized in the current instruction stream, and the jump is made to the instruction indicated by the target memory address.

[0104] In this embodiment, by constructing the jump relationship between the adjacent context instructions of the instruction group to be optimized and the alternative instruction group, when the instruction group to be optimized in the current instruction stream is executed, it can automatically jump to the alternative instruction group with better performance, and after the alternative instruction group is executed, it can automatically jump back to the next instruction of the instruction group to be optimized in the current instruction stream, thereby realizing instruction replacement and improving the performance and efficiency of program operation.

[0105] As a preferred implementation, to further improve code execution efficiency, after constructing the jump relationship between the adjacent context instructions and the alternative instruction group of the instruction group to be optimized in the current instruction stream, the alternative instruction group can be further used to cover the instruction group to be optimized, thereby reducing the number of instruction jumps. For example... Figure 6 As shown, the method of this application further includes: S601. Based on the instruction group to be optimized and the replacement instruction group, determine whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized.

[0106] The original virtual address segment can be the virtual address segment of the instruction in the instruction group to be optimized in the virtual address space.

[0107] Optionally, when determining whether to replace the instruction group to be optimized in the original virtual address segment, the thread's instruction operation can be paused first. This ensures that other threads will not execute the instructions in the instruction group to be optimized during the replacement process, thus avoiding competition between threads or execution errors caused by threads executing replacement instructions. If it is not possible to pause the thread's instruction execution operation at present, then it is determined not to replace the instruction group to be optimized in the original virtual address segment.

[0108] In one possible implementation, the decision to replace the instruction group to be optimized in the original virtual address segment can be determined based on the instruction length of the instruction group to be optimized and the instruction length of the replacement instruction group. If the instruction length of the instruction group to be optimized is greater than or equal to the instruction length of the replacement instruction group, it means that the length of the original virtual address is sufficient to accommodate the replacement instruction group, and instruction replacement can be performed in this case.

[0109] It should be noted that if there are multiple instruction groups to be optimized that need to be replaced in the current instruction stream of the program, the instruction groups to be optimized can be replaced one by one according to the execution order of the instruction groups to be optimized in the current instruction stream, starting from the earliest executed instruction group, and the instruction groups to be optimized in the original virtual address should be replaced with the corresponding alternative instruction groups.

[0110] S602. If so, then replace the instruction group to be optimized in the original virtual address segment according to the replacement instruction group.

[0111] In one possible implementation, if the instruction length of the replacement instruction group is the same as the instruction length of the instruction group to be optimized, then the instructions in the replacement instruction group can be filled into the original virtual address segment in the order of instruction execution. That is, the instructions in the replacement instruction group are used to overwrite the instructions in the instruction group to be optimized in the original virtual address segment from front to back in the order of instruction execution.

[0112] In another possible implementation, if the instruction length of the replacement instruction group is less than the instruction length of the instruction group to be optimized, the difference N between the instruction length of the instruction group to be optimized and the instruction length of the replacement instruction group can be calculated. The difference N is used as the instruction length to be filled. Then, the first N instructions are filled with preset instructions in the original virtual address segment, or the last N instructions are filled with preset instructions, or the first x instructions and the last y instructions are selected in the original virtual address segment to fill the preset instructions, where the sum of x and y is N. The remaining positions are then filled with instructions from the replacement instruction group in sequence to cover each instruction of the instruction group to be optimized.

[0113] The following is a further explanation of the above method for determining whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized, based on the instruction group to be optimized and the replacement instruction group. Figure 7 As shown, the above step S602 includes: S701. Determine the first instruction length of the instruction group to be optimized and the second instruction length of the replacement instruction group.

[0114] Optionally, the first instruction length may be the number of instructions in the instruction group to be optimized or the length of the virtual address segment occupied by all instructions in the instruction group to be optimized, and the second instruction length may be the number of instructions in the replacement instruction group or the length of the virtual address segment occupied by all instructions in the replacement instruction group.

[0115] S702. If the length of the first instruction is greater than or equal to the length of the second instruction, then determine to replace the instruction group to be optimized in the original virtual address segment.

[0116] S703. If the length of the first instruction is less than the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will not be replaced.

[0117] In one possible implementation, the instruction code of the instruction group to be optimized can be parsed using a disassembler to obtain the first instruction length, and the instruction code of the replacement instruction group can be parsed using a disassembler to obtain the second instruction length.

[0118] If the length of the first instruction is greater than or equal to the length of the second instruction, it means that the original virtual address segment of the instruction group to be optimized has sufficient space, and the original virtual address segment can be directly replaced. If the length of the second instruction is greater than the length of the first instruction, it means that the original virtual address segment cannot accommodate the replacement instruction group, and in this case, the pre-occupied virtual address segment needs to be reserved.

[0119] For example, assuming the instruction group to be optimized is a non-LES instruction group, and the replacement instruction group is an LES instruction group (Load Segment and Effective Address), the instruction group to be optimized can be disassembled to obtain the first instruction length n=16. Based on the instruction encoding rules of the ARM (Advanced RISC Machines) architecture, the second instruction length m=4 is determined. Since n>m, it is determined that the original virtual address segment can accommodate the replacement instruction group. Therefore, each instruction in the instruction group to be optimized is sequentially replaced with an instruction in the replacement instruction group, and the remaining space is filled with preset instructions, completing the replacement of the instruction group to be optimized.

[0120] As one possible implementation, if the length of the first instruction is less than the length of the second instruction, it can be further determined whether the original virtual address segment can be dynamically expanded so that the expanded virtual address segment can accommodate the replacement instruction set. If the original virtual address segment is constrained by the memory page size, it can be determined whether there is extra space to accommodate the replacement instruction set by combining page alignment. For example, if the sum of the lengths of the original virtual address segment and the remaining usable space is greater than the length of the second instruction, and the replacement instruction set does not cross pages, and there is no additional page table switching overhead due to page crossing, then the original virtual address segment can be expanded, and the replacement instruction set can be filled into the expanded original virtual address segment.

[0121] This application embodiment directly replaces the instructions to be optimized stored in the original virtual address segment, which can avoid additional address jump overhead and further improve the efficiency of program operation. Optionally, if the instruction group to be optimized in the original virtual address segment is not replaced, such as Figure 8 As shown, the method of this application further includes: S801. If it is determined that the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized will not be replaced, then the pre-occupied virtual address segment will be retained.

[0122] Optionally, independent executable permissions can be applied for pre-occupied virtual address segments to ensure that the alternative instruction set can be directly executed by the CPU. Fixed addresses can be assigned to pre-occupied virtual address segments to ensure that the address segments are not randomly assigned by the system and to avoid address conflicts.

[0123] S802. Execute the instructions in the instruction group sequentially according to the jump relationship between the instruction group to be optimized in the original virtual address segment and the replacement instruction group in the pre-occupied virtual address segment.

[0124] Specifically, executing instructions according to jump relationships can involve executing the first jump instruction to the virtual address segment, sequentially executing the substitute instruction group stored in the virtual address segment, then executing the second jump instruction after the substitute instruction group in the virtual address segment, jumping back to the instructions after the instruction group to be optimized in the current instruction stream, and continuing to execute the current instruction stream.

[0125] In this embodiment, if the length of the first instruction of the instruction group to be optimized is less than the length of the second instruction of the replacement instruction group, and it is not possible to replace it in the original virtual address segment, the pre-occupied virtual address segment can be retained, and the instruction stream can be maintained through jump relationships to avoid program crashes caused by instruction length exceeding the limit, and to ensure the continuity of instruction stream execution.

[0126] The following is a further explanation of the replacement of the instruction group to be optimized in the original virtual address segment based on the substitution instruction group, such as... Figure 9 As shown, the above step S602 includes: S901. Based on the usage of the instruction group to be optimized, determine whether the instruction group to be optimized should be replaced at the current time.

[0127] The usage status of the instruction set to be optimized can indicate whether the instruction set to be optimized is being used by a thread, whether a thread is loading the instruction set to be optimized into the CPU cache, or whether the instruction set to be optimized has not been loaded and used by a thread within a preset period of time.

[0128] For example, the execution status of each thread can be monitored to determine whether any thread's program counter points to the address range of the instruction set to be optimized. If so, the instruction set to be optimized is being used by the thread.

[0129] In another example, based on instruction dependencies, it can be determined whether any thread has already loaded the instructions of the instruction group to be optimized into the CPU cache. If so, it can be determined not to replace the instruction group to be optimized at the current time, thereby avoiding the retention of old instructions in the cache after replacement.

[0130] S902. If so, replace the instruction group to be optimized in the original virtual address segment to obtain the optimization result of the instruction group to be optimized.

[0131] Optionally, if the current time allows for the replacement of the instruction group to be optimized, then starting from the last instruction at the end of the instruction group to be optimized, the last instruction of the instruction group to be optimized can be replaced with the last instruction of the replacement instruction group, and so on, replacing each instruction of the instruction group to be optimized sequentially backwards until the first instruction of the instruction group to be optimized is reached. By starting the instruction replacement from the last instruction of the instruction group to be optimized, the thread can be prevented from jumping to the replacement instruction group that has not been completely replaced due to replacing from the beginning.

[0132] In one possible implementation, when replacing instructions in the instruction group to be optimized with a replacement instruction group, an external process can be used to suspend all threads' execution of the instruction group, thereby preventing the program from executing the instruction group to be optimized that has not been completely replaced. In this case, instruction replacement can begin from the first instruction of the instruction group to be optimized, or it can begin from the last instruction.

[0133] After replacing each instruction in the instruction group to be optimized, the virtual address segment pre-occupied by the replacement instruction group can be released, and the instruction stream obtained after replacement can be saved as an instruction stream for subsequent execution.

[0134] The following section further explains the steps for determining whether to replace the instruction group to be optimized at the current time based on its usage. Figure 10 As shown, the above S901 step includes: S1001. Replace each instruction in the instruction group to be optimized with a preset instruction.

[0135] Among them, the preset instruction can be a placeholder instruction that does not affect the program logic and is only used to mark whether the instruction is executed.

[0136] S1002. If a preset instruction is executed, the counter value is incremented by 1, the preset instruction is restored to the original instruction, and the original instruction corresponding to the preset instruction in the instruction group to be optimized is executed.

[0137] Optionally, the counter value is used to record the number of times a preset instruction is executed, reflecting the activity level of the instruction group to be optimized. If the counter value changes, it indicates that the instruction group to be optimized is being executed by a thread.

[0138] S1003. If the count value does not change within the preset time, then the instruction group to be optimized is determined to be replaceable at the current time.

[0139] The preset time can be a monitoring window that covers the multi-threaded scheduling cycle. If the count value does not change within the preset time, it means that no thread is executing the instructions of the instruction group to be optimized. In this case, replacing the instruction group to be optimized will not cause the risk of thread competition.

[0140] In this embodiment, the usage of the instruction group to be optimized by the thread can be quantified by the count value, thereby ensuring that the replacement of the instruction group to be optimized will not cause the risk of thread competition and accurately determine the timing of the replacement instruction.

[0141] The following is a further explanation of the optimization results obtained by replacing the instruction group to be optimized in the original virtual address segment, as described above. Figure 11 As shown, the above S902 step includes: S1101. Starting from the last instruction of the instruction group to be optimized, replace each instruction of the instruction group to be optimized in the original virtual address segment with the instructions of the replacement instruction group in sequence.

[0142] The last instruction in the instruction group to be optimized can be the instruction at the end of the instruction group. Starting from the end of the instruction group to be optimized, each instruction is replaced sequentially towards the beginning.

[0143] S1102. If the instruction length of the instruction group to be optimized is greater than the instruction length of the replacement instruction group, then the remaining positions of the instruction group to be optimized will be replaced with preset padding instructions.

[0144] Among them, the preset fill instruction can be a no-operation instruction, such as the nop instruction.

[0145] For example, assuming the instruction group to be optimized is represented as A1, A2, A3, and the replacement instruction group is represented as B1, B2, then starting from the last instruction A3 of the instruction group to be optimized, A3 can be replaced with B2, A2 can be replaced with B1, and the redundant instruction A1 can be replaced with the nop instruction.

[0146] S1103. Delete the pre-occupied virtual address segment and use the instruction group in the original virtual address segment as the optimization result of the instruction group to be optimized.

[0147] After replacing the instruction set that is to be optimized, the pre-occupied virtual address segment can be deleted to avoid wasting memory resources. At this point, the replacement instruction set takes effect directly in the original virtual address segment without relying on external virtual address segments for jumps. This allows the instruction replacement to be completed in the original virtual address segment, ensuring cache consistency of the new instructions in the original address space and thus improving program execution efficiency.

[0148] As another possible implementation, the instruction length difference p between the instruction group to be optimized and the replacement instruction group can be determined first, and p nop instructions can be filled in starting from the first instruction of the instruction group to be optimized. Then, the instructions of the replacement instruction group can be filled in the remaining original virtual address segment in sequence to complete the replacement of the instruction group to be optimized.

[0149] For example, Figure 12 This is a flowchart illustrating instruction substitution based on the method described in this application. It can replace a conventional atomic addition operation with the LSE version of the single atomic addition instruction `ldadd`, thereby improving program execution efficiency. (See reference...) Figure 12 A first jump instruction "b new_code" can be added before the instruction group to be optimized, and a second jump instruction "b bafter" can be added after the replacement instruction group. This establishes a jump relationship between the current instruction flow and the pre-occupied virtual address segment. Then, the instruction lengths of the instruction group to be optimized and the replacement instruction group are compared to confirm that the instruction group to be optimized can be replaced in the original virtual address segment. Then, starting from the last instruction of the instruction group to be optimized, the replacement is performed, replacing the last instruction with "ldadd" from the replacement instruction group, and filling the remaining positions with nop instructions to obtain the final instruction flow.

[0150] Each assembly instruction has a corresponding binary instruction. The conventional atomic addition operation is replaced with the LSE version of the single atomic addition instruction ldadd, which replaces its corresponding binary instruction.

[0151] In another example, when data is accessed only once, it is more beneficial for other processes to update the data if it is not loaded into the cache. In this case, the LSE atomic load instruction can be used to replace the ordinary load instruction. The instruction replacement method is the same as in the example above, and will not be described in detail here.

[0152] Based on the same inventive concept, this application also provides a dynamic instruction replacement device corresponding to the dynamic instruction replacement method. Since the principle of the device in this application is similar to the dynamic instruction replacement method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0153] Figure 13 A schematic diagram of the structure of a dynamic instruction replacement device provided in an embodiment of this application is shown.

[0154] The determination module 1301 is used to determine the instruction group to be optimized based on the instruction execution information of multiple instruction groups; The acquisition module 1302 is used to acquire the alternative instruction group corresponding to the instruction group to be optimized. The performance of the alternative instruction group is better than that of the instruction group to be optimized. Storage module 1303 is used to store the replacement instruction set into a pre-occupied virtual address segment; The execution module 1304 is configured to, if the current instruction stream to be processed includes an instruction group to be optimized, jump to a virtual address segment when the execution reaches the instruction group to be optimized in the current instruction stream to execute a substitute instruction group, and after the substitute instruction group has been executed, jump back to the current instruction stream and execute the instructions following the instruction group to be optimized.

[0155] Optionally, module 1301 is specifically used for: During code execution, monitor the execution information of each instruction group; Based on the operational information of each instruction group, determine the instruction groups to be optimized from each instruction group.

[0156] Optionally, the determination module 1301 is specifically used for: Based on the operational information of each instruction group, identify the bottleneck instruction; Obtain the virtual address of the bottleneck instruction and determine the context instruction of the bottleneck instruction based on the virtual address of the bottleneck instruction; Generate a set of instructions to be optimized based on the bottleneck instruction and its context instructions.

[0157] Optionally, the device further includes an insertion module for: Determine the starting position of the instruction group to be optimized in the current instruction stream; Insert the first jump instruction before the starting position; Determine the end position of the replacement instruction group in the virtual address segment; Insert a second jump instruction after the end position.

[0158] Optionally, the execution module 1304 is specifically used for: When the first jump instruction in the current instruction stream is executed, the execution jumps to the virtual address segment to execute the alternative instruction group; When the replacement instruction group has finished executing and the second jump instruction has been executed, jump back to the current instruction stream and execute the instructions following the instruction group to be optimized.

[0159] Optionally, the device further includes a replacement module for: Based on the instruction group to be optimized and the replacement instruction group, determine whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized; If so, the instruction group to be optimized in the original virtual address segment is replaced according to the replacement instruction group.

[0160] Optionally, the replacement module is specifically used for: Determine the first instruction length of the instruction group to be optimized and the second instruction length of the replacement instruction group; If the length of the first instruction is greater than or equal to the length of the second instruction, then the instruction group to be optimized in the original virtual address segment is to be replaced. If the length of the first instruction is less than the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will not be replaced.

[0161] Optionally, the replacement module is specifically used for: If it is determined that the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized will not be replaced, then the pre-occupied virtual address segment will be retained; Based on the jump relationship between the instruction group to be optimized in the original virtual address segment and the replacement instruction group in the pre-occupied virtual address segment, the instructions in the instruction group are executed sequentially.

[0162] Optionally, the replacement module is specifically used for: Based on the usage of the instruction group to be optimized, determine whether the instruction group to be optimized should be replaced at the current time; If so, the instruction group to be optimized in the original virtual address segment is replaced to obtain the optimization result of the instruction group to be optimized.

[0163] Optionally, the replacement module is specifically used for: Replace each instruction in the instruction group to be optimized with a preset instruction; If the preset instruction is executed, the counter value is incremented by 1, the preset instruction is restored to the original instruction, and the original instruction corresponding to the preset instruction in the instruction group to be optimized is executed. If the count value does not change within the preset time, it is determined that the instruction group to be optimized can be replaced at the current time.

[0164] Optionally, the replacement module is specifically used for: Starting from the last instruction of the instruction group to be optimized, replace each instruction of the instruction group to be optimized in the original virtual address segment with the instructions of the replacement instruction group in turn; If the instruction length of the instruction group to be optimized is greater than the instruction length of the replacement instruction group, then the remaining positions of the instruction group to be optimized will be replaced with preset padding instructions. Delete the pre-occupied virtual address segment, and use the instruction group in the original virtual address segment as the optimization result of the instruction group to be optimized.

[0165] In this embodiment, instruction groups with frequent execution and low performance can be identified as instruction groups to be optimized based on instruction execution information. By replacing these instruction groups with higher-performance alternative instruction groups, inefficient instructions can be replaced promptly during program execution, thereby improving program efficiency. Furthermore, compared to function replacement in existing technologies, this application allows modification of any instruction within a function without recompiling, addressing the needs of scenarios where source code cannot be modified, such as compiled binary files and dynamic libraries. The types of instructions that can be modified are unrestricted, improving the fine-grainedness of instruction replacement. By storing the alternative instruction groups in a pre-occupied virtual address segment and establishing a jump relationship between the context instructions of the instruction group to be optimized in the current instruction stream and the pre-occupied virtual address segment, continuous execution of the instruction stream can be ensured without interrupting the original program logic. This also avoids the overhead of overall code analysis and recompiling, optimizing only the target instruction group, reducing optimization costs, and improving program efficiency.

[0166] Figure 14 A schematic diagram of the structure of an electronic device 140 provided in an embodiment of this application is shown, including: a processor 1401, a storage medium 1402, and a bus 1403. The storage medium 1402 stores machine-readable instructions executable by the processor 1401. When the electronic device runs a dynamic instruction replacement method as described in the embodiment, the processor 1401 communicates with the storage medium 1402 through the bus 1403. The processor 1401 executes the machine-readable instructions. The preamble of the method item of the processor 1401 executes the steps in the above-mentioned dynamic instruction replacement method.

[0167] This application also provides a computer-readable storage medium storing a computer program that is executed by a processor, wherein the processor performs the steps of the above-described dynamic instruction replacement method.

[0168] In this embodiment, the computer program, when run by the processor, can also execute other machine-readable instructions to perform other methods as described in the embodiments. For details on the specific execution steps and principles, please refer to the description of the embodiments, which will not be repeated here.

[0169] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0170] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0171] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0172] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0173] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0174] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A dynamic instruction replacement method, characterized in that, include: Based on the instruction execution information of multiple instruction groups, determine the instruction group to be optimized; Obtain the alternative instruction group corresponding to the instruction group to be optimized, wherein the performance of the alternative instruction group is better than that of the instruction group to be optimized; Store the replacement instruction set into a pre-occupied virtual address segment; If the current instruction stream to be processed includes the instruction group to be optimized, when the execution reaches the instruction group to be optimized in the current instruction stream, it jumps to the virtual address segment to execute the alternative instruction group. After the alternative instruction group is executed, it jumps back to the current instruction stream and executes the instructions following the instruction group to be optimized.

2. The method according to claim 1, characterized in that, The step of determining the instruction group to be optimized based on the instruction execution information of multiple instruction groups includes: During code execution, monitor the execution information of each instruction group; Based on the operational information of each instruction group, determine the instruction groups to be optimized from each instruction group.

3. The method according to claim 2, characterized in that, The step of determining the instruction group to be optimized from each instruction group based on the operation information of each instruction group includes: Based on the operational information of each instruction group, identify the bottleneck instruction; Obtain the virtual address of the bottleneck instruction, and determine the context instruction of the bottleneck instruction based on the virtual address of the bottleneck instruction; The set of instructions to be optimized is generated based on the bottleneck instruction and the context instructions of the bottleneck instruction.

4. The method according to claim 1, characterized in that, When execution reaches the instruction group to be optimized in the current instruction stream, the process jumps to the virtual address segment to execute the replacement instruction group. After the replacement instruction group is executed, the process jumps back to the current instruction stream and executes the instructions following the instruction group to be optimized, but before executing the instructions following the replacement instruction group: Determine the starting position of the instruction group to be optimized in the current instruction stream; Insert a first jump instruction before the starting position; Determine the end position of the alternative instruction group within the virtual address segment; Insert a second jump instruction after the said end position.

5. The method according to claim 4, characterized in that, When execution reaches the instruction group to be optimized in the current instruction stream, the process jumps to the virtual address segment to execute the replacement instruction group. After the replacement instruction group is executed, the process jumps back to the current instruction stream and executes the instructions following the instruction group to be optimized, including: When the first jump instruction in the current instruction stream is executed, it jumps to the virtual address segment to execute the alternative instruction group; When the replacement instruction group is completed and the second jump instruction is executed, the system jumps back to the current instruction stream and executes the instruction following the instruction group to be optimized.

6. The method according to any one of claims 1-5, characterized in that, Also includes: Based on the instruction group to be optimized and the replacement instruction group, determine whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized; If so, the instruction group to be optimized in the original virtual address segment is replaced according to the replacement instruction group.

7. The method according to claim 6, characterized in that, The step of determining whether to replace the instruction group to be optimized in the original virtual address segment storing the instruction group to be optimized, based on the instruction group to be optimized and the replacement instruction group, includes: Determine the first instruction length of the instruction group to be optimized and the second instruction length of the replacement instruction group; If the length of the first instruction is greater than or equal to the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will be replaced. If the length of the first instruction is less than the length of the second instruction, then it is determined that the instruction group to be optimized in the original virtual address segment will not be replaced.

8. The method according to claim 6, characterized in that, The method further includes: If it is determined that the instruction group to be optimized will not be replaced in the original virtual address segment storing the instruction group to be optimized, then the pre-occupied virtual address segment will be retained; According to the jump relationship between the instruction group to be optimized in the original virtual address segment and the replacement instruction group in the pre-occupied virtual address segment, the instructions in the instruction group are executed sequentially.

9. The method according to claim 6, characterized in that, The step of replacing the instruction group to be optimized in the original virtual address segment according to the replacement instruction group includes: Based on the usage of the instruction group to be optimized, determine whether the instruction group to be optimized should be replaced at the current time; If so, the instruction group to be optimized in the original virtual address segment is replaced to obtain the optimization result of the instruction group to be optimized.

10. The method according to claim 9, characterized in that, The step of determining whether the instruction group to be optimized should be replaced at the current time based on its usage includes: Replace each instruction in the instruction group to be optimized with a preset instruction; If the preset instruction is executed, the count value is incremented by 1, the preset instruction is restored to the original instruction, and the original instruction corresponding to the preset instruction in the instruction group to be optimized is executed. If the count value does not change within a preset time, then the instruction group to be optimized is determined to be replaceable at the current time.

11. The method according to claim 9, characterized in that, The step of replacing the instruction group to be optimized in the original virtual address segment to obtain the optimization result of the instruction group to be optimized includes: Starting from the last instruction of the instruction group to be optimized, each instruction of the instruction group to be optimized in the original virtual address segment is replaced sequentially with the instruction of the replacement instruction group; If the instruction length of the instruction group to be optimized is greater than the instruction length of the replacement instruction group, then the remaining positions of the instruction group to be optimized are replaced with preset filling instructions; Delete the pre-occupied virtual address segment, and use the instruction group in the original virtual address segment as the optimization result of the instruction group to be optimized.

12. A dynamic instruction replacement device, characterized in that, include: The determination module is used to determine the instruction group to be optimized based on the instruction execution information of multiple instruction groups; The acquisition module is used to acquire the alternative instruction group corresponding to the instruction group to be optimized, wherein the performance of the alternative instruction group is better than that of the instruction group to be optimized; A storage module is used to store the replacement instruction set into a pre-occupied virtual address segment; The execution module is configured to, if the current instruction stream to be processed includes the instruction group to be optimized, jump to the virtual address segment when the execution reaches the instruction group to be optimized in the current instruction stream to execute the alternative instruction group, and after the alternative instruction group is executed, jump back to the current instruction stream and execute the instructions following the instruction group to be optimized.

13. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is in operation, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of a dynamic instruction replacement method as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the dynamic instruction replacement method as described in any one of claims 1 to 11.

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