Memory controller to mitigate noise and distortion in memory link in transmitter using digital signal processor

Abstract

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives, from a processor, a bitstream including a given symbol to be transmitted on a first channel of a plurality of channels according to pulse-amplitude modulation (PAM), and transmits the given symbol to the first channel of the plurality of channels according to the PAM. A plurality of channels connect the transmitter module to a memory module in an integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk on the first channel from other channels. The parameter is identified based on a pending transition of the signal level in each other channel. The transmitter module superimposes parameters of other channels on a given symbol to adjust the given symbol on the first channel. A digital-to-analog converter (digital-to-analog converter, for short, DAC) on the first channel generates an analog output to the memory module. The analog output represents the adjusted given symbol.

Description

[0001] Cross-referencing

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 702,617, filed October 2, 2024, and U.S. Provisional Application No. 63 / 703,245, filed October 4, 2024, the entire contents of which are incorporated herein by reference. [Technical Field]

[0003] Embodiments of the present invention relate to memory controllers and memory input / output technologies in integrated circuit systems. [Background Technology]

[0004] Modern memory controllers support efficient, low-latency data transfer between processors and storage devices. The memory controller translates and coordinates high-level memory access requests from the processor into low-level electrical signals for reading or writing to memory. Based on the memory access request, the memory controller determines the row and column to access in the memory cell array.

[0005] The storage controller also schedules storage I / O commands from the processor according to timing rules, such as reads, writes, activation (row access), precharge (row close), and flush. Furthermore, the storage controller performs time management and read / write data buffering to manage differences in data rates or timing between the processor and memory.

[0006] Modern high-speed storage I / O requires storage controllers to handle large amounts of data transfer at high frequencies. High data rates can lead to signal integrity issues. Noise, distortion, crosstalk, and inter-symbol interference become significant problems that can corrupt data. A powerful transceiver is needed to maintain signal integrity. Storage controller designs are constantly evolving to support faster, larger, and more energy-efficient computing. The demands on storage controllers in terms of time, power, and reliability continue to grow. Therefore, further improvements to storage controller technology are necessary. [Summary of the Invention]

[0007] In one embodiment, a method is performed by a transmitter module of a memory controller in an integrated circuit system. The method includes the transmitter module receiving from a processor a bitstream containing a given symbol to be transmitted on a first channel of a plurality of channels according to pulse-amplitude modulation (PAM). The plurality of channels connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for eliminating crosstalk between the first channel and the other channels of the plurality of channels. These parameters are identified based on an undetermined transition of the signal level in each of the other channels. The method further includes superimposing the parameters of the other channels onto the given symbol to adjust the given symbol on the first channel; and generating an analog output to the memory module via a digital-to-analog converter (DAC) on the first channel. The analog output represents the adjusted given symbol.

[0008] In another embodiment, the memory controller in the integrated circuit system includes a receiving module for receiving incoming data from the memory module in the integrated circuit system, and a transmitter module comprising multiple transmitter circuits for transmitting outgoing data to the memory module on multiple channels. The transmitter module operates to receive from the processor a bit stream containing a given symbol to be transmitted on multiple signal levels according to pulse amplitude modulation (PAM), and identifies parameters for eliminating crosstalk between the first channel and other channels. These parameters are identified based on an undetermined transition of the signal level in each of the other channels. The transmitter module further operates to superimpose the parameters of the other channels onto the given symbol to adjust the given symbol on the first channel, and generates an analog output to the memory module via a digital-to-analog converter on the first channel. The analog output represents the adjusted given symbol. Other aspects and features will become apparent in the following description of specific embodiments in conjunction with the accompanying drawings. [Attached Image Description]

[0009] The invention is illustrated by way of example and not limitation in the accompanying drawings, wherein like reference numerals denote similar elements. It should be noted that different references to "an" or "an embodiment" in this specification do not necessarily refer to the same embodiment, and these references imply at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is believed that, whether explicitly described in connection with other embodiments, a person skilled in the art would be able to implement that feature, structure, or characteristic.

[0010] Figure 1 This is a block diagram illustrating an operable integrated circuit system according to an embodiment of the present invention.

[0011] Figure 2This is a block diagram illustrating a transmitter module in a storage controller according to one embodiment.

[0012] Figure 3 This is a block diagram illustrating a digital signal processor (DSP) in a transmitter module according to one embodiment.

[0013] Figure 4 This is an illustrative description of one embodiment. Figure 3 A block diagram showing further details of the digital signal processor in the diagram.

[0014] Figure 5 This is an example of a lookup table according to one embodiment.

[0015] Figure 6A This is a diagram illustrating the nonlinear characteristics of a digital-to-analog converter (DAC) according to one embodiment.

[0016] Figure 6B This is a block diagram illustrating a predistortion circuit in a digital signal processor according to one embodiment.

[0017] Figure 7A , Figure 7B , Figure 7C and Figure 7D This illustration shows a storage controller connected to different types of storage modules according to some embodiments.

[0018] Figure 8 This is a flowchart illustrating a method performed by a storage controller according to one embodiment.

Detailed Implementation Methods

[0019] Numerous specific details are provided in the following description. However, it should be understood that embodiments of the invention can be carried out without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to affect the understanding of this description. However, those skilled in the art will understand that the invention can be carried out without these specific details. Those skilled in the art will be able to implement appropriate functions without excessive experimentation based on the included description.

[0020] This disclosure describes transmitter circuitry (“Tx circuit”) in a memory controller that uses a digital signal processor (DSP) to improve the quality of transmitted signals sent to the memory module. In one embodiment, the DSP uses calibration data to adjust the digital signal before it is transmitted to the memory channel. In another embodiment, the DSP pre-distorts the digital signal at the input of a digital-to-analog converter (DAC) to compensate for the DAC's nonlinearity. In one embodiment, the memory controller communicates with the memory module using pulse-amplitude modulation (PAM) with more than two signal levels. The order of pulse-amplitude modulation refers to the number of different signal levels represented by a symbol transmitted using pulse-amplitude modulation. For example, “PAM-N” means using N signal levels to represent a symbol transmitted using pulse-amplitude modulation. Higher-order pulse-amplitude modulation means a larger value of N. Using higher-order pulse-amplitude modulation means transmitting more bits per symbol, thereby increasing throughput without increasing the symbol rate. For the same bit rate, higher-order pulse amplitude modulation allows for a slower symbol rate, thereby reducing inter-symbol interference and crosstalk.

[0021] However, there are trade-offs in increasing the order of pulse amplitude modulation. As the number of signal levels increases, the amplitude difference between each level decreases, resulting in a smaller eye diagram opening. Due to the smaller eye diagram opening, the signal-to-noise ratio (SNR) requirement increases significantly with higher-order pulse amplitude modulation. To improve the SNR of higher-order pulse amplitude modulated signals transmitted from the memory controller, the memory controller performs digital signal processing to enhance signal quality before signal transmission. Specific pulse amplitude modulation orders, such as PAM-4, PAM-8, and PAM-16, are mentioned in the following description. It should be understood that the disclosed memory controllers are not limited to the specific pulse amplitude modulations mentioned herein.

[0022] Figure 1This is a block diagram illustrating an integrated circuit system 100 (“System 100”) in which embodiments of the present invention can be operated. System 100 includes a processor 110 coupled to a memory controller 130. When instructed by the processor 110, the memory controller 130 reads from and writes to a memory module 120. The memory module 120 includes a memory cell array 122 for data storage. In one embodiment, the memory controller 130 may coexist with the processor 110 on a single chip, while the memory module 120 may be located off-chip. In another embodiment, the memory controller 130, the processor 110, and the memory module 120 may all coexist on the same chip.

[0023] Although Figure 1 A processor 110 is shown, but it should be understood that system 100 may include multiple processors, and each processor may include one or more processing cores or computing units. Non-limiting examples of processor 110 include a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a neural processing unit (NPU), and any processing unit that uses a storage controller to access storage module 120.

[0024] Storage controller 130 includes one or more transmitter (Tx) modules 150 and one or more receiver (Rx) modules 170, as well as other components. Transmitter modules 150 and receiver modules 170 communicate with storage module 120 to write to and read from storage cells 122 of storage module 120. In storage I / O interfaces supporting a high number of storage channels (e.g., hundreds or more channels), storage channels can be grouped and routed. Each transmitter module 150 and receiver module 170 is responsible for communication on a set of storage channels. Storage channels within the same group are physically close to each other, thus generating more crosstalk than storage channels in different groups. In the following description, crosstalk cancellation techniques are applied to storage channels within the same group. It should be understood that the same techniques can be applied to storage channels in different groups, but at a higher hardware cost.

[0025] Figure 2This is a block diagram illustrating further details of a transmitter module 150 according to one embodiment. The transmitter module 150 includes a digital signal processor 280 that performs crosstalk cancellation before the signal is transmitted from the storage controller 130. The digital signal processor 280 is coupled to a plurality of (e.g., m) transmitter circuits 250, each transmitter circuit 250 transmitting a signal (Sout) on one of the m storage channels (“channels”). The transmitted signal can carry any information, such as data, commands, addresses, time, etc. Each transmitter circuit 250 transmits a signal at one of the pulse amplitude modulated signal levels in each unit time interval. Each signal level is mapped to a bit group representing a symbol. In one embodiment, each signal level may be mapped to a Gray-coded bit group. For PAM-4, there are 4 signal levels, with each symbol containing 2 bits; for PAM-8, there are 8 signal levels, with each symbol containing 3 bits; for PAM-16, there are 16 signal levels, with each symbol containing 4 bits, and so on.

[0026] Figure 3 This is a block diagram illustrating transmitter module 150 in more detail according to one embodiment. For simplicity, transmitter module 150 supports four storage channels (m=4) as an example. It should be understood that the number of storage channels can be any positive integer not limited to four. Transmitter module 150 receives four signals (S1, S2, S3, S4) from processor 110. Digital signal processor 280 performs crosstalk cancellation on each signal to generate adjusted signals (S1a, S2a, S3a, S4a) respectively, and sends the adjusted signals to the corresponding transmitter circuit 250 for transmission on the corresponding channel. Digital signal processor 280 includes a correction circuit 310 and a data structure, such as one or more lookup tables (e.g., LUT 320). The operation of digital signal processor 280 will be described later. Figure 4 and Figure 5 Describe it.

[0027] In one embodiment, transmitter circuitry 250 includes, among other circuit components, a serializer 350, a digital-to-analog converter (DAC) 352, and an output driver 355. Serializer 350 converts parallel data bits into a serial bit stream with a higher data rate and creates bit groups representing symbols according to a modulation scheme, such as pulse amplitude modulation (PAM) with N signal levels, where N is a positive integer. DAC 352 converts the serialized digital symbols into corresponding analog voltage levels, and output driver 355 drives current representing the analog voltage levels onto the channels. In this example, the output signals from transmitter circuitry are shown as Sout_1, Sout_2, Sout_3, and Sout_4.

[0028] Figure 4 This is a block diagram illustrating further details of a digital signal processor 280 according to one embodiment. In one embodiment, the correction circuit 310 in the digital signal processor 280 includes a crosstalk cancellation circuit 410 for mitigating or eliminating crosstalk on the signal to be transmitted. In a non-limiting example where four signals (S1, S2, S3, S4) are located on four channels respectively, the crosstalk cancellation circuit 410 determines and performs a corresponding correction action for each signal. For clarity of description, the channel affected by crosstalk is referred to as the victim channel, and the channel causing the crosstalk is referred to as the attack channel. In this example, each channel is an attack channel carrying an attack signal that causes crosstalk on the other three signals on the other three channels. Each channel is also a victim channel carrying a victim signal, affected by the other three signals on the other three channels. The correction action may include adjusting the timing and amplitude of each victim signal. The amount of adjustment to a given symbol on the victim channel depends on the pending transition of the signal level of each attack signal. For example, the pending transition of the attack signal is the difference between the previous symbol transmitted on the attack channel and the symbol to be transmitted. The pending symbol can be transmitted approximately simultaneously with the given symbol on the victim channel.

[0029] In one embodiment, the correction action for each victim signal relative to each attack signal is determined during the training phase. During training in the training phase, transmitter circuit 250 (“Tx1”) on the attack channel transmits a signal with a known pattern (e.g., S1) that repeatedly switches between two signal levels of pulse amplitude modulation (e.g., switching between 0000 and 1111 within each unit time interval of PAM-4 transmission), while transmitter circuit 250 (“Tx2”) on the victim channel transmits a signal with a random signal level of PAM-4 (e.g., S2). On the receiving side of the victim channel, the analyzer creates an eye diagram of the received victim signal and measures the reduction in the width and height of each eye opening compared to when S1 is absent. The analyzer further calculates the value of the signal by digital signal processor 280 (…). Figure 2 and Figure 3 The adjustment parameters are used to adjust the timing and amplitude of the victim signal, thereby restoring the eye opening of the victim signal. Training continues, training the victim signal S2 with different signal transition amplitudes (e.g., changes in signal level). For PAM-N (i.e., pulse amplitude modulation with N signal levels), transmitter Tx1 can transmit N different signal transition amplitudes of S1 in N different training processes, while transmitter Tx2 transmits S2 with random signal levels. The result of the N training processes is N sets of adjustment parameters used to adjust the timing and amplitude of S2 when S1 is present. Training is repeated for each attack channel. The generated adjustment parameters are stored in a lookup table 320 of transmitter Tx module 150 for use by digital signal processor 280. Lookup table 320 can be stored in a memory register or other type of fast memory.

[0030] Figure 5 This is an example of a lookup table 320 according to one embodiment. In one embodiment, the lookup table 320 may be organized as a two-dimensional data structure. In a non-limiting example of four signals (S1, S2, S3, S4), the first column of the lookup table 320 includes adjustment data A21, A31, and A41, respectively, for eliminating crosstalk on S1 caused by S2, S3, and S4; the second column includes adjustment data A12, A32, and A42, respectively, for eliminating crosstalk on S2 caused by S1, S3, and S4, and so on. Figure 5The example shows that crosstalk cancellation of the victim signal S2 uses adjustment data A12, A32, and A42 to generate an adjusted digital signal S2a. In one embodiment, each adjustment data includes adjustment parameters indexed by different signal conversion amounts of the attacking signal (e.g., different changes in signal level). In the PAM-N example, A32 includes an array of N sets of adjustment parameters, each set corresponding to a different signal conversion amount of S3. Therefore, for each victim signal transmitted according to PAM-N, the lookup table contains (m-1) x N sets of adjustment parameters for the victim channel to eliminate crosstalk from (m-1) other channels, where m is the total number of crosstalk signals.

[0031] In one embodiment, each set of adjustment parameters includes a time adjustment parameter for advancing or delaying the victim symbol, and an amplitude adjustment parameter for adjusting the digital value representing the victim symbol. The amplitude adjustment parameter may include offset adjustment and / or gain adjustment. Before sending the adjusted digital signal to the digital-to-analog converter 352 and driver 355 to generate an analog output signal, the digital signal processor 280 may further process the adjusted victim symbol (e.g., digital filtering, digital pulse shaping, oversampling, etc.).

[0032] In addition to or as a substitute for crosstalk cancellation, the digital signal processor 280 can perform predistortion operation to compensate for the nonlinearity of the digital-to-analog converter 352. Figure 6A This is a diagram illustrating the nonlinear characteristics of a digital-to-analog converter (DAC) 352 according to one embodiment. The transfer curve of an ideal DAC is a straight line 611 with uniform step sizes. Due to integral nonlinearity (INL) and differential nonlinearity (DNL), the transfer curve of the DAC 352 may be curves 612 or 613. Initialization and training can handle and train some INL, but not all of it. To compensate for the nonlinearity of the DAC 352, the inverse function of the DAC 352's transfer function is calculated and applied to the input signal of the DAC 352. The inverse function is called the digital predistortion (DPD) function. In one embodiment, the digital signal processor 280 performs a digital predistortion operation on the signal to be transmitted before the signal reaches the corresponding DAC 352. The digital predistortion operation is performed channel-by-channel because different DACs may have different transfer functions. When the nonlinear DAC 352 processes the predistorted signal, the predistortion eliminates (or largely eliminates) the nonlinear effects of the DAC 352.

[0033] Figure 6BThis is a block diagram illustrating a predistortion circuit 610 in a digital signal processor 280 according to one embodiment. In one embodiment, the correction circuit 310 includes a predistortion circuit 610 for each channel. The predistortion circuit 610 applies a predistortion value (e.g., a digital value) to the digital signal before it is converted for transmission by the digital-to-analog converter 352, such that the nonlinear combination of predistortion and the digital-to-analog converter 352 becomes substantially linear. For example, the predistortion circuit 610 may retrieve the predistortion value from a lookup table 620 to predistort the signal S2 and generate S2c as the input to the digital-to-analog converter 352. In one embodiment, the lookup table 620 stores a set of predistortion values ​​for the digital-to-analog converter 352 on each channel. Each set of predistortion values ​​includes predistortion values ​​used to predistort a series of digital signal levels at the input of the digital-to-analog converter.

[0034] Figures 7A-7D The diagram illustrates how, according to some embodiments, the storage controller 130 is connected to different types of storage modules. Figure 7A The display memory controller 130 is connected to one or more memory chips 710. The memory chips 710 can be manufactured using any known manufacturing technology and can communicate with the memory controller 130 according to any known memory I / O protocol. For example, the memory chip 710 can be Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Ferroelectric Random Access Memory (FeRAM), Phase Change Memory (PCM), etc. Figure 7B In this configuration, the memory controller 130 communicates with a high-bandwidth memory (HBM) module 720, which includes memory chips arranged in a vertical stack, and is accessed via a TSV 721. The memory controller 130 and the HBM module 720 may coexist on a substrate chip 723, which sits above an interposer and a substrate 725. It should be noted that stacked memory technology is not limited to the HBM module 720. The memory controller 130 described above can operate with memory stacks formed by other memory technologies, such as a low-power dual data rate (LPDDR) memory stack. In one embodiment, the LPDDR memory chips can be vertically stacked via wire bonding, with the bottom LPDDR memory chip connected to a package substrate via wire bonding. Alternatively, the LPDDR memory stack can be packaged in a single package. Figure 7C The display memory controller 130 communicates with a memory chip 730 based on dual data rate (DDR) memory, such as DDR4, DDR5, DDR6, LPDDR, or graphics DDR (GDDR) memory chips. The memory controller 130 and the DDR-based memory chip 730 can coexist on the same package substrate 735. Alternatively, the dual data rate (DDR) based memory chip 730 can be packaged separately from the memory controller 130. Figure 7DThe display memory controller 130 communicates with a dual-line memory module 740 containing multiple memory chips. The memory controller 130 and the dual-line memory module 740 can coexist on the same printed circuit board (PCB) 745. Figures 7A-7D The storage controller 130 in the memory performs the above-described oversampling operation. More specifically, Figures 7A-7D The storage controller 130 in the middle executes method 800 ( Figure 8 ).

[0035] Figure 8 This is a flowchart illustrating method 800 performed by a transmitter module in a memory controller of an integrated circuit system according to one embodiment. (Reference) Figure 2 An example of a transmitter module could be transmitter module 150. Method 800 begins at step 810 when the transmitter module receives a bit stream from a processor containing a given symbol to be transmitted on a first channel of a plurality of channels, modulated according to pulse amplitude. The channels connect the transmitter module to a storage module in an integrated circuit system. The transmitter module (more specifically, a digital signal processor, such as digital signal processor 280, within the transmitter module) identifies parameters for eliminating crosstalk on the first channel from the other channels of the plurality of channels. The parameters are identified based on a pending conversion of the signal level in each of the other channels. The digital signal processor superimposes the parameters from the other channels onto the given symbol to adjust the given symbol on the first channel. The transmitter module then generates an analog output to the storage module via a digital-to-analog converter on the first channel. The analog output represents the adjusted given symbol.

[0036] In one embodiment, the parameters for each other channel include a time adjustment parameter and an amplitude adjustment parameter. In one embodiment, the application parameter may include advancing or delaying a given symbol on a given symbol according to the time adjustment parameter of each other channel. In one embodiment, the overlay parameter may include adjusting the digital value representing a given symbol according to the amplitude adjustment parameter of each other channel. In one embodiment, the pending transition of the signal level is between the previous symbol transmitted on each other channel and the pending symbol to be transmitted.

[0037] In one embodiment, the transmitter module receives corresponding symbols to be transmitted on multiple channels, identifies corresponding undetermined transitions of signal levels in the multiple channels, adjusts the corresponding symbols on the multiple channels according to a lookup table containing crosstalk cancellation parameters, and converts the adjusted corresponding symbols into analog outputs to the storage module via corresponding digital-to-analog converters on the multiple channels. The analog outputs represent the adjusted corresponding symbols. In one embodiment, for a signal with N signal levels transmitted on each channel according to pulse amplitude modulation, the lookup table contains (m-1) x N sets of parameters for each channel to cancel crosstalk from (m-1) other channels.

[0038] In one embodiment, the digital signal processor in the transmitter module identifies a predistortion value from a second lookup table to compensate for nonlinearity of the digital-to-analog converter on the first channel, and adjusts the input of the digital-to-analog converter using the predistortion value to generate an analog output representing an adjusted given symbol. In one embodiment, the predistortion value depends on the signal value of the given symbol. In another embodiment, the digital signal processor superimposes parameters from other channels and the predistortion value onto the given symbol to adjust the given symbol on the first channel.

[0039] Figure 8 The flowchart operation has been referenced Figure 1-5 Exemplary embodiments of 7 and 8 have been described. However, it should be understood that... Figure 8 The operation of the flowchart can be performed by, except Figure 1-5 The embodiments other than 7 are executed, and these embodiments may perform operations different from those discussed in the reference flowchart. Although Figure 8 The flowchart illustrates a specific order of operations performed in some embodiments, but it should be understood that such order is exemplary (e.g., alternative embodiments may perform operations in a different order, combine some operations, overlap some operations, etc.).

[0040] This document describes various functional components or modules. As those skilled in the art will understand, functional modules are preferably implemented by circuits (dedicated or general-purpose circuits that operate under the control of one or more processors and coded instructions), which typically include transistors configured to operate according to the functional and operational control circuitry described herein.

[0041] While the invention has been described through various embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments and that modifications and variations can be made within the spirit and scope of the appended claims. Therefore, the description should be considered illustrative rather than restrictive.

Claims

1. A method for a transmitter module of a memory controller in an integrated circuit system, comprising: The processor receives a bit stream containing a given symbol to be transmitted on a first channel of a plurality of channels according to pulse amplitude modulation (PAM), wherein the plurality of channels connect the transmitter module to a memory module in the integrated circuit system. Identify parameters for eliminating crosstalk between the first channel and the other channels of the plurality of channels, wherein the parameters are identified based on the undetermined transition of the signal level in each of the other channels; The parameters of the other channels are superimposed on the given symbol to adjust the given symbol on the first channel; and An analog output is generated to the storage module via a digital-to-analog converter (DAC) on the first channel, which represents the adjusted given symbol.

2. The method of claim 1, wherein the parameters of each other channel include time adjustment parameters and amplitude adjustment parameters.

3. The method of claim 1, wherein applying the parameter further comprises: The time adjustment parameter of each other channel advances or delays the given symbol on that given symbol.

4. The method of claim 1, wherein adding the parameter further comprises: The numerical value representing the given symbol is adjusted on the given symbol based on the amplitude adjustment parameters of each of the other channels.

5. The method of claim 1, wherein the pending transition of the signal level is between a previous symbol transmitted on each other channel and a pending symbol to be transmitted.

6. The method of claim 1, further comprising: The transmitter module receives the corresponding symbols to be transmitted on the multiple channels; Identify the corresponding pending transitions of signal levels in these multiple channels; Adjust the corresponding symbols on these multiple channels according to a lookup table containing crosstalk cancellation parameters; as well as The adjusted symbol is converted into an analog output to the storage module by the corresponding digital-to-analog converter on the multiple channels. The analog output represents the adjusted symbol.

7. The method of claim 6, wherein, For signals transmitted according to the N signal level on each channel, the lookup table contains (m-1) x N sets of parameters to eliminate crosstalk from (m-1) other channels.

8. The method of claim 1, further comprising: Identify the predistortion value used to compensate for the nonlinearity of the digital-to-analog converter on the first channel from the second lookup table; as well as The input of the digital-to-analog converter is adjusted by the predistortion value to generate the analog output representing the adjusted given symbol.

9. The method of claim 8, wherein the predistortion value depends on the signal value of the given symbol.

10. The method of claim 8, further comprising: The parameters of the other channels and the predistortion value are superimposed on the given symbol to adjust the given symbol on the first channel.

11. A memory controller in an integrated circuit system, including: A receiving module for receiving incoming data from the storage module of the integrated circuit system; as well as A transmitter module, comprising multiple transmitter circuits, is used to transmit data to and from the storage module on multiple channels, wherein the transmitter module operates as follows: Receive from the processor a bit stream containing a given symbol to be transmitted on the first channel of a multi-channel array according to pulse amplitude modulation (PAM); Identify parameters for eliminating crosstalk between the first channel and the other channels of the plurality of channels, wherein the parameters are identified based on the undetermined transition of the signal level in each of the other channels; The parameters of the other channels are superimposed on the given symbol to adjust the given symbol on the first channel; and An analog output is generated to the storage module via a digital-to-analog converter (DAC) on the first channel, which represents the adjusted given symbol.

12. The storage controller of claim 11, wherein the parameters of each other channel include time adjustment parameters and amplitude adjustment parameters.

13. The storage controller of claim 11, wherein, when the parameter is applied, the transmitter module further operates to: The time adjustment parameter of each other channel advances or delays the given symbol on that given symbol.

14. The memory controller as claimed in claim 11, wherein, When the 91 parameter is added, the 92transmitter module can also: Adjust the numerical value representing the given symbol 93 according to the 94 amplitude adjustment parameter for each of the other channels.

15. The memory controller as claimed in claim 11, wherein, The 98 pending transition in the signal level occurs between the previously transmitted symbol and the symbol to be transmitted, which is located on each of the other channels.

16. The memory controller as claimed in claim 11, wherein, The 101 transmitter module can also: Receive the corresponding symbols that will be transmitted on more than 102 channels; Identify the corresponding undetermined transitions of signal levels in more than 103 channels; Adjust the 104 corresponding symbols on more than 105 channels according to a lookup table containing crosstalk cancellation parameters; and The corresponding symbols adjusted by 106 are converted into analog outputs of 107 memory modules by corresponding digital-to-analog converters on multiple channels, and the analog outputs of 109 represent the corresponding symbols adjusted by 110.

17. The memory controller as claimed in claim 16, wherein, For a signal with N signal levels transmitted on each channel according to pulse amplitude modulation, the 112 lookup table contains (m-1) x N sets of parameters for channel 113 to eliminate crosstalk from (m-1) other channels.

18. The memory controller as claimed in claim 11, wherein, The 115 transmitter module can also: Identify the predistortion value used to compensate for the nonlinearity of the 116 digital-to-analog converter from the second lookup table; and The input of the digital-to-analog converter 118 is adjusted by the predistortion value 119 to generate the analog output of the storage module 120 representing the adjusted given symbol 121.

19. The memory controller as claimed in claim 18, wherein, The 123 predistortion value depends on the signal value of the given symbol in 124.

20. The memory controller as claimed in claim 18, wherein, The 126 transmitter module can also: The parameters of the other channels 127 and the predistortion value 129 are superimposed on the given symbol of the storage controller 130 to adjust the given symbol 131 on the first channel 132.

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