FPGA (Field Programmable Gate Array)-based address mapping DMA (Direct Memory Access) engine hardware system and implementation method thereof

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based address mapping DMA (Direct Memory Access) engine hardware system and an implementation method thereof. According to the system, an address mapping table is constructed through a dual-port RAM, and multi-interval virtual-to-physical address conversion is supported; an engine extracts an FPGA side request address, and generates a host physical address through an FPGA address offset reduction and base address addition algorithm after matching a mapping entry; a multi-level cache mechanism is adopted, a read-write path is coordinated through a request distribution module and a response distribution module, and a data sequence is ensured in combination with recombination information cache; the method comprises the steps of request analysis, address conversion and recombination, data recombination, request execution, response processing, read data recombination and response return. According to the method, the data transmission efficiency among heterogeneous systems is remarkably improved, and delay is reduced.

Description

Technical Field

[0001] This invention belongs to the field of data transmission and hardware acceleration technology, and in particular relates to an FPGA-based address mapping DMA engine hardware system and its implementation method. Background Technology

[0002] In modern high-performance computing and embedded systems, FPGAs are widely used for specific processing acceleration tasks due to their reconfigurability and parallel processing capabilities. To achieve efficient data interaction between the FPGA and host-side memory, DMA (Direct Memory Access) technology is typically used to reduce the CPU processing load and improve data throughput.

[0003] Traditional DMA engines often rely on the underlying DMA driver to provide the host-side memory address and length information to be accessed. Multiple DMA transfers require the software driver to provide memory address and length information multiple times. This not only increases the application programming complexity of FPGA and CPU but also reduces DMA access latency and bandwidth. At the same time, traditional DMA engines do not implement read / write channel separation and decoupling of requested data, which can easily cause data congestion and resource contention, affecting the system's concurrent performance. In addition, most typical DMA architectures access host memory through standard buses such as AXI, but when faced with narrow bit widths and continuous data streams on the FPGA side, there are problems such as bus wait, bit width mismatch, address misalignment, and lack of flexible address mapping mechanisms. Summary of the Invention

[0004] The purpose of this invention is to provide an address-mapped DMA engine hardware system based on FPGA and its implementation method, which solves the technical problems of low DMA efficiency caused by multiple DMA transfers of data address and length information, unified read and write channels, request data coupling, mismatch between data bit width on the FPGA side and the CPU side, and address misalignment.

[0005] To achieve the objectives of this invention, in one aspect, this invention provides an FPGA-based address mapping DMA engine hardware system, comprising the following modules:

[0006] The register module is used to initialize and control the modules of the system through the register access interface;

[0007] The FPGA-side request distribution module is used to obtain read requests, write requests, and write data from the request packet header of the interface through the FPGA-side streaming data.

[0008] The address mapping lookup module is used to obtain address mapping information in the address mapping table within the address mapping lookup module through a lookup algorithm;

[0009] The read / write request reassembly module is used to reassemble read / write requests to obtain read / write requests on the host side.

[0010] The write data reassembly module is used to reassemble the write data on the FPGA side using write data reassembly information to obtain write data that meets the requirements of the host side memory data interface.

[0011] The host read / write request generation module is used to send out read requests, write data, and write data through the host-side memory data read / write request interface;

[0012] The host-side response distribution module is used to obtain the response information of the corresponding request through the host-side memory data read and write response interface;

[0013] The read data reconstruction module is used to reconstruct the host-side read data using read data reconstruction information to obtain read data that meets the requirements of the FPGA-side streaming data interface.

[0014] The FPGA-side response generation module sends out the response header and read data through the FPGA-side streaming data master interface.

[0015] On the other hand, the present invention also provides a method for implementing the above-described FPGA-based address mapping DMA engine hardware system, comprising the following steps:

[0016] Step 1: Parse the FPGA-side streaming data through the FPGA-side request distribution module to obtain read / write requests and write data. The read / write requests are written to the corresponding FPGA-side read / write request caches, and the write data is written to the FPGA-side write data cache. At the same time, the response information corresponding to the request is written to the FPGA-side response information cache.

[0017] Step 2: The read / write request is used to find the corresponding address mapping information in the address mapping table through the address lookup module. Combined with the alignment rules of the host-side memory request, the read / write request is reassembled to obtain the host read / write request and read / write reassembly information, and written into the host-side read / write request cache and read / write reassembly information cache.

[0018] Step 3: Read the FPGA write data from the FPGA write data cache, reassemble the data according to the write data reassembly information through the write data reassembly module, and write it into the host write data cache;

[0019] Step 4: The host-side read / write request generation module reads from the host-side read / write request cache and sends the request out through the host-side memory data read / write request interface. If it is a write request, it continues to read the write data from the host-side write data cache and sends the write data out through the above interface.

[0020] Step 5: The host-side response distribution module receives the response from the host-side memory data read / write response interface, writes the response value into the host-side response value cache, and if the response is a read response, stores the subsequent read data into the host-side read data cache.

[0021] Step 6: Read the host-side read data from the host-side read data cache, reassemble the data according to the read data reassembly information through the read data reassembly module, and write it into the FPGA-side read data cache;

[0022] Step 7: The FPGA-side response generation module reads the FPGA-side response information from the corresponding cache and combines it with the host-side response value to generate an FPGA-side response, which is then sent out through the FPGA-side streaming data interface. If the response is a read response, the module continues to read read data from the FPGA-side read data cache and sends the read data out through the aforementioned interface.

[0023] Compared with existing technologies, the significant advancements of this invention are as follows: By introducing an address mapping table on the FPGA side, the FPGA-side data address can be dynamically converted to the host-side memory address, realizing a memory-mapped access method. This reduces DMA operation latency while improving programming flexibility and reducing FPGA logic complexity. Combined with a read / write channel separation design, channel conflicts and resource contention are effectively avoided, improving concurrent processing capabilities and system stability. The pipelined design for request and data processing improves the efficiency of the host-side memory data interface bus. A data reassembly module completes the bit-width conversion and address alignment between the FPGA-side data interface and the host-side memory data interface, resolving the compatibility issue between FPGA narrowband streaming data and host wideband memory interfaces. The overall solution significantly improves DMA transfer efficiency and throughput, reduces application programming complexity, and thus enhances the efficiency of the entire information system.

[0024] To more clearly illustrate the functional characteristics and structural parameters of the present invention, further explanation is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0026] Figure 1 This is a schematic diagram showing the connection between the address mapping table and the address lookup module of the present invention;

[0027] Figure 2 This is a schematic diagram of the read / write request processing pipeline of the present invention;

[0028] Figure 3This is a schematic diagram of the read / write data processing pipeline of the present invention;

[0029] Figure 4 This is an architectural diagram of Embodiment 1 of the present invention;

[0030] Figure 5 This is a flowchart of the reorganization request process of this invention;

[0031] Figure 6 This is a flowchart of the data reorganization process of the present invention. Detailed Implementation

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] This invention provides an FPGA-based address-mapped DMA engine hardware system, combined with... Figures 1-3 It includes the following modules:

[0034] The register module is used to initialize and control the modules of the system through the register access interface;

[0035] The FPGA-side request distribution module is used to obtain read requests, write requests, and write data from the request packet header of the interface through the FPGA-side streaming data.

[0036] The address mapping lookup module is used to obtain address mapping information in the address mapping table within the address mapping lookup module through a lookup algorithm;

[0037] The read / write request reassembly module is used to reassemble read / write requests to obtain read / write requests on the host side.

[0038] The write data reassembly module is used to reassemble the write data on the FPGA side through write data reassembly information to obtain write data that meets the requirements of the host side memory data interface.

[0039] The host read / write request generation module is used to send read requests, write data, and write data through the host-side memory data read / write request interface;

[0040] The host-side response distribution module is used to obtain the response information of the corresponding request through the host-side memory data read / write sound zone interface;

[0041] The read data reconstruction module is used to reconstruct the host-side read data using read data reconstruction information to obtain read data that meets the requirements of the FPGA-side streaming data interface.

[0042] The FPGA-side response generation module sends out the response header and read data through the FPGA-side streaming data master interface.

[0043] The address mapping table is used to establish the correspondence between FPGA-side data addresses and host-side memory addresses. It consists of dual-port RAM, supports simultaneous read and write access, and ensures low-latency queries at high frequencies. The mapping entries include source address segments, target address segments, and their mapping range sizes, allowing users to configure multiple virtual-to-physical address mapping intervals. When the FPGA initiates a data access request, the engine first searches the mapping table through the address lookup engine to determine whether the request falls within the valid mapping area and obtains the corresponding host physical address starting point, thus completing the address translation process.

[0044] The data reconstruction module performs dynamic data splicing or splitting operations based on the bit width difference between the FPGA-side streaming interface and the host-side memory interface; multiple narrow bit-width streaming data packets are combined into a wide bit-width AXI burst write data block; the read data reconstruction module decomposes the wide bit-width data into narrow bit-width data streams suitable for FPGA processing in sequence.

[0045] The data reconstruction module takes as input a data stream in Axi-Stream format from the FPGA side and control parameters output from the reconstruction information buffer, and outputs data organized in a manner adapted to the host-side memory interface. Internally, this module includes byte alignment logic, a data splicing / splitting unit, a burst length manager, and boundary detection circuitry. It adjusts the effective starting point of the input data based on the initial byte order offset of the source data to ensure that the payload is acquired from the correct byte position. Subsequently, based on the difference in burst counts between the source and destination sides, it dynamically merges or splits the input data blocks to match the burst transmission requirements of the target interface.

[0046] The host-side memory data interface adopts the AXI interface, which supports interconnection with AXI bus peripherals, thereby enabling the FPGA to exchange data with any bus peripheral through streaming data.

[0047] The address mapping lookup module receives an address request signal from the FPGA-side streaming data interface and extracts the data address field. Then, it compares the address with the FPGA-side starting address and mapping size of each entry in the address mapping information table to determine whether the address falls within any valid mapping range. If a match is found, the corresponding host-side memory address is output, the original FPGA address is subtracted from the local mapping start offset, and the host-side base address is added to complete the address conversion. If no match is found, an address error exception is triggered or the default processing path is returned.

[0048] The host-side memory data read / write request interface is located at the front end of the host bus interface and is used to cache data transactions to be sent or just received. In the write direction, it temporarily stores reorganized data blocks and waits for the host-side write request to be approved before submitting them in batches. In the read direction, it is used to receive response data from the host and collect and sort it according to the request ID to ensure that the data returned to the FPGA side is in the correct order.

[0049] A method for implementing the above-described FPGA-based address mapping DMA engine hardware system according to the present invention includes the following steps:

[0050] Step 1: Parse the FPGA-side streaming data through the FPGA-side request distribution module to obtain read / write requests and write data. The read / write requests are written to the corresponding FPGA-side read / write request caches, and the write data is written to the FPGA-side write data cache. At the same time, the response information corresponding to the request is written to the FPGA-side response information cache.

[0051] Step 2: The read / write request is used to find the corresponding address mapping information in the address mapping table through the address lookup module. Combined with the alignment rules of the host-side memory request, the read / write request is reassembled to obtain the host read / write request and read / write reassembly information, and written into the host-side read / write request cache and read / write reassembly information cache.

[0052] Step 3: Read the FPGA write data from the FPGA write data cache, reassemble the data according to the write data reassembly information through the write data reassembly module, and write it into the host write data cache;

[0053] Step 4: The host-side read / write request generation module reads from the host-side read / write request cache and sends the request out through the host-side memory data read / write request interface. If it is a write request, it continues to read the write data from the host-side write data cache and sends the write data out through the above interface.

[0054] Step 5: The host-side response distribution module receives the response from the host-side memory data read / write response interface, writes the response value into the host-side response value cache, and if the response is a read response, stores the subsequent read data into the host-side read data cache.

[0055] Step 6: Read the host-side read data from the host-side read data cache, reassemble the data according to the read data reassembly information through the read data reassembly module, and write it into the FPGA-side read data cache;

[0056] Step 7: The FPGA-side response generation module reads the FPGA-side response information from the corresponding cache and combines it with the host-side response value to generate an FPGA-side response, which is then sent out through the FPGA-side streaming data interface. If the response is a read response, the module continues to read read data from the FPGA-side read data cache and sends the read data out through the aforementioned interface.

[0057] Example 1

[0058] like Figure 4 As shown, this embodiment constructs an integrated DMA engine hardware structure, enabling the FPGA to access host-side physical memory via address mapping, thereby simplifying the programming model and improving data interaction efficiency. The entire DMA engine is deployed inside the FPGA, acting as a bridge connecting the FPGA logic units and the external host memory system. Its core functions include: implementing dynamic mapping from the FPGA local address space to the host physical address space; coordinating data paths of different bit widths; adapting to access constraints of host memory bus protocols (such as AXI4); and improving throughput and response speed through structured pipeline design.

[0059] The DMA engine incorporates an address mapping table to establish the correspondence between FPGA-side data addresses and host-side memory addresses. This mapping table, comprised of dual-port RAM, supports simultaneous read and write access, ensuring low-latency lookups at high frequencies. Mapping entries include a source address range (FPGA side), a target address range (host side), and their mapping range size, allowing users to configure multiple virtual-to-physical address mapping intervals. When the FPGA initiates a data access request, the engine first searches the mapping table using the address lookup engine to determine if the request falls within a valid mapping area and obtains the corresponding host physical address starting point, completing the address translation process.

[0060] This DMA engine employs a "read-write channel separation" architecture, meaning that read and write operation paths are completely independent. The read channel is responsible for reading data from host memory and returning it to the FPGA side, while the write channel is responsible for writing data from the FPGA side to a designated host memory area. This separation design avoids contention for shared resources between read and write operations, improves concurrent processing capabilities, and is particularly suitable for high-bandwidth applications.

[0061] Furthermore, the engine incorporates a "request and data separation" design philosophy, where control information (such as address, length, and type) is decoupled from the actual payload data during transmission, either in time or via a specific channel. This design conforms to the specifications of modern high-speed bus protocols (such as the Advanced Dextensible Interface, AXI) that separate control and data channels, enhancing system stability and scalability.

[0062] Furthermore, to address the compatibility issue between narrowband streaming data on the FPGA side and wideband memory interfaces on the host side, this embodiment includes a data reassembly module. This module performs dynamic data splicing or splitting operations based on the bit width difference between the FPGA-side streaming interface (e.g., AXI-Stream) and the host-side memory interface (e.g., AXI4 Write Data Channel). For example, in a write operation, multiple narrow-bit-width streaming data packets may be combined into a wide-bit-width AXI burst write data body; in a read operation, the wide data needs to be sequentially decomposed into narrow data streams suitable for FPGA processing. Simultaneously, this module supports address alignment processing, particularly for the common 4K boundary alignment requirements of host memory controllers, automatically adjusting the burst start position and inserting padding or truncating redundant portions to meet transmission specifications.

[0063] The above modules work together to form a complete address-mapped DMA solution. The address mapping mechanism gives FPGA CPU-like memory access capabilities, the data reassembly module eliminates obstacles caused by heterogeneous interfaces, and the read / write separation and request / data separation architecture ensures high performance and high stability. In practical implementation:

[0064] Step 1: The FPGA-side request distribution module receives streaming data from the FPGA side.

[0065] Among them, "FPGA sidestream data" refers to a continuous, beat-transmitted data stream generated by the internal logic of the FPGA. The typical interface is AXI-Stream (Advanced eXtensible Interface-Stream), which is characterized by the absence of fixed address lines, the reliance on packet headers to carry control information, and support for backpressure mechanisms to prevent overflow.

[0066] In an optional embodiment, the FPGA-side streaming data can be replaced with other interface protocols that support flow control, such as LocalLink, User-Defined Stream Protocol, or a custom protocol based on the Valid-Ready handshake mechanism. As long as it has basic flow control and data packaging capabilities, it can be adapted to this solution.

[0067] The FPGA request distribution module parses the packet header to obtain information such as the request type, address, and length. It then separates read and write requests and writes them to the corresponding FPGA-side read / write request caches, while also writing the response information to the FPGA-side response cache. If the request is determined to be a write request, all data except the packet header is written to the FPGA-side write data cache. This achieves separation of read and write requests.

[0068] Step 2: Address mapping table lookup and address conversion.

[0069] This embodiment includes a register module whose external interface is via AXI-Lite, Avalon, or other bus interfaces. Both the host side and the FPGA side can access the internal registers through this bus interface. Internally, the register module mainly provides control signals such as enable and reset, and most importantly, it initializes and updates the address mapping table.

[0070] The address mapping table is a lookup table structure that stores address mapping relationships. It is implemented using dual-port static random access memory (DRAM) and supports read and write operations within the same clock cycle, making it suitable for the high-frequency operating scenario in this embodiment. Each mapping entry in this embodiment contains three key fields: FPGA-side start address, host-side physical start address, and mapping region size. The address mapping relationship is linear. When the request reassembly module initiates an access request for a local address A_fpga, the address lookup module sequentially traverses the table, determining whether A_fpga falls within any mapping interval (i.e., satisfying A_fpga ∈ [Base_fpga, Base_fpga + Size)). If so, the corresponding host memory address A_host = Base_host + (A_fpga - Base_fpga) is calculated, completing the address translation.

[0071] The address mapping mechanism allows FPGA developers to access remote memory without needing to worry about the actual layout of the host memory; they can simply use a preset local address space, greatly simplifying the hardware-software collaborative development process. The mapping table content can be dynamically loaded through host-side configuration interfaces (such as the PCIe BAR register) and supports runtime updates.

[0072] In an optional embodiment, the address mapping table can be replaced by a single-port RAM with time-division multiplexing control logic; the search algorithm can be sequential traversal, hash index, or a fast matching structure based on a Trie tree, depending on the trade-off between performance and resource overhead.

[0073] Step 3: Request processing flow.

[0074] Request pipeline processing is completed by the FPGA-side read / write request cache, the read / write request reassembly module, and the host-side read / write request cache.

[0075] The request processing pipeline primarily handles the merging or splitting of requests on the FPGA side. Request merging mainly combines two or more requests with consecutive address values ​​into a single request; request splitting specifically refers to whether the host memory addresses of the requests meet certain alignment requirements (such as 4KB page boundary alignment). If not aligned, the data reassembly module will split the original request into multiple sub-requests: the first request handles the unaligned header, the middle requests handle the aligned body, and the last request handles the tail remnants. This strategy ensures that each sub-request complies with the host memory controller's secure access rules, preventing abnormal interruptions.

[0076] In an optional embodiment, the address alignment granularity can be adjusted according to the actual platform requirements, supporting 2KB, 1KB, or other boundary alignment modes.

[0077] like Figure 5 As shown, the specific water treatment process is as follows:

[0078] (1) When the read / write request cache on the FPFA side is not empty, the read / write request reassembly module reads the new request from the read / write request processing cache on the FPGA side and submits it to the address lookup module for address translation;

[0079] (2) After the read / write request reassembly module obtains the host-side address, it determines whether it is continuous with the previous write request. If it is continuous, the two requests are reassembled into a new write request.

[0080] (3) Repeat (1) and (2) until the new request is not continuous with the previous write request, or there is no new write request, or the new write request crosses the host-side address boundary limit such as the 4K boundary. Then write the write request to the host-side read / write request cache, and extract data reassembly information such as the data start byte order offset on both sides and the burst number, as well as write response related information, and write them together to the read / write data reassembly information cache and the response information cache, and return to (1).

[0081] Step 4: Data processing pipeline.

[0082] The data processing pipeline consists of a source data cache, a data reassembly information cache, a data reassembly module, and a destination data cache. The data reassembly information cache temporarily stores context information for the current transmission transaction, including: source data start byte offset, destination data start byte offset, burst count, and transmission direction. This information comes from the read / write request reassembly module. Based on the above information and the protocol specifications of the host-side memory interface (such as AXI), the data reassembly module performs specific data rearrangement operations. Here, for write requests, the source is the FPGA side and the destination is the host side; for read requests, the opposite is true.

[0083] For example, in a write operation, if the FPGA sends data in 32-bit increments, while the host requires a 512-bit aligned burst write, the reassembly module needs to accumulate 16 FPGA data cycles and reorganize them into a complete 512-bit AXI write burst. If the starting address is not aligned, it needs to pad the leading empty bytes or process the parts at the beginning and end that are not full bursts separately. Similarly, in a read operation, the reassembly module needs to decompose the wide-bit-width data read back according to the format required by the FPGA and compensate for byte misalignment caused by address offset.

[0084] This module supports various reassembly strategies, including but not limited to: data concatenation, data segmentation, byte reordering, padding, and truncation. All operations are performed in a hardware pipeline with controllable latency.

[0085] In an optional embodiment, the data reconstruction module can integrate ECC encoding / decoding functions to simultaneously complete error correction and protection during the reconstruction process; it can also support transparent reconstruction of compressed data streams, provided that the data lengths before and after compression are known and predictable.

[0086] like Figure 6 As shown, the specific water treatment process is as follows:

[0087] (1) When the write data reorganization information cache is not empty, the write data reorganization module reads the reorganization information from the write data reorganization information cache;

[0088] (2) When the depth of the source data cache is greater than the source burst number required in the data reassembly information, and the depth of the free data in the destination data cache is greater than or equal to the destination burst number required in the data reassembly information, the data reassembly module reassembles the written data according to the byte order information on both sides and writes it into the host side write data cache.

[0089] (3) Repeat (1) and (2)

[0090] Step 5: Response processing and generation.

[0091] Requests and responses are associated through a transaction ID to ensure an accurate match between them.

[0092] (1) When the FPGA-side request distribution module receives a request from the FPGA side, it will write the transaction identifier and other information of the request into the response information cache;

[0093] (2) When the host-side memory data interface receives a write response value, the host-side response distribution module writes the response value into the response value cache. When a read response value is received, the read response value is written into the response value cache, and the subsequent read data is written into the host-side read data cache.

[0094] (3) The FPGA-side response generation module reads the response information with the transaction identifier from the response information cache and reads the corresponding response value from the response value cache, forms a response packet header and sends it to the FPGA-side streaming data main interface. If the response is a read response, the FPGA-side read data is sent to the FPGA-side streaming data main interface.

[0095] Through the above-described steps, this application achieves efficient and reliable interaction between FPGA-side streaming data and host-side memory. Due to the use of an address mapping table mechanism, the FPGA can access complex host physical memory using a simplified local address space, improving the system abstraction level and development convenience. The data reassembly module resolves the bit width and alignment contradictions between the FPGA's narrowband streaming interface and the host's wideband memory interface, avoiding data misalignment or transmission failures. The implementation of read / write channel separation and request / data separation significantly improves the DMA engine's concurrent processing capabilities and protocol compatibility, meeting the needs of modern high-performance interconnect architectures. In summary, this application achieves high throughput, low latency, and high reliability data transmission without relying on CPU intervention, effectively solving the problems of low data interaction efficiency and difficult interface adaptation in the background technology.

[0096] Example 2

[0097] Based on the above embodiments, this embodiment further provides:

[0098] The host-side memory data interface uses an AXI interface or other bus interface, supporting interconnection with AXI bus or other bus peripherals, thereby enabling the FPGA's streaming data to interact with any bus peripheral.

[0099] The host-side memory data interface serves as a crucial data exchange path between the DMA engine and the host system, and its physical and protocol layer design must be compatible with mainstream on-chip bus standards. This interface can be configured as the AXI (Advanced deXtensible Interface) protocol or adapted to other general-purpose bus interfaces, such as AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus), CHI (Coherent Hub Interface), Avalon-MM (Avalon Memory-Mapped Interface), or custom flow control buses. The AXI interface is widely used in modern SoC (System-on-Chip) architectures due to its high bandwidth, low latency, support for concurrent read / write operations, and address / data separation; while other bus interfaces are suitable for applications with varying requirements for power consumption, area, or functional complexity.

[0100] The configurability of this interface is achieved through a modular hardware design, such as using parameterized logic blocks or reconfigurable interface bridge structures, allowing the same DMA engine IP core to flexibly select and instantiate the corresponding bus adapter module according to the target platform. When configured as an AXI4 or AXI4-Lite interface, it supports functions such as burst transfer, unaligned access processing, and QoS priority control, and can be connected to a multi-level interconnect network through the AXIinterconnect component, thereby directly communicating with various peripherals mounted on the AXI bus (such as GPUs, NPUs, high-speed network cards, and storage controllers).

[0101] When using other bus interfaces, the internally unified data format can be converted into the signal timing and timing constraints specified by the target bus through the bridging module. For example, when connecting to AHB peripherals, read and write requests are received through the AHB slave interface module, and the data is encapsulated into a single or continuous transmission mode that conforms to the AHB transmission protocol; when connecting to low-speed APB devices, clock domain conversion and handshake process matching are completed through synchronous or asynchronous bridging mechanisms.

[0102] Through the above steps, this application achieves multi-bus compatibility of the DMA engine host-side interface. Supporting AXI and other bus interfaces, FPGA-side streaming data can not only efficiently access host main memory but also be forwarded to different types of functional peripherals via the DMA engine without additional CPU intervention or intermediate buffering. Therefore, it solves the problems of difficult system integration and poor scalability caused by the strong interface specificity in traditional DMA designs, improves the reusability of hardware modules and cross-platform portability, and enhances the interconnect flexibility and functional expansion space of the entire system.

[0103] Example 3

[0104] Based on the above embodiments, this embodiment further provides:

[0105] The FPGA-side streaming data interface is divided into two interfaces: a master interface for receiving FPGA-side requests and a master interface for sending FPGA-side responses.

[0106] The FPGA-side streaming data interface is a key path for achieving efficient communication between FPGA logic units and the DMA engine. This interface is divided into a slave interface and a master interface, which respectively handle the functions of request input and response output.

[0107] The slave interface serves as an input channel to receive data access requests initiated by internal logic modules within the FPGA. These requests typically include control information such as the address, length, and identifier for read or write operations. The slave interface receives request data packets using flow control, sampling and buffering the request signals while ensuring handshake protocols (such as valid / ready) are met, thus guaranteeing the integrity and timing stability of the request transmission. This interface is compatible with various streaming standards, such as AXI-Stream or other data streaming protocols that support backpressure, thereby ensuring compatibility with data interaction requirements across different FPGA design architectures.

[0108] Optionally, the interface can select different bit widths (such as 32-bit, 64-bit, 128-bit) through configuration registers to match the data output capabilities of the upstream logic modules; it can also integrate an elastic buffer structure to alleviate congestion problems caused by cross-clock domains or burst traffic.

[0109] The main interface serves as the output channel, transmitting the response information generated by the DMA engine after processing back to the FPGA-side logic units. The response content includes, but is not limited to, read data return, transaction completion status, and error flags. The main interface also follows the flow control protocol for data push, driving downstream logic to receive response data via a valid signal upon readiness. By setting independent response paths, contention and latency accumulation caused by request-response interleaving in a single channel are avoided.

[0110] In one optional implementation, the main interface supports a multiplexing mechanism, which can sort and return responses to multiple concurrent requests in an ordered manner according to transaction ID, improving the overall system response consistency and predictability. Furthermore, the main interface can also integrate CRC check functionality to enhance the reliability of data return.

[0111] The aforementioned slave and master interfaces are physically isolated from each other, forming a dual-channel communication architecture. This separate design ensures that request sending and response returning each have independent bandwidth resources and timing paths, significantly reducing the risk of bus contention and improving the system's throughput and real-time response performance. Especially in high-concurrency data transmission scenarios (such as video stream processing and high-speed acquisition systems), this structure can effectively prevent pipeline blockage caused by response lag and ensure stable collaboration between the DMA engine and FPGA logic.

[0112] Through the above scheme, this application realizes the master-slave separation architecture of the FPGA side-stream data interface: since the request is input unidirectionally through the slave interface and the response is output unidirectionally through the master interface, the problems of response delay, timing conflict and low backpressure propagation efficiency in the traditional shared channel are solved, thus improving the decoupling degree of the control flow and data flow inside the FPGA and enhancing the modularity and scalability of the system.

[0113] Example 4

[0114] Based on the above embodiments, this embodiment further provides:

[0115] The address mapping table includes an address mapping information table consisting of a dual-port RAM (which includes the starting mapping addresses and mapping size on both sides) and an address lookup engine module.

[0116] The address mapping information table is implemented using dual-port RAM to store the mapping relationship between FPGA-side data addresses and host-side memory addresses. Key parameters recorded in this mapping information table include at least: the FPGA-side starting address, the corresponding host-side physical memory starting address, and the size of the mapped region. The dual-port RAM allows two independent access ports to perform read and write operations simultaneously. One port can be dynamically written to or updated by an external control unit (such as the CPU or configuration logic) during system initialization or runtime; the other port is used by the DMA engine for real-time querying during data transfer. This structural design allows for flexible adjustment of the address mapping relationship without interrupting DMA operations, making it suitable for multi-tasking, dynamic memory allocation applications.

[0117] The address lookup engine module is responsible for retrieving a matching valid mapping range from the address mapping information table based on the input FPGA-side data address. Its operation is as follows: it receives an address request signal from the FPGA-side streaming data interface and extracts the data address field; then, it compares this address with the FPGA-side starting address and mapping size of each entry in the address mapping information table to determine if the address falls within any valid mapping range. If a match is found, the corresponding host-side memory address is output, which is the original FPGA address minus the local mapping start offset and plus the host-side base address, completing the address translation; if no match is found, an address error exception is triggered or the default processing path is returned.

[0118] The address lookup engine module supports various lookup algorithm implementations, such as sequential traversal, suitable for scenarios with few mapping entries and low latency requirements; binary search, suitable for large mapping tables requiring fast location, in which case the mapping entries must be arranged in address order; and hash lookup mechanisms or content-based addressing hardware acceleration structures can be integrated to further improve lookup efficiency. These implementations can be selected and replaced according to actual application needs without affecting the technical essence of this application.

[0119] Through the above steps, this application achieves efficient and reconfigurable mapping management of FPGA-side addresses to host-side memory addresses. The use of a dual-port RAM structure allows the address mapping table to support both static configuration and dynamic updates, enhancing the system's flexibility and adaptability. A dedicated address lookup engine module ensures the real-time and deterministic nature of address translation, meeting the low-latency response requirements of high-speed DMA data transfer. This solution is particularly suitable for heterogeneous computing architectures where embedded FPGAs and host processors share memory resources, completing hardware-level address translation without software intervention, simplifying the system programming model and improving overall data throughput performance.

[0120] Example 5

[0121] Based on the above embodiments, this embodiment further provides:

[0122] The address lookup module can be implemented using algorithms such as traversal and binary search.

[0123] The address lookup module is used to find the corresponding host-side memory address based on the data address input from the FPGA side in the address mapping information table composed of dual-port RAM. This lookup process needs to support multiple lookup strategies to adapt to application scenarios with different scales and performance requirements.

[0124] Firstly, regarding the technical feature of the "address lookup engine module," its function is to quickly locate the host-side memory address entry that matches the FPGA-side data address from the address mapping information table during address mapping by the DMA engine. As the core processing unit of the address mapping mechanism, this module is responsible for parsing the input address, executing the lookup logic, and outputting the corresponding mapping results, including the starting address offset of the target memory region and the effective mapping range. To meet the different system requirements for balancing resource consumption and response latency, the address lookup engine is designed to support various configurable lookup algorithms, primarily including two typical implementations: traversal and binary search.

[0125] The "traversal" algorithm works by sequentially reading each record in the address mapping table, comparing the input FPGA-side address with the starting address and length range of each mapping entry, and determining whether it falls within the mapping range. When the first matching entry is found, the corresponding host-side address information is returned. This method is simple in structure and suitable for small-scale applications with a small number of mapping table entries (e.g., less than 16 entries). In hardware implementation, it can control sequential access to dual-port RAM via a state machine, eliminating the need for additional sorting overhead, resulting in low resource consumption and suitability for area-sensitive designs. For example, in some embedded FPGA systems, if only 4-8 fixed memory window mappings are required, a fully parallel comparison structure can be used to complete the lookup operation in a single cycle.

[0126] The binary search algorithm relies on the premise that entries in the address mapping table are ordered by host-side or FPGA-side addresses. During the search process, the search range is gradually narrowed down through multiple binary comparisons until the target item is located. This method has a time complexity of O(log n), significantly better than the O(n) of linear traversal, and is particularly suitable for large mapping tables (e.g., exceeding 64 entries). In hardware implementation, iterative comparison logic combined with an address index register can be used to perform a midpoint comparison and update the boundary pointers every cycle; a pre-decoding mechanism can also be combined to improve the initial location speed. For example, in high-performance computing accelerator cards, when supporting hundreds of dynamically allocated virtual memory channels, a binary search engine can complete efficient addressing within a finite number of clock cycles, ensuring the real-time performance of DMA transfers.

[0127] The two algorithms described above can be flexibly selected or dynamically switched according to actual application requirements. For example, the system can set the currently used search mode through configuration registers; or the controller can automatically activate the optimal strategy based on the size of the currently loaded mapping table. In addition, other optional algorithms such as hash lookup and Trie trees can be introduced as extension schemes to further enhance the system's adaptability.

[0128] Through the above steps, this application achieves a multi-algorithm support design for the address lookup engine module. Because appropriate lookup algorithms are selected based on address mapping tables of different sizes, hardware resource utilization and system response speed are balanced while ensuring lookup accuracy. In small-scale mapping scenarios, a traversal method is used to reduce implementation complexity, while for large-scale ordered tables, a binary search method is used to significantly reduce the average lookup cycle, improving the overall throughput efficiency of the DMA engine. This design embodies the idea of ​​hardware-software co-optimization, enhancing the compatibility and scalability of the DMA engine in diverse application scenarios.

[0129] Example 6

[0130] Based on the above embodiments, this embodiment further provides:

[0131] The read / write channel separation design is mainly achieved by the FPGA-side request distribution module, which writes the requests received from the interface of the FPGA-side streaming data into the read request or write request buffer respectively; then the FPGA-side response generation module returns the read / write response to the FPGA side through the FPGA-side streaming data main interface.

[0132] Step 1: The FPGA-side request distribution module writes the requests received from the interface by the FPGA-side streaming data into the read request or write request buffer respectively, thereby realizing the separation of read and write channels;

[0133] The FPGA-side request distribution module is used to identify the type and make routing decisions for input requests received from the FPGA-side streaming data slave interface. The data stream received by this module includes packet header information, which at least includes a request type field (e.g., read or write operation), data address, and data length control information. The request distribution module classifies requests according to the request type field and directs read requests to a read request buffer queue and write requests to a write request buffer queue. The two buffer queues are physically independent and logically isolated from each other, avoiding resource contention, state machine conflicts, or bus arbitration delays caused by processing different types of operations on the same channel. The buffers can be implemented using a first-in, first-out (FIFO) structure with sufficient depth to absorb burst traffic and smooth data throughput. This mechanism achieves complete separation of read and write operations at the channel level, improving system parallelism and response efficiency.

[0134] As an optional implementation, the request distribution module can integrate priority scheduling strategies, such as setting higher priority for read requests to meet the needs of low-latency application scenarios; it can also support dynamic configuration of distribution rules to adapt to different peripheral bandwidth characteristics or business load patterns. Furthermore, the cache structure can be replaced with dual-port RAM or other forms of shared storage structure to optimize area overhead while ensuring read-write isolation.

[0135] Step 2: The FPGA-side response merging module then returns the read / write responses from the separated read / write channels to the FPGA side via the FPGA-side streaming data master interface.

[0136] The FPGA-side response merging module is responsible for aggregating completed read and write responses and outputting them to the FPGA's internal logic via the FPGA-side streaming data main interface. Since read and write operations are processed separately at the front end, the response messages originate from different execution paths—read responses come from feedback after a read operation from the host-side memory, while write responses originate from successful confirmation of a write operation to the host-side memory. The response merging module needs to orderly integrate the two types of responses, which can be achieved through polling, priority arbitration, or multiplexing to serialize them before sending them to the main interface. The main interface follows the AXI-Stream protocol or other streaming standards that support backpressure mechanisms to ensure that transmission can be paused when downstream processing capacity is insufficient, preventing data overflow.

[0137] In one embodiment, the response merging module can add a status identifier field based on the response type to facilitate parsing of the response content by the FPGA-side receiver; alternatively, a timestamp or sequence number mechanism can be introduced to ensure the consistency between the response and the original request. To improve throughput, the response channel can support parallel output from multiple lanes, which are then reordered and reassembled at the receiving end.

[0138] Through the above steps, this application achieves channel-level separation management of read and write requests in the FPGA-side DMA engine and centralized feedback of responses. By employing a request distribution mechanism to divert read and write operations to independent cache paths, contention and blocking issues in mixed channels are avoided, improving data transmission efficiency. Simultaneously, the response merging module enables the orderly integration and standardized output of response data, enhancing the system's structural clarity and maintainability. The overall design optimizes the data path architecture, reduces transaction processing latency, and is suitable for high-bandwidth, low-latency heterogeneous computing scenarios.

[0139] Example 7

[0140] Based on the above embodiments, this embodiment further provides:

[0141] The request and data separation design mainly includes a three-level pipelined process for requests consisting of FPGA-side read / write request caching, read / write request splitting and reassembly, and host-side memory read / write request caching; and a three-level pipelined process for data consisting of FPGA-side read / write data caching, read / write data reassembly module, and host-side memory read / write data request caching.

[0142] The request-data separation design refers to a design method in the DMA engine hardware architecture that logically isolates control information (i.e., requests) from the actual data transmission path. This design avoids mutual blocking by independently handling control flows such as addresses and commands with high-bandwidth data flows, thereby improving system parallelism and resource utilization. This separation mechanism is particularly suitable for large-scale data exchange scenarios between high-performance FPGAs and host memory, effectively reducing latency, increasing throughput, and enhancing system scalability and stability.

[0143] The FPGA-side read / write request buffer is used to temporarily store read or write operation requests initiated from the FPGA's local logic. These requests typically contain control fields such as the destination address, transfer length, and transaction type (read or write). The buffer is implemented using a first-in, first-out (FIFO) structure or a multi-port memory, supporting burst access and backpressure feedback mechanisms to ensure a stable input of upstream data streams even when downstream modules are busy. Its capacity can be configured based on the maximum number of concurrent requests in typical application scenarios; for example, it can be set to accommodate 32 write request entries in video streaming processing, while network packet forwarding applications may require supporting a deeper read request queue.

[0144] As an optional embodiment, the request cache can be divided into independent read request queues and write request queues to achieve physical isolation between read and write channels; alternatively, a unified cache space can be used, and transaction types can be distinguished by tags, thereby improving storage resource utilization. Furthermore, the cache can integrate priority scheduling logic to support QoS-based request ordering, such as assigning higher priority to small packet reads with high real-time requirements.

[0145] The read / write request reassembly module is responsible for adapting the original requests according to the host-side memory interface protocol specifications. For example, when a long burst access initiated by the FPGA side crosses multiple 4KB page boundaries or exceeds the host bus single-transfer limit, this module will automatically split it into multiple sub-requests conforming to the AXI (Advanced eXtensible Interface) protocol constraints. Each sub-request meets conditions such as address alignment, burst length not exceeding a limit (e.g., INCR8), and not spanning pages. After splitting, each sub-request is sequentially sent to the subsequent pipeline stage for processing.

[0146] In another embodiment, the module also has request merging capability: for consecutive small write requests, if their addresses are adjacent and no write response return condition is triggered, they can be temporarily stored and merged into a larger write operation to reduce host-side bus transaction overhead and improve write efficiency. This function is particularly suitable for DDR memory write optimization scenarios, helping to improve bank utilization and precharge efficiency.

[0147] The host-side memory read / write request cache is located at the front end of the DMA engine leading to the host memory controller. It buffers formatted read / write requests awaiting submission to the host bus. This cache not only performs rate matching but also absorbs fluctuations during host-side bus congestion or arbitration delays, ensuring that front-end processing remains unaffected. It is typically implemented as a multi-level deep FIFO structure and supports out-of-order submissions and completion status tracking to facilitate error recovery and retry mechanisms.

[0148] In some variants, the cache can also integrate an address conflict detection unit to prevent read and write requests for the same address range from competing for space; it can also introduce request deduplication logic to avoid repeatedly sending read operations for the same address range, thereby saving bandwidth resources.

[0149] Meanwhile, the FPGA-side read / write data buffer is mainly used to temporarily store data that is about to be written to the host memory or data read back from the host but not yet delivered to the FPGA user logic. The write data buffer receives streaming input from the FPGA's internal data source and organizes the storage according to the address unit corresponding to the request; the read data buffer is used to receive response data packets from the host side, reorder them according to the original request order, and output them to the target module.

[0150] These types of caches typically employ double-buffered or ring-buffered structures, supporting flow control backpressure signal transmission to ensure data integrity. In high-throughput scenarios, bandwidth capacity can be increased by increasing cache depth or using a distributed cache array. For example, in 100Gbps Ethernet bridging applications, write data cache depth can reach several kilobytes to cope with sudden traffic surges.

[0151] The core function of the read / write data reconstruction module is to convert and rearrange the data to meet the physical layer requirements of the host-side memory interface. For example, the FPGA-side data stream may be in 64-bit wide AXI-Stream format, while the host-side memory data interface requires a 512-bit wide AXI4 interface. In this case, the data reconstruction module needs to concatenate multiple 64-bit data into a complete 512-bit data block and adjust the byte positions according to the starting offset to ensure compliance with constraints such as 4K boundary alignment and burst length compliance.

[0152] This module typically combines control information (such as source offset, destination offset, and burst count) to dynamically calculate the reassembly strategy. Internally, it may contain shift register arrays, crossbars, or multiplexer networks, supporting flexible mapping between different bit widths. In low-latency mode, a bypass path can also be enabled to bypass the reassembly logic and minimize latency.

[0153] As an optional embodiment, this module can integrate ECC (Error Correction Code) encoding / decoding functions to add checksums before data is written or to perform error correction during reading, thereby enhancing data reliability. Furthermore, it can also support transparent transmission of compressed data streams, performing reassembly only on the uncompressed portions.

[0154] The host memory-side read / write data request cache is located at the front end of the host bus interface and is used to cache data transactions that are about to be sent or have just been received. In the write direction, it temporarily stores reassembled data blocks, waiting for the host-side write request to be approved before submitting them in batches; in the read direction, it is used to receive response data from the host and collect and sort it according to the request ID to ensure that the data returned to the FPGA side is in the correct order.

[0155] This type of cache often works in conjunction with the host-side request cache to form a complete request-data pairing management mechanism. Its design needs to consider the data consistency model, especially when there are multiple DMA channels or shared memory regions, and should support cache consistency protocols (such as the snoop mechanism in ACE) to prevent dirty data or duplicate reads.

[0156] The aforementioned technical features achieve efficient collaboration through precise timing and state synchronization: the request process originates from the FPGA side, sequentially passing through three stages: request caching, splitting and reassembling, and host-side request queuing, forming a deep three-level pipeline; the data process runs independently on another path, also undergoing local caching, reassembly processing, and host-side data queuing, maintaining decoupling from the request path. The two pipelines are associated and matched at the transaction completion point through transaction IDs or flag bits to ensure correct response returns.

[0157] Through the above-described steps, this application achieves complete separation and parallel processing of request and data paths. Since request processing is no longer affected by large data volume transmissions, the front end can continuously receive new requests, significantly improving overall processing throughput. Simultaneously, the three-stage pipeline effectively hides the processing latency at each stage, enabling the system to operate stably at higher clock frequencies. This design is particularly suitable for FPGA applications such as high-bandwidth, low-latency data acquisition, image processing, and AI inference acceleration, greatly enhancing the performance and adaptability of the DMA engine.

[0158] Example 10

[0159] Based on the above embodiments, this embodiment further provides:

[0160] The data reconstruction module mainly consists of a reconstruction information cache and a data reconstruction module. The reconstruction information includes the starting byte order offset and data burst count of the source data, and the starting byte order offset and data burst count of the destination data. Based on the above information, and in conjunction with the requirements of the host-side memory data interface and the FPGA-side streaming data interface, the data reconstruction module reconstructs and arranges the data. These data interface requirements include 4K boundary-aligned access, etc.

[0161] The reassembly information cache stores reassembly control parameters related to the current data transmission task, including the starting byte position of the source data in the FPGA-side streaming data stream (i.e., the starting byte order offset), the number of burst transmissions corresponding to the total amount of data to be transmitted (data burst number), the write start offset of the target host memory region, and the expected data burst length at the receiving end. This cache can be implemented using a register file or on-chip dual-port RAM, and can be preloaded by the control logic before the DMA transaction starts and read in real-time by the data reassembly module during data transmission to guide the reassembly behavior. As an optional implementation, this cache can also be integrated into the DMA engine's state machine, storing key offset and length parameters through a state register group, suitable for small-scale, fixed-pattern data transfer scenarios.

[0162] The data reorganization module is the core functional unit that performs the actual data rearrangement operation. Its input comes from the Axi-Stream format data stream on the FPGA side and the control parameters output from the reorganization information buffer. The output is adapted to the data organization format required by the host-side memory interface (such as AXI4). Internally, this module typically includes byte alignment logic, data splicing / splitting units, a burst length manager, and boundary detection circuitry. Specifically, the module first adjusts the effective starting point of the input data based on the starting byte order offset of the source data to ensure that the payload is acquired from the correct byte position. Then, based on the difference in the number of data bursts on the source and destination sides, it dynamically merges or splits the input data blocks to match the burst transmission requirements of the target interface (e.g., aggregating multiple short bursts into a long burst to improve bandwidth utilization). Simultaneously, the module incorporates a 4K boundary detection mechanism, which determines whether the current access crosses the 4KB address boundary before each host memory write request. If there is a risk of crossing the boundary, the current transmission is automatically split into two independent memory transactions, corresponding to the data segments before and after the boundary, thereby meeting the performance optimization requirements of most DDR controllers for continuous intra-page access.

[0163] The two components work together: the reorganization information cache provides static configuration parameters, serving as the context for the data reorganization module; while the data reorganization module dynamically adjusts the data flow and structure based on these parameters, enabling flexible data format conversion. Together, they contribute to the bridge-building process between the raw streaming data on the FPGA side and the host memory standard interface.

[0164] Through the above-described steps, the present invention achieves:

[0165] In heterogeneous systems, when the streaming data generated by the FPGA exhibits unaligned, variable-length, or non-standard burst characteristics, the data structure can be automatically reconstructed according to a preset reassembly strategy to comply with the strict access rules of host-side memory bus protocols (such as Advanced eXtensible Interface, AXI). Because an independent reassembly information cache is introduced to decouple control and data paths, the same hardware structure can adapt to various data mapping modes without redesigning logic circuits. Furthermore, because the data reassembly module possesses intelligent scheduling capabilities based on start offset and burst count, and enforces 4K boundary alignment, it avoids memory performance degradation caused by cross-page access. Therefore, this embodiment effectively improves the compatibility and transmission efficiency of the DMA engine in complex data interaction scenarios, enhancing the overall data throughput and resource utilization of the system.

[0166] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0167] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A hardware system for an address-mapped DMA engine based on an FPGA, characterized in that, Includes the following modules: The register module is used to initialize and control the modules of the system through the register access interface; The FPGA-side request distribution module is used to obtain read requests, write requests, and write data from the request packet header of the interface through the FPGA-side streaming data. The address mapping lookup module is used to obtain address mapping information in the address mapping table within the address mapping lookup module through a lookup algorithm; The read / write request reassembly module is used to reassemble read / write requests to obtain read / write requests on the host side. The write data reassembly module is used to reassemble the write data on the FPGA side using write data reassembly information to obtain write data that meets the requirements of the host side memory data interface. The host read / write request generation module is used to send out read requests, write data, and write data through the host-side memory data read / write request interface; The host-side response distribution module is used to obtain the response information of the corresponding request through the host-side memory data read and write response interface; The read data reconstruction module is used to reconstruct the host-side read data using read data reconstruction information to obtain read data that meets the requirements of the FPGA-side streaming data interface. The FPGA-side response generation module sends out the response header and read data through the FPGA-side streaming data master interface.

2. The FPGA-based address mapping DMA engine hardware system according to claim 1, characterized in that, The address mapping table is used to establish the correspondence between FPGA-side data addresses and host-side memory addresses; it is composed of dual-port RAM, supports simultaneous read and write access, and ensures low-latency queries at high frequencies; the mapping entries include source address segments, target address segments, and their mapping range sizes, allowing users to configure multiple virtual-to-physical address mapping intervals. When the FPGA initiates a data access request, the engine first searches the mapping table through the address lookup engine to determine whether the request falls within the valid mapping area, and obtains the corresponding host physical address starting point to complete the address translation process.

3. The FPGA-based address mapping DMA engine hardware system according to claim 1, characterized in that, The data reconstruction module performs dynamic data splicing or splitting operations based on the bit width difference between the FPGA-side streaming interface and the host-side memory interface; the write data reconstruction module combines multiple narrow bit-width streaming data packets into a wide bit-width AXI burst write data block; the read data reconstruction module sequentially decomposes the wide bit-width data into narrow bit-width data streams suitable for FPGA processing.

4. The FPGA-based address mapping DMA engine hardware system according to claim 1, characterized in that, The data reconstruction module takes as input a data stream in Axi-Stream format from the FPGA side and control parameters output from the reconstruction information buffer, and outputs data organization format adapted to the host-side memory interface. The module includes byte alignment logic, data splicing / splitting unit, burst length manager, and boundary detection circuit. It adjusts the effective starting point of the input data according to the starting byte order offset of the source data to ensure that the effective payload is acquired from the correct byte position. Then, based on the difference in the number of data bursts on the source and destination sides, it dynamically merges or splits the input data blocks to match the burst transmission requirements of the target interface.

5. The FPGA-based address mapping DMA engine hardware system according to claim 1, characterized in that, The host-side memory data interface adopts the AXI interface, which supports interconnection with AXI bus peripherals, thereby enabling the FPGA to exchange data with any bus peripheral through streaming data.

6. The FPGA-based address mapping DMA engine hardware system according to claim 1, characterized in that, The address mapping lookup module receives an address request signal from the FPGA-side streaming data interface and extracts the data address field. Then, it compares the address with the FPGA-side starting address and mapping size of each entry in the address mapping information table to determine whether the address falls within any valid mapping range. If a match is found, the corresponding host-side memory address is output, the original FPGA address is subtracted from the local mapping start offset, and the host-side base address is added to complete the address conversion. If no match is found, an address error exception will be triggered or the default processing path will be returned.

7. The FPGA-based address mapping DMA engine hardware system according to claim 1, characterized in that, The host-side memory data interface is located at the front end of the host bus interface and is used to send or receive data transactions. In the write direction, it works with the host-side write request cache and the host-side data cache to temporarily store the reassembled data blocks and submit them after the host-side write request interface becomes idle. In the read direction, it works with the host-side read data cache and the host-side response value cache to receive response data from the host and collect and sort it according to the request ID to ensure that the data returned to the FPGA side is in the correct order.

8. A method for implementing an FPGA-based address-mapped DMA engine hardware system as described in any one of claims 1-7, characterized in that, Includes the following steps: Step 1: Parse the FPGA-side streaming data through the FPGA-side request distribution module to obtain read / write requests and write data. The read / write requests are written to the corresponding FPGA-side read / write request caches, and the write data is written to the FPGA-side write data cache. At the same time, the response information corresponding to the request is written to the FPGA-side response information cache. Step 2: The read / write request is used to find the corresponding address mapping information in the address mapping table through the address lookup module. Combined with the alignment rules of the host-side memory request, the read / write request is reassembled to obtain the host read / write request and read / write reassembly information, and written into the host-side read / write request cache and read / write reassembly information cache. Step 3: Read the FPGA write data from the FPGA write data cache, reassemble the data according to the write data reassembly information through the write data reassembly module, and write it into the host write data cache; Step 4: The host-side read / write request generation module reads from the host-side read / write request cache and sends the request out through the host-side memory data read / write request interface. If it is a write request, it continues to read the write data from the host-side write data cache and sends the write data out through the above interface. Step 5: The host-side response distribution module receives the response from the host-side memory data read / write response interface, writes the response value into the host-side response value cache, and if the response is a read response, stores the subsequent read data into the host-side read data cache. Step 6: Read the host-side read data from the host-side read data cache, reassemble the data according to the read data reassembly information through the read data reassembly module, and write it into the FPGA-side read data cache; Step 7: The FPGA-side response generation module reads the FPGA-side response information from the corresponding cache and combines it with the host-side response value to generate an FPGA-side response, which is then sent out through the FPGA-side streaming data interface. If the response is a read response, the module continues to read read data from the FPGA-side read data cache and sends the read data out through the aforementioned interface.

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