UART architecture with automatic time pinch function

Abstract

The invention provides a UART (Universal Asynchronous Receiver / Transmitter) architecture with an automatic time pinching function, which belongs to the technical field of embedded system design and comprises a serial-to-parallel conversion module, a timer module, a receiving FIFO (First In First Out) module, an interrupt processing module, a register configuration module, a sending FIFO module, a parallel-to-serial conversion module and a local parallel bus management module. The framework can automatically identify the interval between each frame of data on a signal line in the data receiving process, the interval time is used as a time segment and is written into a receiving cache queue FIFO together with the frame data, and an upper computer CPU can analyze the interval time between the frame data and the previous frame data through a timestamp while reading the cache queue data. Therefore, whether the frame data is the packet header of the data packet or not is effectively judged. Through design, simulation and verification, a logic function module is formed and can be directly used in the FPGA.

Description

Technical Field

[0001] This invention belongs to the field of embedded system design technology, specifically relating to a UART architecture with automatic time-counting function. Background Technology

[0002] UART is a universal serial data bus used for asynchronous communication. This bus allows for bidirectional communication, enabling full-duplex transmission and reception. In embedded design, RS422 and RS485 interfaces based on UART communication are widely used.

[0003] In industrial control and other applications, periodic real-time data transmission is required. The sender periodically sends packets of data consisting of multiple frames to the online system. The receiver needs to parse the complete packet data from the received multiple frames to perform closed-loop control. In asynchronous communication scenarios, the receiver uses a receive FIFO buffer. If, due to software task cycle conflicts or other issues, the packet data in the FIFO buffer is not read in time, the multiple frames obtained from the receive FIFO may contain mixed data from previous and next frames. Software then needs to reassemble and recover the data.

[0004] Currently used UART standards such as UART16550 and UART16650 do not have time-triggered functionality when receiving data. Therefore, the traditional software processing method involves inserting frame data representing packet header characteristics into the packet data, and the receiver parses this frame data to determine the packet header. This processing method incurs significant software overhead, and if a valid data frame with the same header characteristics exists in the packet data, it can lead to software parsing errors, resulting in system misjudgment.

[0005] Therefore, developing a UART circuit that can effectively characterize the time interval of frame data transmission on the bus is of great significance for improving the performance of real-time control systems. Summary of the Invention

[0006] The purpose of this invention is to provide a UART architecture with automatic time-counting function. By using a timer module, the interval time of online transmission can be obtained to effectively characterize whether a data frame is a packet header, thereby enabling the host computer to efficiently and accurately assemble and parse data packets, forming a standard modular product and improving the versatility of the interface circuit.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a UART architecture with automatic time-counting function, comprising: The serial-to-parallel conversion module is connected to the UART serial receive signal and is used to convert UART serial input data into parallel data. The timer module receives UART serial signals as input and uses an 8-bit accumulator as the timer. The receiving FIFO module is connected to the output terminals of the serial-to-parallel conversion module and the timer module. It is used to combine the frame interval time output by the timer module and the frame data output by the serial-to-parallel conversion module into 16-bit data and write it into the receiving FIFO. The interrupt handling module, whose input is connected to the output of the receiving FIFO module, is used to generate receive overflow and receive timeout interrupt signals by detecting the amount of data in the receiving FIFO module. The local parallel bus management module is connected to the output of the receiving FIFO module and the output of the interrupt handling module. It is used to perform address latching, decoding, and status register setting of the local parallel bus. The transmit FIFO module writes to the local parallel bus management module at the port parallel to buffer the transmitted data. The parallel-to-serial conversion module, with its input connected to the read port of the transmitting FIFO module, is used to convert parallel input data into serial data output. The register configuration module is used to configure the working modes of the receive FIFO module, transmit FIFO module, and interrupt handling module.

[0008] The UART architecture with automatic time-counting function provided by this invention also has the following technical feature: the timer module is configured to count according to the following rules: the timer value is incremented by 1 for each symbol time, with a maximum count value of 255; the timer stops when the maximum count value is reached.

[0009] The UART architecture with automatic timing function provided by this invention also has the following technical features: the timer module detects the UART serial received signal at the input terminal in real time. When the stop bit of a frame of serial data is detected, the timer starts to accumulate from 0. When the start bit of a frame of serial data is detected, the timer stops counting and saves the current timer value as the interval time between the current frame of data and the previous frame of data, and outputs it to the receiving FIFO module.

[0010] The UART architecture with automatic time-triggered function provided by this invention also has the following technical features: the local parallel bus management module is configured so that the host computer can read the data in the receiving FIFO through the local parallel bus management module. The high and low 8 bits of the data represent the interval between the current frame data and the previous frame data and the valid frame data, respectively. The host computer software determines whether the frame data is the packet header of the packet data by the frame interval time.

[0011] The UART architecture with automatic time-triggered function provided by this invention also has the following technical features: the working modes configured by the register configuration module include: FIFO depth, interrupt enable, interrupt trigger depth, timeout time, and full-duplex / half-duplex mode.

[0012] Beneficial effects: The UART architecture with automatic time-triggered function provided by this invention can effectively characterize whether a data frame is a packet header by obtaining the interval time of online transmission through the timer module, thereby enabling the host computer to efficiently and accurately assemble and parse data packets, forming a standard modular product and improving the versatility of the interface circuit. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a block diagram of a UART architecture with automatic time-counting function provided in an embodiment of the present invention. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent changes or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the protection scope of the present invention.

[0016] In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the invention.

[0017] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0018] The terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art will understand the specific meaning of these terms in this invention based on the specific circumstances.

[0019] like Figure 1 As shown, this embodiment of the invention provides a UART architecture with automatic time-triggered functionality, including: The serial-to-parallel conversion module is connected to the UART serial receive signal and is used to convert the UART serial input data into parallel data RX_DATA[7:0] and write it into the receive FIFO module; The timer module receives UART serial signals as input and uses an 8-bit accumulator as the timer. The receiving FIFO module is connected to the output of the serial-to-parallel conversion module and the timer module. It is used to combine the frame interval time RX_TIME[7:0] output by the timer module and the frame data RX_DATA[7:0] output by the serial-to-parallel conversion module into 16-bit data and write it into the receiving FIFO. The read port is connected to the input RX_DOUT of the local parallel bus management module, and the number of data buffered in the current FIFO FIFO FIFO_CNT is output to the interrupt handling module. The interrupt handling module is connected to the output of the receiving FIFO module. It is used to generate receive overflow and receive timeout interrupt signals by detecting the amount of data in the receiving FIFO module. When the interrupt trigger depth or the receive timeout period is exceeded, an interrupt signal is generated. The interrupt signal is connected to the local parallel bus management module. The local parallel bus management module is connected to the output of the receiving FIFO module and the output of the interrupt handling module. It is used to perform address latching, decoding, and status register setting of the local parallel bus. The transmit FIFO module writes to the local parallel bus management module at the port parallel to buffer the transmitted data. The parallel-to-serial conversion module, with its input connected to the read port of the transmitting FIFO module, is used to convert parallel input data into serial data output. The register configuration module is used to configure the working modes of the receive FIFO module, transmit FIFO module, and interrupt handling module.

[0020] The architecture provided in the above embodiments can automatically identify the interval between each frame of data on the signal line during data reception, and write this interval as a timestamp along with the frame data into the receive buffer queue FIFO. While the host computer CPU reads the data from the buffer queue, it can parse the interval between the current frame and the previous frame using the timestamp, thereby effectively determining whether the current frame is the header of a data packet. Through design, simulation, and verification, a logical functional module is formed, which can be directly used in an FPGA.

[0021] In some embodiments, the timer module is configured to time according to the following rules: the timer increments by 1 for each symbol of time elapsed (e.g., at a baud rate of 9600, one symbol represents 1 / 9600 seconds), with a maximum time value of 255 (the maximum value represented by an 8-bit binary number); the timer stops when the maximum time value is reached.

[0022] The timer module can obtain the interval between the start bit of each frame of data and the stop bit of the previous frame of data from the received signal line, which is used as the frame interval time RX_TIME[7:0]. The interval time is in units of symbols through adaptive baud rate.

[0023] In some embodiments, the timer module detects the UART serial receive signal at the input terminal in real time. When the stop bit of a frame of serial data is detected, the timer starts to accumulate from 0. When the start bit of a frame of serial data is detected, the timer stops counting and saves the current timer value as the interval time RX_TIME[7:0] between the current frame of data and the previous frame of data, and outputs it to the receiving FIFO module.

[0024] In some embodiments, the local parallel bus management module is configured so that the host computer can read the data in the receiving FIFO through the local parallel bus management module, and can parse out 8 bits of valid frame data and 8 bits of time tag. The high and low 8 bits of the data represent the interval between the current frame data and the previous frame data and the valid frame data, respectively. The host computer software determines whether the frame data is the packet header of the packet data by the frame interval time reflected by the 8 bits of time tag.

[0025] In some embodiments, the operating modes configured by the register configuration module include: FIFO depth, interrupt enable, interrupt trigger depth, timeout time, and full-duplex / half-duplex mode.

[0026] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the protection scope of the present invention.

Claims

1. A UART architecture with automatic time-triggered function, characterized in that, include: The serial-to-parallel conversion module is connected to the UART serial receive signal and is used to convert UART serial input data into parallel data. The timer module receives UART serial signals as input and uses an 8-bit accumulator as the timer. The receiving FIFO module is connected to the output terminals of the serial-to-parallel conversion module and the timer module. It is used to combine the frame interval time output by the timer module and the frame data output by the serial-to-parallel conversion module into 16-bit data and write it into the receiving FIFO. The interrupt handling module, whose input is connected to the output of the receiving FIFO module, is used to generate receive overflow and receive timeout interrupt signals by detecting the amount of data in the receiving FIFO module. The local parallel bus management module is connected to the output of the receiving FIFO module and the output of the interrupt handling module. It is used to perform address latching, decoding, and status register setting of the local parallel bus. The transmit FIFO module writes to the local parallel bus management module at the port parallel to buffer the transmitted data. The parallel-to-serial conversion module, with its input connected to the read port of the transmitting FIFO module, is used to convert parallel input data into serial data output. The register configuration module is used to configure the working modes of the receive FIFO module, transmit FIFO module, and interrupt handling module.

2. The UART architecture with automatic time-triggered function according to claim 1, characterized in that, The timer module is configured to keep time according to the following rules: the timer value is incremented by 1 for each symbol time elapsed, with a maximum time value of 255; the timer stops when the maximum time value is reached.

3. The UART architecture with automatic time-matching function according to claim 1, characterized in that, The timer module detects the UART serial receive signal at the input terminal in real time. When a stop bit of a frame of serial data is detected, the timer starts to accumulate from 0. When a start bit of a frame of serial data is detected, the timer stops counting and saves the current timer value as the interval between the current frame of data and the previous frame of data, which is then output to the receiving FIFO module.

4. The UART architecture with automatic time-matching function according to claim 1, characterized in that, The local parallel bus management module is configured so that the host computer can read the data in the receiving FIFO through the local parallel bus management module. The high and low 8 bits of the data represent the interval between the current frame data and the previous frame data and the valid frame data, respectively. The host computer software determines whether the frame data is the packet header by the frame interval time.

5. The UART architecture with automatic time-matching function according to claim 1, characterized in that, The working modes configured by the register configuration module include: FIFO depth, interrupt enable, interrupt trigger depth, timeout time, and full-duplex / half-duplex mode.

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