Reading-mode-selectable low-power-consumption parallel-serial conversion circuit and method suitable for large array
By using a dual-pipeline parallel architecture with odd and even column partitioning and an adaptive sleep circuit, the problems of power consumption and area overhead under large array scale are solved, and low-power parallel-to-serial conversion is achieved, which is suitable for large array readout circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-04-10
AI Technical Summary
As the scale of large arrays increases, the power consumption and area overhead of existing parallel-to-serial conversion circuits gradually increase, becoming an important part of the power consumption of large array chips.
A dual-pipeline parallel architecture with parity column partitioning is adopted, combined with an adaptive sleep circuit module, to realize sequential readout, window selection and mirror readout modes. Power consumption is reduced by interleaving control of parity code value chain and data chain.
In different readout modes, it significantly saves the area and power consumption of the digital section, and is especially suitable for large array readout circuits. The adaptive sleep function further reduces power consumption.
Smart Images
Figure CN121841371A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a low-power parallel-to-serial conversion circuit and method with selectable readout modes suitable for large arrays. BACKGROUND
[0002] Parallel-to-serial conversion circuits can realize conversion between signal parallel and serial, and are an important module in signal transmission. Shift register type parallel-to-serial conversion circuits are widely used in large array parallel readout structures due to their advantages of single clock, high stability, and suitability for parallel-to-serial output of any bit.
[0003] Large array readout circuits usually have the needs of sequential readout, window selection, and mirror readout of array data. The traditional implementation mode is to sequentially read out data to digital, then perform cache processing on the data, and after the entire array data is read out, complete window selection and mirror readout of the data. However, with the increase of the array size, the data volume increases exponentially, and this implementation mode becomes a large source of power consumption and area overhead. In addition, the circuit size and power consumption of the shift register type structure are linearly positively correlated with the parallel data volume. With the gradual increase of the array size, the power consumption of the parallel-to-serial conversion circuit itself also gradually becomes an important part of the power consumption of the large array chip. SUMMARY
[0004] Therefore, the present application aims to provide a low-power parallel-to-serial conversion circuit and method with selectable readout modes suitable for large arrays to solve the problem that the power consumption and area overhead gradually increase with the gradual increase of the array size in the prior art.
[0005] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows: In a first aspect, the present application provides a low-power parallel-to-serial conversion circuit with selectable readout modes suitable for large arrays, which is based on a shift register structure and adopts a double-pipeline parallel architecture with odd and even column division; including three modes of sequential readout, window selection, and mirror readout; including a clock chain, an odd code value chain, an even code value chain, a data chain, an adaptive sleep circuit module, and an array circuit module; The odd code value chain, the even code value chain, the data chain, the adaptive sleep circuit module, and the array circuit module are all connected with the clock chain, and the odd code value chain, the even code value chain, the data chain, and the adaptive sleep circuit are all connected with the array circuit; The array circuit module includes a plurality of partition circuit modules, The plurality of partition circuit modules are divided into odd partition circuit modules and even partition circuit modules, and the odd partition circuit modules and the even partition circuit modules both include a partition control circuit module and a column readout circuit module. The odd partition circuit module is one-to-one mapped with the D flip-flop group on the odd code value chain, and the two are connected; The even partition circuit module is one-to-one mapped with the D flip-flop group on the even code value chain, and the two are connected; The partition circuit module is one-to-one mapped with the D flip-flop group on the data chain, and the two are connected; The clock chain provides a synchronous clock for the D flip-flop group on the odd code value chain, the D flip-flop group on the even code value chain, the D flip-flop group on the data chain, and the partition control circuit module.
[0006] Further, The column readout circuit module is divided into left and right parts, and each of the left and right parts includes The column readout circuit module.
[0007] Further, the partition circuit module includes a two-stage multiplexer structure, a first-stage multiplexer is used for column data gating within a partition, and a second-stage multiplexer is used for data switching between partitions.
[0008] Further, the adaptive sleep circuit module includes a D flip-flop, an AND gate, an OR gate, and a decoder, an input end of the D flip-flop is connected to a low-power-consumption control signal output by a previous partition circuit module, an output end of the D flip-flop is connected to an input end of the AND gate, another input end of the AND gate is connected to an output end of the OR gate, an output end of the AND gate is connected to a next partition circuit module, one input end of the OR gate is connected to the decoder, and another input end of the OR gate is connected to an output end of a decoder within the partition circuit module.
[0009] Further, the number of flip-flops of the D flip-flop group on the odd code value chain and the even code value chain is .
[0010] In a second aspect, based on the same inventive concept, the application further provides a low-power-consumption parallel-to-serial conversion method with selectable readout modes for a large array, including the following steps: S1, initialization and monitoring: a high enable signal is pulled up to start the circuit, and after a number of cycles, a code value input flag signal is pulled up to receive bit code values, obtain high bit partition code values and low bit column code values, based on the partition code values, decode to select a target partition, and close subsequent unselected partitions; S2, partition data readout: in the selected partition, based on the column code values, decode to control the gating of the corresponding column buffer, data is transmitted to the D flip-flop through a two-stage multiplexer for synchronous output, the data output flag signal is pulled up, and data starts to output; S3, adaptive sleep control: in sequential readout, the next partition is woken up in advance, in mirror readout, the clock of the completed partition is closed, and the clock of the unselected partition remains closed; S4, data end processing: at the end of window selection, the code value input flag signal is pulled low, the decoding is stopped, the data output flag signal is pulled low, indicating that the data output is completed, and after the code value input flag signal is pulled low for several periods, the enable signal is pulled low, and the circuit is closed.
[0011] Further, in step S1, the partition code value and the column code value both use Gray code.
[0012] Compared with the prior art, the low-power parallel-to-serial conversion circuit and method suitable for large array and having selectable readout modes have the following beneficial effects: In the parallel-to-serial conversion stage, functions such as sequential readout, window selection, and mirror readout are realized, which can save the corresponding area and power consumption of the digital part, and is especially suitable for large array readout circuits that need such functions. Meanwhile, in cooperation with different readout modes, the completed parallel-to-serial conversion part or the part that does not need to be read out is automatically put to sleep, further saving the power consumption of the circuit. BRIEF DESCRIPTION OF DRAWINGS
[0013] The accompanying drawings, which form a part of the present application, are intended to provide further understanding of the present application, and are used to explain the illustrative embodiments of the present application and their descriptions, and do not constitute improper limitations on the present application. In the drawings: Figure 1 The overall architecture schematic diagram described in the embodiments of the present application; Figure 2 The working timing schematic diagram described in the embodiments of the present application; Figure 3 The partition circuit module schematic diagram described in the embodiments of the present application; Figure 4 The adaptive sleep circuit module schematic diagram described in the embodiments of the present application. DETAILED DESCRIPTION
[0014] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0015] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" and the like can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.
[0016] In the description of the present application, it needs to be understood that the terms "installation", "connection", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood by specific circumstances.
[0017] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.
[0018] As Figure 1 shown, the overall architecture schematic diagram, compared with the conventional shift register type parallel-to-serial conversion circuit, the present application divides the array into odd partition and even partition, respectively reads out the data of odd partition and even partition through odd code value chain and even code value chain, thereby dividing the entire parallel-to-serial conversion process into two pipeline structures controlled by the same clock, through the timing interlacing of the two pipelines, realizing the reading out of data in any direction, and without the problem of overlapping and repetition of output data, ensuring the integrity of the readout data.
[0019] The overall architecture includes clock chain, odd code value chain, even code value chain, data chain and local logic circuit module, which includes adaptive sleep circuit module and array circuit module, To further reduce power consumption, the array circuit module is divided into k partition circuit modules, which are further divided into odd partition circuit modules and even partition circuit modules. Each partition circuit module includes a partition control circuit module and m column readout circuit modules. For odd partitions, D flip-flops (DFFs) are used on the odd code value chain, and the outputs of the DFFs are connected to the odd partition. Buffers are used on the even code value chain, but these buffers are not connected to the odd partition; instead, they transmit the code value to the next partition. For even partitions, the opposite is true: D flip-flops are used on the even code value chain, and the outputs of the DFFs are connected to the even partition. Buffers are used on the odd code value chain. On the clock chain, each partition has a set of buffers connected in series to ensure the integrity of the clock signal and to ensure that the clock signal between partitions is slower than the code value signal. The clock chain provides a synchronous clock for the D flip-flop groups on the odd code value chain, the even code value chain, the D flip-flop groups on the data chain, and the partition control circuit module. On the data chain, each partition has n×p D flip-flops, and the D flip-flops between partitions are connected in series via multiplexers (MUX).
[0020] like Figure 2 The diagram shows the timing sequence, including both sequential and mirror readout timings. By misaligning the two sets of code values, correct data reading from the data chain is achieved. To reduce power consumption, both sets of code values use Gray code, meaning that each readout of data from the two code value chains only involves one flip. The entire parallel-to-serial conversion circuit receives an enable signal from the enable signal line Col_en_15. When reading begins, the enable signal needs to be pulled high at least two cycles in advance to wake up the circuit, and then the clock chain and code value chain start working sequentially. When the code value input flag signal line Col_flag_in_15 is pulled high, the code value signal transmitted by the code value chain is valid, and Col_flag_in_15 is synchronously transmitted to the corresponding partition's data chain along with the code value. The data output flag signal line Col_flag_out_15 outputs the data output flag signal (pulled high) synchronously with the data. Since the parallel-to-serial conversion circuit supports different modes, the output data timing is uncertain; the data is only valid when Col_flag_out_15 is pulled high. Simultaneously, the clock output signal line Col_clk_out_15 outputs a clock signal for data synchronization. After the array readout is complete, Col_flag_in_15 is pulled low, and subsequent input code values become invalid. After a certain period, Col_flag_out_15 is pulled low, and the data is no longer valid. Col_en_15 needs to be maintained low for at least k periods before being pulled low, and the entire parallel-to-serial conversion circuit enters a sleep state.
[0021] like Figure 3As shown, the partition circuit module schematic diagram, in order to reduce the timing requirements, each partition will be divided into m column readout circuit left and right m / 2 column, both sides of the data to the middle multiplexer transmission. In the partition, the code value on the code value chain is split into two parts, high bit for partition code value, corresponding D flip-flop connection within the decoder, after decoding to determine whether the partition is selected, low bit for column code value, control within the column gating, the corresponding D flip-flop output end is connected to the buffer on both sides of the partition, column code value is transmitted to both sides of the partition and then use D flip-flop synchronization once, and then sent to the decoder within the partition, through the decoder output non overlapping signal control column buffer in turn will be m column readout circuit data read out, complete a n x m column to n x p column parallel to serial conversion, through the multiplexer data transmission to the data chain in turn output. When the partition is not selected, the multiplexer continues to determine the gating subsequent partition, the data of the selected partition is read out in turn, so as to realize a k column to 1 column parallel to serial conversion, finally output data, complete the overall n x m x k column to n x p column parallel to serial conversion.
[0022] As Figure 4 shown, the adaptive sleep circuit module schematic diagram, the input end of D flip-flop is connected with the low power control signal Lowpower_15 <k-1>, the output of which is connected to one input of an AND gate, the other input of the AND gate being connected to the output of an OR gate, the output of the AND gate being connected to the next partition. One input of the OR gate is connected to a small decoder, the other input of the OR gate being connected to the output of the decoder in the corresponding partition Bank_select_15 <k>. In the absence of a partition being selected, and after Col_en_15 is pulled high, the serial to parallel circuit enters a monitoring mode, and once a partition is selected, Bank_select_15 <k>The signal is pulled low, and the output of the AND gate, Lowpower_15 <k>pulls low so that the circuit after the partition is turned off, clock is cut off, and enters the sleep mode. In the mirror readout, the partition circuit from left to right is turned off in turn as the data is read out, and when the sequential readout is performed, the decoder is pulled high at least two periods before the partition readout is completed, so as to wake up the next partition to prepare for the clock.
[0023] Embodiment one: The embodiment is applied to a parallel-serial conversion circuit of a CMOS image sensor array readout circuit, and the sensor chip is implemented under the condition of a 110 nm process. The parallel readout array of the whole chip is 1296 columns, each column of data is 13 bits, the whole array is divided into 6 partitions (k=6), 4 middle partitions include 256 columns (m=256), and 2 edge partitions include 136 columns. In order to speed up the data readout, the data bus is 13*4 column parallel readout (n=13, p=4). Therefore, the parallel-serial conversion circuit realizes 13*1296 column to 13*4 column parallel-serial conversion as a whole.
[0024] Taking the sequential window selection mode as an example, the working process of the parallel-serial conversion circuit is as follows: A1. First, at the beginning of the parallel-serial conversion readout, Col_en_15 is pulled high, and the parallel-serial conversion circuit starts to monitor the code value chain. After 4 periods, Col_flag_in_15 is pulled high, the code value starts to be input, the corresponding partition is selected, the low-power-consumption signal in the partition is pulled low, and the subsequent partition is turned off.
[0025] A2. In the selected kth partition, according to the input code value, the corresponding column buffer is enabled, the data is transmitted to the enable multiplexer in the middle of the partition, and then transmitted to the D flip-flop output end through the second multiplexer, and then read out to the next stage D flip-flop through clock synchronization. The data in the partition is read out from left to right in turn. At the same time, for the whole parallel-serial conversion circuit, Col_flag_in_15 is pulled high for a period, and Col_flag_out_15 is pulled high, which represents that the data starts to be read out.
[0026] A3. When the fourth group of data in the kth partition is read out, the decoder in the low-power-consumption module is pulled high, the low-power-consumption signal is pulled high, and the k+1th partition is woken up four periods in advance. Due to the difference in the number of D flip-flops in the transmission between the partitions, the k+1th partition starts decoding in advance to ensure that the data splicing between the partitions is correct. When the data in the kth partition is read out, the multiplexer at the input end of the D flip-flop is enabled to the next partition, and the data in the k+1th partition starts to be read out.
[0027] A4, data is read out to the end of window selection, Col_flag_in_15 is pulled down, no longer decoding, after a period of time, Col_flag_out_15 is pulled down, data read out is completed, Col_flag_in_15 is pulled down for 8 periods of time, Col_en_15 is pulled down, and the serial-parallel conversion circuit stops working, and the readout is ended.
[0028] The application can not only reduce the area and power consumption required by functions such as mirror readout or window selection readout, but also can reduce the power consumption by different degrees according to different modes. In the conditions of sequential readout and mirror readout, the power consumption is about 60% of the power consumption of the traditional structure; and in the condition of window selection readout, according to the size of the selected window, the power consumption corresponding to the window from 0 to the full array will be 0-60% of the original.
[0029] The innovation points of the application are: The serial-parallel conversion circuit with optional readout mode and the self-adaptive sleep power reduction function based on the readout mode.
[0030] The advantages and beneficial effects of the application are: The functions such as sequential readout, window selection and mirror readout are realized in the serial-parallel conversion stage, which can save the corresponding area and power consumption of the digital part, and is especially suitable for large array readout circuits which need such functions. Meanwhile, the completed serial-parallel conversion part or the part which does not need to be read out is automatically put into sleep according to different readout modes, so as to further save the power consumption.
[0031] The above only describes the preferred embodiments of the application and should not be used to limit the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application should be included in the protection scope of the application.< / k> < / k> < / k>
Claims
1. A low-power and serial conversion circuit with selectable readout mode for large array, characterized in that: a double-pipeline parallel architecture based on shift register structure and odd-even column division is adopted; three modes of sequential readout, window selection and mirror readout are included; a clock chain, an odd code value chain, an even code value chain, a data chain, an adaptive sleep circuit module and an array circuit module are included; the odd code value chain, the even code value chain, the data chain, the adaptive sleep circuit module and the array circuit module are connected with the clock chain, and the odd code value chain, the even code value chain, the data chain and the adaptive sleep circuit are connected with the array circuit; The array circuit module comprises a partition circuit module, The array circuit module comprises a column readout circuit module; the odd partition circuit module is one-to-one mapped with the D flip-flop group on the odd code value chain and connected with the D flip-flop group; the even partition circuit module is one-to-one mapped with the D flip-flop group on the even code value chain and connected with the D flip-flop group; the partition circuit module is one-to-one mapped with the D flip-flop group on the data chain and connected with the D flip-flop group; the clock chain provides synchronous clock for the D flip-flop group on the odd code value chain, the D flip-flop group on the even code value chain, the D flip-flop group on the data chain and the partition control circuit module.
2. The low power consumption and serial conversion circuit with selectable readout mode suitable for large array according to claim 1, characterized in that: The readout circuit module is divided into left and right parts, and each of the left and right parts includes Column readout circuit modules.
3. The low power consumption and serial conversion circuit with selectable readout mode suitable for large array according to claim 2, characterized in that: the partition circuit module includes a two-stage multiplexer structure, the first-stage multiplexer is used for column data gating within a partition, and the second-stage multiplexer is used for data switching between partitions.
4. The low power consumption and serial conversion circuit with selectable readout mode suitable for large array according to claim 1, characterized in that: the adaptive sleep circuit module includes a D flip-flop, an AND gate, an OR gate and a decoder, the input end of the D flip-flop is connected with the low-power control signal output by the previous partition circuit module, the output end of the D flip-flop is connected with the input end of the AND gate, the other input end of the AND gate is connected with the output end of the OR gate, the output end of the AND gate is connected with the next partition circuit module, one input end of the OR gate is connected with the decoder, and the other input end of the OR gate is connected with the output end of the decoder within the partition circuit module.
5. The low power consumption and serial conversion circuit with selectable readout mode suitable for large array according to claim 1, characterized in that: The trigger number of the D trigger group on the odd code value chain and the even code value chain is .
6. A low-power and parallel-to-serial conversion method with selectable readout mode for large arrays, applied to the low-power and parallel-to-serial conversion circuit with selectable readout mode for large arrays according to any one of claims 1-5, characterized in that: the steps include: S1, initialization and monitoring: pull high enable signal to start the circuit, after several cycles, pull high code value input flag signal, receive bit code value, get high bit partition code value and low bit column code value, based on the partition code value, decode the selected target partition, and close the subsequent unselected partitions; S2, partition data readout: in the selected partition, based on the column code value, the corresponding column buffer is gated by decoding control, the data is transmitted to the D flip-flop through the two-stage multiplexer and is synchronously output, the data output flag signal is pulled high, and the data starts to output; S3, adaptive sleep control: in the sequential readout, the next partition is woken up in advance, in the mirror readout, the clock of the completed partition is turned off, and the clock of the unselected partition is kept off; S4, data end processing: at the end of the window selection, the code value input flag signal is pulled low, the decoding is stopped, the data output flag signal is pulled low, the data output is completed, the code value input flag signal is pulled low for a plurality of periods, the enable signal is pulled low, and the circuit is turned off.
7. A low power consumption and serial conversion method with selectable readout mode for large arrays according to claim 6, characterized in that: In step S1, the partition code value and the column code value both adopt Gray code.