Computing device, computing array and computing system

Abstract

The invention discloses a computing device, a computing array and a computing system.The computing device, the computing array and the computing system.The computing device, the computing array and the computing system.The computing device comprises an input port, an optical power distribution assembly, a programmed switch, an integrating capacitor, an accumulation activation unit and a mantissa quantization unit; the optical signals are distributed according to a binary weight proportion through an optical power distribution assembly, the optical signals are distributed to a plurality of optical detectors for detection, and the power proportion of the optical signals received by the optical detectors is 1 / 2 N power. An optical signal is input, the optical power distribution assembly divides the input optical signal into light currents with different relative intensities, the light currents are respectively converted into light currents by corresponding light detectors, and the light currents passing through a plurality of detectors of the power distribution device are combined through a group of programmed switches and flow into an integrating capacitor, so that the integrating capacitor is charged to generate voltage; the scheme of accumulating activation units is simple, and energy loss is reduced.

Description

Technical Field

[0001] This invention relates to the field of computing devices, computing arrays, and computing systems, specifically to a computing device, computing array, and computing system. Background Technology

[0002] Deep learning, one of the hottest research areas in artificial intelligence today, involves a large number of matrix multiplications. Using light for matrix operations is an emerging research direction. However, existing optical chips for matrix operations have several problems. On the one hand, the performance of optical computing chips is positively correlated with the number of devices integrated on-chip, and the use of a large number of optical devices causes losses, resulting in significant light loss within the optical chip. On the other hand, the programming control of optical computing chips is achieved by adjusting the refractive index of materials during light propagation, usually by controlling the phase of the waveguide or additional losses. Synchronously controlling a large number of optical devices may involve complex synchronization, require high power consumption, introduce unwanted additional losses, occupy a large chip area, or have limited control speed of the devices themselves, thus limiting practical applications.

[0003] The shortcomings of existing computing devices, computing arrays, and computing systems are: 1. Patent document CN112308224B discloses an optical neural network device, chip, and optical implementation method for neural network computation, "including: a light generating sub-device for generating N optical signals of different wavelengths; N being an integer greater than 1; a first modulation sub-device for modulating the intensity of the N optical signals according to N first voltages to obtain N first optical signals; a first conversion sub-device for performing parallel-to-serial conversion on the N first optical signals to obtain second optical signals; a beam splitter for splitting the second optical signals into N third optical signals; and a second modulation sub-device for... N first voltage sets are used to modulate the intensity of N third optical signals to obtain N fourth optical signals; a second conversion sub-device is used to convert each of the N fourth optical signals from serial to parallel to obtain N fifth optical signals; a processing sub-device is used to adjust the values ​​of the N first voltages and the N first voltage sets based on the N fifth optical signals. However, existing computing devices, computing arrays, and computing systems use a large number of optical delay units, wave splitting and multiplexing units, etc. in optical chips, occupying a large chip area. At the same time, the optical link loss is large, which is detrimental to the signal-to-noise ratio, power consumption, and computing accuracy. Summary of the Invention

[0004] The purpose of this invention is to provide a computing device, computing array, and computing system to solve the technical problems mentioned in the background art, such as the large light loss in optical chips, the need for large power consumption, and the occupation of a large chip area.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a computing device, comprising: an input port, an optical power distribution component, programmable switches, an integrating capacitor, an accumulation activation unit, and a tail quantization unit. The input port is used to receive an input optical signal. The optical signal is distributed by the optical power distribution component according to a binary weight ratio. The optical signal is distributed to a plurality of photodetectors for detection. The power ratio of the optical signal received by each photodetector is 1 / 2 to the power of N, where N is the number of photodetectors plus one. A plurality of programmable switches are provided, one end of which is connected to a photodetector. The integrating capacitor is connected between a common node or a reference potential of the programmable switches. The accumulation activation unit includes a voltage comparator and a state register. The register and voltage comparator compare the voltage on the integrating capacitor with the reference voltage. When the voltage on the integrating capacitor is greater than the reference voltage, the accumulation activation unit generates an excitation signal to increment the state value of the state register by 1. At the same time, the integrating capacitor is disconnected from the common node and grounded to release the charge accumulated in the integrating capacitor. Then it is reconnected to the common node to start accumulating charge again until the voltage on the integrating capacitor exceeds the reference voltage again. After the integration time, the tail quantization unit will have several counts on the accumulation circuit, while there is still some charge accumulated on the integrating capacitor. The voltage corresponding to this charge is quantized by the analog-to-digital converter circuit to form the tail number. Together with the counter of the accumulation activation circuit, it constitutes the complete current time-domain integral quantization digital result.

[0006] Preferably, the integrating capacitor and the common node are disconnected and grounded to release the charge accumulated in the integrating capacitor. The common node is then switched to another integrating capacitor of the same specification but not charged, and charge accumulation continues until the voltage of the integrating capacitor exceeds the reference voltage. Then, the common node is disconnected from it and reconnected to the integrating capacitor that has completed charge release. If the voltage generated by the accumulated charge is still less than the reference voltage when the integrating capacitor is larger than the integration time, then only the tail quantization circuit part can be used.

[0007] Preferably, the photocurrent flowing into the integrating capacitor is determined by the product of the intensity of the input optical signal at that moment and the weight corresponding to the binary number of the programmable switch: I(t) = G multiplied by A(t) multiplied by W(t) / 2 to the power of N, where G is the detector responsivity, which is a constant.

[0008] Preferably, the time-domain integration circuit for the photocurrent is in single-ended mode or differential mode. In single-ended mode, when the programmable switch is turned on, the photocurrent of the connected photodetector flows into the integrating capacitor; when the programmable switch is reset, the photocurrent of the connected photodetector flows into ground. In differential mode, when the programmable switch is turned on, the photocurrent of the connected photodetector flows into the integrating capacitor; when the programmable switch is reset, the photocurrent of the connected photodetector flows into another identical integrating capacitor.

[0009] Preferably, the optical power distribution component is a waveguide-cascaded power divider integrated in the optical chip or implemented in free space through a group of photoelectric conversion units with different light-receiving areas. Under uniform illumination, the optical power received by each photoelectric conversion unit is proportional to the light-receiving area.

[0010] Preferably, the optical signal is generated by a light source that is directly modulated or externally modulated; The light source is a DFB laser, VCSEL, SLD, LED, or microLED, which generates the input optical signal through direct modulation. Alternatively, the input optical signal can be generated by externally modulating the light source. The modulator can be one of the following: a silicon-based Mach-Jendl interferometer modulator, Michelson interferometer modulator, micro-ring modulator, photonic crystal modulator, electro-absorption modulator, lithium niobate modulator, lithium tantalate modulator, or barium titanate modulator. The programmable switch is a MOSFET, BJT transistor, or a switching circuit composed of multiple integrated circuit elements using semiconductor technology. The detector uses a PN junction photodiode, PIN photodiode, or avalanche photodiode, which can operate in reverse bias in photoconductive mode or in zero bias in photovoltaic mode.

[0011] Preferably, the computing device constitutes a vector dot product computing unit, and m multiplied by n computing units form an m-row n-column computing array for matrix-matrix multiplication or matrix-vector multiplication calculations; For matrix-matrix multiplication: The programmable switches of the same bit in the same row of computing units on the computing array are connected to the same input port, and all computing units in the same column of the computing array receive the same input optical signal sequence; after clock current integration, the output results of each computing unit form an m x n matrix, M, which corresponds to the product of an m x k ​​matrix A and a k x n matrix B, i.e., M = AB. For matrix-vector multiplication: Any one of the m x n computing units, where each bit of the programmable switch is written with a different digital signal, and all units receive the same input optical signal, after clock current integration, the output results of each computing unit can form an m x n x k matrix A and a k x 1 vector b, i.e., M = Ab.

[0012] Preferably, the computing array constitutes a computing module, and p by q computing modules are combined into a computing system to process matrix A of size pm by k and matrix-matrix multiplication of size k by qn or matrix multiplication of size pmqn by k and vector multiplication of size k by 1; the collaboration between computing modules is solidified into a matrix computing accelerator in the form of a pulsating array, and they are interconnected and collaboratively perform computing tasks through on-chip or inter-chip communication networks.

[0013] Preferably, the computing system integrates unit devices onto the same chip or wafer through monolithic integration, or combines multiple different functional device units or chips into a complete system through heterogeneous integration. The computing system is used for artificial neural network computing acceleration, gene sequencing, large-scale scientific computing, blockchain analysis, autonomous driving, and various scenarios involving matrix calculations.

[0014] Preferably, the input port receives multiple optical signals with a wavelength range of 300nm-2000nm. The optical power distribution component splits each input optical signal into N branch signals (N≥8) according to a weighted ratio. The weights are implemented by a programmable switch array, which contains M×N electro-optic modulation units (M≥32). The branch signal paths are dynamically selected according to the control signal. The integrating capacitor array contains M capacitor units, which receive the electrical signal converted from the selected optical signal and accumulate charge. The accumulation activation unit compares the capacitor voltage with a reference voltage and performs accumulation counting to form the integer part of the integration result. The tail quantization conversion circuit converts the tail quantization result into the final product. The activation output is separated into integer and mantissa bits, with the mantissa bits obtained through analog-to-digital converter quantization. This computing device uses an optical domain parallel weighting and electrical domain precision compensation architecture to solve the bandwidth bottleneck of large-scale matrix computation through optical distribution components. The accumulation activation and mantissa quantization circuits innovatively transform the single-step high-speed, high-precision data quantization in traditional optical computing schemes into multi-step low-speed, medium-low-precision data quantization and concatenation of integer and mantissa bits, reducing the size of analog circuits while retaining high precision. The collaborative design of programmable switches and integrating capacitors supports dynamic reconstruction of computing modes, which is suitable for the variable topology requirements of convolutional and recurrent neural networks.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention uses an input optical signal and an optical power distribution component to divide the input optical signal into components with different relative intensities of 1:1:2:4…2. N-1 The photocurrent is divided into N+1 parts and converted into photocurrent by the corresponding photodetectors. The photocurrents from multiple detectors through the power distribution device are combined into an integrating capacitor through a set of programmable switches, which charges the capacitor to generate voltage. When the voltage is greater than the reference voltage Vref, the status register of the accumulating activation unit is incremented by 1. At the same time, the integrating capacitor is grounded to release the accumulated charge, and the voltage returns to 0. Then the integrating capacitor continues to receive the photocurrent to charge it to generate voltage until it is higher than the reference voltage again. This realizes the accumulating activation unit scheme, which is simple and reduces energy loss. 2. This invention eliminates dead time by employing a dual-capacitor alternating working mode through an accumulation activation unit. It includes two identical integrating capacitors C1 and C2, and a switching switch controlled by control logic. In the initial state, the switch connects node P to capacitor C1. When the voltage on C1 exceeds Vref, the control logic increments the counter by 1 and simultaneously controls the switching switch to connect node P to the fully discharged capacitor C2. At the same time, an independent discharge switch discharges capacitor C1 to ground. This cycle repeats continuously, with node P always connected to a charging capacitor, achieving seamless integration of photocurrent and improving measurement accuracy and efficiency. 3. This invention uses a beam of expanded parallel light to uniformly illuminate a detector array composed of N+1 photodiodes. The photosensitive areas of the photodiodes are arranged in a ratio of 1:1:2:4:...:2. N-1 Under uniform illumination, the light power received by each detector is proportional to its photosensitive area, thus realizing the required binary weighted light power allocation. When the illumination is uneven, the same effect can be achieved by adjusting the ratio of the product of the effective photosensitive area of ​​each detector at its position and the local light power density. 4. This invention dynamically selects branch signal paths based on control signals. The integrating capacitor array contains M capacitor units, which receive the electrical signal converted from the selected optical signal and accumulate charge. The accumulation activation unit compares the capacitor voltage with the reference voltage and accumulates the integer part of the integral result. The tail quantization conversion circuit separates the activation output into integer bits and tail bits. The tail bits are obtained by quantization through an analog-to-digital converter. This computing device solves the bandwidth bottleneck of large-scale matrix calculation by using a parallel weighted optical domain and an electrical domain precision compensation architecture. The accumulation activation and tail quantization circuits innovatively transform the single-step high-speed, high-precision data quantization in traditional optical computing schemes into multi-step low-speed, medium-low-precision data quantization and concatenation of integer and tail bits. While retaining high precision, the scale of the analog circuit is reduced. The collaborative design of the programmable switch and the integrating capacitor supports dynamic reconstruction of the computing mode, which is suitable for the variable topology requirements of convolutional and recurrent neural networks. Attached Figure Description

[0016] Figure 1 This is a schematic block diagram of the computing device of the present invention; Figure 2 This is a schematic diagram of two types of cumulative activation units of the present invention; Figure 3 These are schematic diagrams of two power distribution units of the present invention; Figure 4 This is a schematic diagram of the computing array of the present invention; Figure 5 This is a schematic diagram of matrix multiplication calculation according to the present invention; Figure 6This is a schematic diagram of the vector multiplication calculation of the present invention; Figure 7 This is a schematic diagram of the vector multiplication calculation of the present invention; Figure 8 This is a schematic diagram of the computing system of the present invention; Figure 9 This is a schematic diagram of a large-size matrix in the outer product form of the present invention; Figure 10 This is a schematic diagram of a large-size matrix in the form of a pulsating array according to the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand this according to the specific circumstances.

[0019] Example 1: Please refer to Figure 1 A computing device includes an input optical signal, wherein an optical power distribution component divides the input optical signal into components with different relative intensities of 1:1:2:4…2. N-1The N+1 portions of the photocurrent are converted into photocurrent by the corresponding photodetectors. The photocurrents from multiple detectors in the power distribution device are combined through a set of programmable switches and flow into an integrating capacitor to charge it and generate voltage. When the voltage is greater than the reference voltage Vref, the state register of the accumulating activation unit increments by 1, while the integrating capacitor is grounded to release the accumulated charge, and the voltage returns to 0. Subsequently, the integrating capacitor continues to receive photocurrent to charge it and generate voltage until it is higher than the reference voltage again, generating an activation output. After an integration period T, the state register of the accumulating activation unit generates a certain count m. This count n indicates that more than m*C*Vref of charge has flowed into the integrating capacitor during this period T. The charge exceeding m*C*Vref but less than (m+1)*C*Vref is quantized and output as q through the tail quantization unit. During this integration period T, the input optical signal changes with time as A(t). The programmable switches correspond to a set of rapidly changing binary signals. The binary number W(t) corresponding to this signal corresponds to the different degrees of attenuation of the optical signal at different times. Therefore, the total charge accumulated on the integrating capacitor is essentially the same as the input optical signal. The sum of the counts m and q of the accumulator activation unit is proportional to (t=0, T / n, 2T / n……T), and is considered as the inner product of two n-dimensional vectors A(t) and W(t). This is reflected in the sum m+q of the count m of the accumulator activation unit and the output q of the tail quantizer unit, thus simplifying the accumulator activation unit scheme and reducing energy loss.

[0020] Example 2: Please refer to Figure 2 A computing device is described, in which the accumulation activation unit employs a dual-capacitor alternating operating mode to eliminate dead time. It includes two identical integrating capacitors C1 and C2, and a switching switch controlled by control logic. Initially, the switch connects node P to capacitor C1. When the voltage on C1 exceeds Vref, the control logic increments a counter by 1 and simultaneously controls the switching switch to connect node P to the fully discharged capacitor C2. At the same time, an independent discharge switch grounds capacitor C1. This cycle repeats continuously, ensuring node P is always connected to a charging capacitor, achieving seamless integration of photocurrent and improving measurement accuracy and efficiency.

[0021] Example 3: Please refer to Figure 3 A computing device, wherein the power distribution device is implemented by an N-stage 1x2 power divider cascaded in an integrated optical chip; wherein the first-stage 1x2 power divider has a single input port connected to an input optical signal, and two output ports with the same output power, one of which is connected to a waveguide-coupled photodetector D1, and the other is coupled to the input port of the next-stage 1x2 power divider. The two output ports of this power divider are connected, one to a photodetector D2 and the other to the input port of the next-stage 1x2 power divider, and so on, until the two output ports of the last stage are each connected to a photodetector D1.N and D N+1 At this point, the ratio of the optical power received by these detectors is 2. N-1 ...4:2:1:1; A beam of expanded parallel light is uniformly incident on a detector array consisting of N+1 photodiodes. The photosensitive areas of the diodes are arranged in a ratio of 1:1:2:4:...:2. N-1 Under uniform illumination, the optical power received by each detector is proportional to its photosensitive area, achieving the required binary weighted optical power allocation. Under non-uniform illumination, the same effect is achieved by adjusting the ratio of the effective photosensitive area of ​​each detector at its position to the product of the local optical power density. When the integrating capacitor is large enough that the voltage generated by charge integration within the time interval from 0 to T does not exceed Vref, the result is directly output using the tail quantization unit. For a given detector responsivity, when the photodetector converts the optical signal into current, the output photocurrent of each detector is proportional to the received optical power. The programmable switch is one or more of the following: MOS transistor, BJT transistor, or a switching circuit composed of multiple circuit elements that can be integrated by semiconductor technology.

[0022] Example 4, please refer to Figure 4 and Figure 5 A computing array, comprising m×n computing units or processing units as described above, arranged in rows and columns to form a computing core. A global control module provides control signals, which are weight data W, to each programmable switch in the array and coordinates the timing of the entire array. An input light generation module generates a timing optical signal carrying the input data A(t) and distributes it to each column of the array through an optical distribution network. Each computing unit independently performs a dot product operation between its input optical signal and the weight vector. Finally, the results of all units are synchronously read out from the output interface, forming a complete output matrix or vector. The computing array performs matrix-matrix multiplication (M= The operation mechanism of AB involves multiplying matrices A (dimension m×k) and B (dimension k×n). During the operation, matrix B is pre-loaded into the computing array: specifically, the data in the j-th column of matrix B is loaded onto the programmable switches of all units in the j-th column of the computing array. Over the next k clock cycles, the data from the 1st to the k-th rows of matrix A are sequentially converted into light intensity signals and broadcast to the entire array via the optical distribution network. Each computing unit in each column performs a dot product with the column vector of matrix B loaded into that column. After k cycles of accumulation, the output of the computing unit in the i-th row and j-th column is precisely the dot product of the i-th row of matrix A and the j-th column of matrix B, i.e., the element M of the resulting matrix M. ij Finally, the output of the entire array is the matrix product M=AB.

[0023] Example 5, please refer to Figure 4 , Figure 6 and Figure 7 A computing array performs matrix-vector multiplication (M=Ab) using a matrix A (dimension p×k, where p=m×n) and vector b (dimension k×1) to be computed. All row vectors of the large matrix A are loaded into m×n computing units. Each unit's programmable switch stores one row of matrix A data. The k elements of vector b are sequentially converted into light intensity signals over k clock cycles and broadcast to all computing units in the array. Each unit performs a dot product operation between the received light signal sequence vector b and one row of its stored weight vector matrix A. After k cycles, the output of each unit is the dot product of a row of matrix A and vector b. Arranging the outputs of all units in order yields the final result vector M=Ab.

[0024] Example 6, please refer to Figure 8 , Figure 9 and Figure 10 A computing system, which consists of multiple such Figure 4 The computing modules shown are combined through an inter-chip interconnect network, which allows the system to be flexibly expanded to handle ultra-large-scale matrix operations. The control processor is responsible for task decomposition and scheduling, dividing the huge computing task into multiple sub-tasks and distributing them to each computing module for parallel processing through the interconnect network. The computing modules can communicate and cooperate with each other using efficient data flow architectures such as systolic arrays or based on on-chip networks. Finally, the computing results of each module are aggregated to obtain the final result.

[0025] Example 7, please refer to Figure 4 , Figure 8 and Figure 10 A calculation method, applicable to any of the aforementioned computing devices, computing arrays, or computing systems, comprising the following steps: Step 1: Receive the input optical signal, the intensity of which varies over time to carry the input data; Step 2: Distribute the input optical signal according to a specific binary weight ratio to generate multiple optical signals with different weights; Step 3: Convert each optical signal into a corresponding photocurrent; Step 4: Based on the digital weights to be loaded, select which photocurrents to connect to the integrating circuit using a programmable switch; Step 5: Integrate the incoming photocurrent in the time domain to generate a corresponding voltage across the integrating capacitor; Step 6: Determine if the integrated voltage exceeds the reference threshold. If it does, increment the counter and reset the integrating capacitor; if it does not exceed the threshold, continue integrating. Step 7: After the predetermined integration time has elapsed, perform analog-to-digital conversion on the remaining voltage tails on the integrating capacitor; Step 8: Combine the integer part of the counter with the quantized result of the mantissa to output the final numerical result, which represents the dot product of the input data vector and the weight vector.

[0026] Example 8 illustrates an application scenario for a computing system. The computing system can function as a coprocessor or accelerator card, connected to the host CPU via a high-speed bus (PCIe). The host CPU runs the main application, which includes tasks such as artificial intelligence inference, scientific computing simulation, gene sequence analysis, blockchain hash calculation, and autonomous driving environmental perception. When encountering large-scale matrix operation tasks, the tasks are offloaded to the computing system for high-speed parallel processing. After processing, the results are returned to the host CPU, thereby improving the overall computing efficiency of the system in specific application scenarios.

[0027] Example 9, please refer to Figure 1 and Figure 2 A computing device includes an input port for receiving multiple optical signals with a wavelength range of 300nm-2000nm. An optical power distribution component divides each input optical signal into N branch signals (N≥8) according to a weighted ratio. The weights are implemented by a programmable switch array, which contains M×N electro-optic modulation units (M≥32) that dynamically select branch signal paths based on control signals. An integrating capacitor array contains M capacitor units that receive the electrical signal converted from the selected optical signal and accumulate charge. An accumulation activation unit compares the capacitor voltage with a reference voltage and performs accumulation counting to form the integer part of the integration result. The tail is quantized and converted into an electrical signal. The circuit separates the activation output into integer and mantissa bits, with the mantissa bits obtained through analog-to-digital converter quantization. This computing device solves the bandwidth bottleneck of large-scale matrix computation by implementing an optical domain parallel weighting and electrical domain precision compensation architecture. The accumulation activation and mantissa quantization circuits innovatively transform the single-step high-speed, high-precision data quantization in traditional optical computing schemes into multi-step low-speed, low-precision data quantization and concatenation of integer and mantissa bits, reducing the size of analog circuits while retaining high precision. The collaborative design of programmable switches and integrating capacitors supports dynamic reconstruction of the computing mode, which is suitable for the variable topology requirements of convolutional and recurrent neural networks.

[0028] In terms of manufacturing, the computing devices, arrays, and systems disclosed herein can be fabricated on the same silicon-based or other semiconductor substrate using monolithic integration processes to form highly integrated system-on-a-chip (SoC). The optical components are waveguides, beam splitters, and modulators, while the electronic components are detectors, transistors, capacitors, and comparators. Alternatively, heterogeneous integration technology can be used to package and interconnect separately fabricated photonic chips, detector chips, and CMOS logic chips at high density using technologies such as three-dimensional stacking, through-silicon vias, or microbumps, so as to fully leverage the advantages of different process platforms.

[0029] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A computing device, characterized in that, include: The system comprises an input port, an optical power distribution component, programmable switches, an integrating capacitor, an accumulation activation unit, and a tail quantization unit. The input port receives an input optical signal, which is distributed by the optical power distribution component according to a binary weight ratio. The optical signal is then distributed to several photodetectors for detection. The power ratio of the optical signal received by each photodetector is 1 / 2 to the power of N, where N is the number of photodetectors plus one. Several programmable switches are provided, with one end connected to a photodetector. The integrating capacitor is connected between a common node or a reference potential of the programmable switches. The accumulation activation unit includes a voltage comparator and a status register. The voltage comparator compares the voltage on the integrating capacitor with the reference voltage. After the integration time, the tail quantization unit accumulates several counts on the accumulation circuit. The voltage corresponding to the partially accumulated charge on the integrating capacitor is quantized by an analog-to-digital converter to form a tail number, which, together with the counter of the accumulation activation circuit, constitutes a complete current time-domain integrated quantized digital value.

2. A computing device according to claim 1, characterized in that: The integrating capacitor and the common node are disconnected and grounded to release the charge accumulated in the integrating capacitor. The common node switches to connect to another integrating capacitor of the same specification but not charged, and continues to accumulate charge until the voltage of the integrating capacitor exceeds the reference voltage. Then the common node disconnects from it and reconnects to the integrating capacitor that has completed the charge release. When the integrating capacitor is longer than the integration time, the voltage generated by the accumulated charge is still less than the reference voltage, so the tail quantization circuit section is used.

3. A computing device according to claim 1, characterized in that: The photocurrent flowing into the integrating capacitor is determined by the product of the intensity of the input optical signal at that moment and the weight corresponding to the binary number of the programmable switch: I(t) = G multiplied by A(t) multiplied by W(t) / 2 to the power of N, where G is the detector responsivity, which is a constant.

4. A computing device according to claim 3, characterized in that: The time-domain integration circuit for the photocurrent is either single-ended or differential. In single-ended mode, when the programmable switch is turned on, the photocurrent of the connected photodetector flows into the integrating capacitor; when the programmable switch is reset, the photocurrent of the connected photodetector flows into ground. In differential mode, when the programmable switch is turned on, the photocurrent of the connected photodetector flows into the integrating capacitor; when the programmable switch is reset, the photocurrent of the connected photodetector flows into another identical integrating capacitor.

5. A computing device according to claim 4, characterized in that: The optical power distribution component is a power divider cascaded in the waveguide of the integrated optical chip or implemented in free space through a group of photoelectric conversion units with different light-receiving areas. Under uniform illumination, the optical power received by each photoelectric conversion unit is proportional to the light-receiving area.

6. A computing device according to claim 1, characterized in that: The optical signal is generated by a light source that is directly modulated or externally modulated; The light source is a DFB laser, VCSEL, SLD, LED, or microLED, which generates the input optical signal through direct modulation. Alternatively, the input optical signal can be generated by externally modulating the light source. The modulator can be one of the following: a silicon-based Mach-Jendl interferometer modulator, Michelson interferometer modulator, micro-ring modulator, photonic crystal modulator, electro-absorption modulator, lithium niobate modulator, lithium tantalate modulator, or barium titanate modulator. The programmable switch is a MOSFET, BJT transistor, or a switching circuit composed of multiple integrated circuit elements using semiconductor technology. The detector uses a PN junction photodiode, PIN photodiode, or avalanche photodiode, which can operate in reverse bias in photoconductive mode or in zero bias in photovoltaic mode.

7. A computing array, applicable to a computing device according to any one of claims 1-4, characterized in that: The computing device constitutes a vector dot product computing unit, and m multiplied by n computing units form an m-row n-column computing array for matrix-matrix multiplication or matrix-vector multiplication calculations. For matrix-matrix multiplication: The programmable switches of the same bit in the same row of computing units on the computing array are connected to the same input port, and all computing units in the same column of the computing array receive the same input optical signal sequence; after clock current integration, the output results of each computing unit form an m x n matrix, M, which corresponds to the product of an m x k ​​matrix A and a k x n matrix B, i.e., M = AB. For matrix-vector multiplication: Any one of the m x n computing units, where each bit of the programmable switch is written with a different digital signal, and all units receive the same input optical signal, after clock current integration, the output results of each computing unit can form an m x n x k matrix A and a k x 1 vector b, i.e., M = Ab.

8. A computing system, applicable to the computing array of claim 7, characterized in that: The computing array constitutes a computing module. p x q computing modules are combined to form a computing system for processing matrix A of size pm x k ​​and matrix-matrix multiplication of size k x qn, or matrix multiplication of size pmqn x k and vector multiplication of size k x 1. The collaboration between computing modules is solidified into a matrix computing accelerator by means of a pulsating array, and they are interconnected through on-chip or inter-chip communication networks to perform computing tasks collaboratively.

9. A computing system according to claim 8, characterized in that: The computing system integrates unit devices onto the same chip or wafer through monolithic integration, or combines multiple different functional device units or chips into a complete system through heterogeneous integration. The computing system is used in various scenarios involving matrix calculations, such as artificial neural network computing acceleration, gene sequencing, large-scale scientific computing, blockchain analysis, and autonomous driving.

10. A computing device according to claim 1, characterized in that, The input port receives multiple optical signals with a wavelength range of 300nm-2000nm. The optical power distribution component splits each input optical signal into N branch signals (N≥8) according to a weight ratio. The weights are implemented by a programmable switch array, which contains M×N electro-optic modulation units (M≥32). The branch signal path is dynamically selected according to the control signal. The integrating capacitor array contains M capacitor units, which receive the electrical signal after conversion of the selected optical signal and accumulate charge. The accumulation activation unit compares the capacitor voltage with the reference voltage and accumulates the integer part of the integral result. The tail quantization conversion circuit separates the activation output into integer bits and tail bits. The tail bits are obtained by quantization through an analog-to-digital converter. The final calculation result is obtained by concatenating the integer bits and tail bits.

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