System and method for measuring latency of interconnect lines

Abstract

The invention provides a system for measuring the time delay of an interconnection line. The system comprises the interconnection line, a first FPGA and a second FPGA. The first FPGA is configured to send a message to the second FPGA via the interconnect line at a first instant of an edge trigger. The second FPGA is configured to receive the message, determine a counter value during receiving and delay the message until a second moment of edge triggering, and the counter value corresponding to the second moment of edge triggering is the sum of the counter value during receiving and a preset integer value. And the second FPGA determines the time delay of the interconnection line based on the counter value corresponding to the first moment of edge triggering, the counter value during receiving, the delay time of the message by the second FPGA, the preset integer value and the time interval of the adjacent counter values. Through the cooperation of the digital logic function in the FPGA and the delay unit, the delay of the interconnection line can be accurately measured.

Description

Technical Field

[0001] This disclosure relates to the field of data communication technology, and more specifically to a system for measuring the delay of interconnect lines and a method for measuring the delay of interconnect lines. Background Technology

[0002] Prototype verification, as a crucial step in the chip verification process, has been widely and significantly applied in the field of chip verification due to its advantage of enabling early verification of chip designs, discovery of design defects, and optimization of performance under conditions close to the actual operating environment of real chips. However, during the actual use of prototype equipment, some problems have gradually emerged, among which issues related to FPGA (Field-Programmable Gate Array) interconnects have significantly impacted the accuracy and reliability of prototype verification.

[0003] On the one hand, as prototype devices are used for extended periods, the internal interconnect structures are prone to aging and wear, leading to unreliable internal interconnects. This unreliability directly impacts the transmission of signals across the FPGA, causing instability. During cross-FPGA signal transmission, delay is a crucial indicator of the physical state of the interconnect lines. When the internal interconnects are unreliable, measurable abnormal fluctuations in signal delay will occur. These abnormal fluctuations can interfere with the accurate assessment of chip performance parameters during prototype verification, potentially leading to biased performance evaluations of the chip design by researchers.

[0004] On the other hand, during the construction and expansion of prototype verification systems, it is often necessary to add new cross-FPGA interconnects to meet system functional requirements. However, the delay values ​​of these newly added cross-FPGA interconnects are often unknown. When performing system timing analysis, the delay value of the cross-FPGA interconnects is an indispensable key parameter. Only by knowing this delay value can accurate system timing analysis be performed, and thus the frequency at which the system can operate stably be calculated. If the delay value of the newly added cross-FPGA interconnects cannot be obtained, system timing analysis cannot be carried out normally, resulting in the inability to determine the frequency range in which the system can operate stably.

[0005] To address the aforementioned issues, technicians typically measure the difference between the timestamps of the transmitting and receiving sides to obtain the delay value across FPGA interconnects. Specifically, the transmitting side uses its current counter value, which changes with the clock, as its timestamp and records it in the transmitted data packet. Once the receiving side receives the data packet, it uses its receiving counter value as its timestamp and subtracts it from the transmitting side's timestamp to obtain the delay of that FPGA interconnect. However, this existing method for measuring delay across FPGA interconnects has a significant drawback: poor measurement accuracy. The accuracy of the delay value obtained by this method is only at the nanosecond (ns) level, which cannot meet the increasingly demanding requirements for delay measurement accuracy in current chip verification. With the continuous development of chip technology and the increasing operating frequency of chips, it is necessary to develop a more accurate method for measuring delay across FPGA interconnects. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this disclosure provides a system and method for measuring the delay of interconnect lines. By using the measurement system or method of this disclosure, the delay of interconnect lines can be measured more accurately, for example, achieving a measurement accuracy at the picosecond (ps) level.

[0007] A first aspect of this disclosure provides a system for measuring the delay of an interconnect line, the system including the interconnect line, a first FPGA, and a second FPGA. One end of the interconnect line is located on the first FPGA, and the other end of the interconnect line is located on the second FPGA. The first FPGA is configured to send a message via the interconnect line to the second FPGA at a first edge-triggered moment. A counter of the second FPGA is synchronized with a counter of the first FPGA and is configured to: receive the message and determine a counter value at the time of reception; delay the message until a second edge-triggered moment, the counter value corresponding to the second edge-triggered moment being the sum of the counter value at the time of reception and a predetermined integer value; and determine the delay of the interconnect line based on: the counter value corresponding to the first edge-triggered moment, the counter value at the time of reception, the delay time of the message by the second FPGA, the predetermined integer value, and the time interval between adjacent counter values.

[0008] In this measurement system, the first FPGA sends a message at the edge-triggered moment, and the message is then transmitted to the second FPGA via interconnect lines. The second FPGA, upon receiving the message, delays it until another edge-triggered moment. Through the internal digital logic functions of the FPGAs, combined with the delay unit, the delay of the interconnect lines can be accurately measured.

[0009] In one embodiment, the first FPGA and the second FPGA are the same FPGA.

[0010] In one embodiment, the counter value corresponding to the first moment of edge triggering is obtained by the second FPGA processing the message.

[0011] In one embodiment, the message includes a counter value corresponding to the first moment of the edge triggering.

[0012] In one embodiment, the second FPGA includes a delay unit that delays the message in increments of a delay interval, the delay interval being less than the time interval between adjacent counter values.

[0013] In one embodiment, the delay time of the message by the second FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

[0014] A second aspect of this disclosure provides a method for measuring the delay of an interconnect line, wherein one end of the interconnect line is located on a first FPGA and the other end of the interconnect line is located on a second FPGA, and the counters of the first FPGA and the second FPGA are synchronized. The method includes: the first FPGA sending a message via the interconnect line to the second FPGA at a first edge-triggered moment; the second FPGA receiving the message and determining a counter value at the time of reception; the second FPGA delaying the message until a second edge-triggered moment, the counter value corresponding to the second edge-triggered moment being the sum of the counter value at the time of reception and a predetermined integer value; and determining the delay of the interconnect line based on: the counter value corresponding to the first edge-triggered moment, the counter value at the time of reception, the delay time of the message by the second FPGA, the predetermined integer value, and the time interval between adjacent counter values.

[0015] In one embodiment, the first FPGA and the second FPGA are the same FPGA.

[0016] In one embodiment, the second FPGA determines the delay of the interconnect line, and the counter value corresponding to the first moment of the edge triggering is obtained by the second FPGA processing the message.

[0017] In one embodiment, the message includes a counter value corresponding to the first moment of the edge triggering.

[0018] In one embodiment, the second FPGA includes a delay unit that delays the message in increments of a delay interval, the delay interval being less than the time interval between adjacent counter values.

[0019] In one embodiment, the delay time of the message by the second FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

[0020] A third aspect of this disclosure provides a system for measuring the delay of an interconnect line, the system including the interconnect line, a first FPGA, and a second chip. One end of the interconnect line is located on the first FPGA, and the other end of the interconnect line is located on the second chip. The first FPGA has a counter configured to: send a message via the interconnect line to the second chip at a first edge-triggered moment; receive the message returned from the second chip and determine the counter value at the time of reception; delay the message until a second edge-triggered moment, the counter value corresponding to the second edge-triggered moment being the sum of the counter value at the time of reception and a predetermined integer value; and determine the delay of the interconnect line based on: the counter value corresponding to the first edge-triggered moment, the counter value at the time of reception, the delay time of the message by the first FPGA, the predetermined integer value, and the time interval between adjacent counter values. The second chip is configured to immediately return the message to the first FPGA via the interconnect line after receiving the message.

[0021] In one embodiment, the first FPGA includes a delay unit that delays the message in increments of a delay interval, the delay interval being less than the time interval between adjacent counter values.

[0022] In one embodiment, the delay time of the message by the first FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

[0023] A fourth aspect of this disclosure provides a method for measuring the delay of an interconnect line, one end of which is located on a first FPGA and the other end on a second chip, the first FPGA having a counter. The method includes: the first FPGA sending a message via the interconnect line to the second chip at a first edge-triggered moment; the second chip immediately transmitting the message back to the first FPGA via the interconnect line; the first FPGA receiving the transmitted message and determining a counter value at the time of reception; the first FPGA delaying the message until a second edge-triggered moment, the counter value corresponding to the second edge-triggered moment being the sum of the counter value at the time of reception and a predetermined integer value; and determining the delay of the interconnect line based on: the counter value corresponding to the first edge-triggered moment, the counter value at the time of reception, the delay time of the message by the first FPGA, the predetermined integer value, and the time interval between adjacent counter values.

[0024] In one embodiment, the first FPGA includes a delay unit that delays the message in increments of a delay interval, the delay interval being less than the time interval between adjacent counter values.

[0025] In one embodiment, the delay time of the message by the first FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself. Attached Figure Description

[0026] Other features and advantages of the invention will be better understood through the following detailed description of preferred embodiments in conjunction with the accompanying drawings, wherein the same reference numerals denote the same or similar parts.

[0027] Figure 1 A schematic diagram of a system according to a first embodiment of the present disclosure is shown.

[0028] Figure 2 An example message flow for measuring the latency of interconnect lines is shown in the first embodiment.

[0029] Figure 3 A timing diagram corresponding to the sending and receiving of messages in the first embodiment is shown.

[0030] Figure 4 A system according to a second embodiment of the present disclosure is shown, which is also used to measure the delay of interconnect lines.

[0031] Figure 5 A flowchart of a delay measurement method for interconnect lines according to an embodiment of the present disclosure is shown.

[0032] Figure 6A schematic diagram of a system according to a third embodiment of the present disclosure is shown.

[0033] Figure 7 An example message flow is shown in the third embodiment for measuring the latency of interconnect lines.

[0034] Figure 8 The timing diagram corresponding to the sending and receiving of messages in the third embodiment is shown.

[0035] Figure 9 A flowchart of a delay measurement method for interconnect lines according to an embodiment of the present disclosure is shown. Detailed Implementation

[0036] The technical solutions of this disclosure will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of this disclosure and should not be construed as a limitation thereof.

[0037] The terms “comprising,” “including,” and similar terms as used in this disclosure should be understood as open-ended terms, meaning “including / including but not limited to,” implying that other content may also be included. The term “based on” means “at least partially based on.” The term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one additional embodiment,” and so on.

[0038] This disclosure proposes a system for measuring the time delay of interconnect lines. Figure 1 A schematic diagram of a system according to a first embodiment of this disclosure is shown. The system includes a first FPGA, a second FPGA, and an interconnect line 100. One end of the interconnect line 100 is located on the first FPGA, and the other end is located on the second FPGA. An FPGA is a hardware platform that can be reconfigured to implement different functions. Its core advantage lies in its ability to dynamically adjust the hardware structure according to requirements, thereby realizing different chip functions. In other words, engineers can customize the internal circuit logic of the FPGA in the field (i.e., in a laboratory or in the field of use) through programming. The counter of the first FPGA is synchronized with the counter of the second FPGA.

[0039] Figure 2 An example message flow for measuring the latency of interconnect lines is shown in the first embodiment. Figure 3A timing diagram corresponding to message transmission and reception in the first embodiment is shown. In this system, a first FPGA is configured to transmit a message via an interconnect to a second FPGA at a first edge-triggered moment. The second FPGA is configured to receive the message and determine the counter value at that time. Further, the second FPGA delays the message until a second edge-triggered moment, where the counter value corresponding to the second edge-triggered moment is the sum of the counter value at reception and a predetermined integer value. Through the above operations, the interconnect delay can be determined based on the counter value corresponding to the first edge-triggered moment, the counter value at reception, the delay time of the second FPGA for the message, the predetermined integer value, and the time interval between adjacent counter values.

[0040] The counters of the first FPGA and the second FPGA are synchronized. Figure 3 The clock timing diagram and counter output timing diagram illustrate the clock signal synchronization between the first and second FPGAs and the changes in the counter values. Ensuring clock synchronization between the first and second FPGAs is fundamental to counter synchronization. Both FPGAs have internal counters. In one example, the system can send synchronization pulse signals to both FPGAs simultaneously, causing their counters to begin counting in the same clock cycle. Driven by the same clock, the counters on both FPGAs increment continuously and output their current counter values. Based on these measures, the counter values ​​of the two FPGAs are synchronized and can therefore be compared.

[0041] refer to Figure 2 and Figure 3 The first FPGA is configured to send a message via an interconnect to the second FPGA at the first moment of edge triggering 110. For example Figure 3 As shown, the message is sent from the output pin of the first FPGA at the rising edge of the clock at time 110. This operation can be implemented using a non-blocking assignment statement. Of course, in other examples, the edge triggering time could also be the falling edge of the clock, but since this case is not suitable for the timing operation described in this embodiment, it will not be elaborated on here. At the first edge triggering time 110, refer to... Figure 3 The first FPGA's counter outputs a value of 1. It needs to be explained that... Figure 3 In the timing diagram shown, the time period with a counter value of 0 in the timing area covered by a lighter gray shading corresponds to the interval from the first rising edge of the clock to the second rising edge of the clock; the time period with a counter value of 1 in the timing area covered by a darker gray shading corresponds to the interval from the second rising edge of the clock to the third rising edge of the clock, and so on.

[0042] The message sent by the first FPGA can be any meaningful information unit, such as... Figure 3 The example shown is a rising edge signal. In other examples, the message could also be a sequence referred to as a packet or frame. The message could include a counter value corresponding to the first moment of edge triggering. Additionally, the message could also include a destination address (e.g., a second FPGA).

[0043] Subsequently, after the message passes through the interconnect, the second FPGA receives the message and determines the counter value at the time of reception (i.e., time 120), for example, through... Figure 1 The input pins shown are used to receive messages. (See reference.) Figure 3 The second FPGA's counter outputs a value of 4. In fact, depending on the interconnect delay, the second FPGA could receive the message at the 5th rising edge of the clock, or it could be any time between the 5th rising edge and the 6th rising edge. In other words, the second FPGA's output counter value of 4 means that message reception occurs at any time within the time period when the counter value is 4.

[0044] Following this, the second FPGA delays the message until the edge-triggered second time point 130. The counter value corresponding to the edge-triggered second time point 130 is the sum of the counter value at the time of reception and a predetermined integer value. In this embodiment, the predetermined integer value is set to 1. Given that the counter value at the time of reception is 4, the counter value corresponding to the edge-triggered second time point 130 should be 5. (Reference) Figure 3 In other words, the second FPGA delays the message until the 6th rising edge of the clock occurs. Since the exact moment the second FPGA receives the message cannot be determined, we can only determine that the message was received within the time period when the counter value is 4 using the counter value. To more accurately calculate the delay value of the interconnect, it is necessary for the second FPGA to delay the received message until the next edge triggering moment is encountered. Thus, the message is sent at edge triggering moment 110 and delayed to another edge triggering moment 130 after reception. We only need to determine the delay time to accurately calculate the message transmission time in the interconnect. Technically, this can be achieved using a non-blocking assignment statement to determine that the message has been delayed to another edge triggering moment.

[0045] It should be noted that in this embodiment, the predetermined integer value is set to 1, meaning that the second FPGA, after receiving the message, delays it until the most recent edge-triggered moment. Combined with... Figure 3The second FPGA receives the message during the time period when the counter value is 4. The nearest edge trigger time to the reception time is the occurrence of the 6th rising clock edge, and the corresponding counter value at the occurrence of the 6th rising clock edge is 5 (i.e., 4+1=5). In other examples, the predetermined integer value can also be set to 2 or other values. When the predetermined integer value is 2, it means that the second FPGA needs to delay the message until the occurrence of the 7th rising clock edge, and the corresponding counter value at the occurrence of the 7th rising clock edge is 6 (i.e., 4+2=6).

[0046] By knowing the counter value CV1 corresponding to the first edge-triggered moment 110, the counter value CV2 at the receiving moment 120, and the delay time T of the message by the second FPGA, delay The predetermined integer value n and the time interval T between adjacent counter values. cycle This allows us to determine the latency of the interconnection lines. The time interval between adjacent counter values ​​refers to, for example, the time interval between a period when the counter value is 0 and a period when the counter value is 1, which is equal to the clock cycle. Figure 3 The T marked above cycle The delay T of the interconnection line includes T1 and T2, that is: (1) T1 can be calculated using the following formula (2): (2) Furthermore, T2 can be calculated using the following formula (3): (3)

[0047] As mentioned earlier, in one example, the first FPGA packages the counter value corresponding to the first moment of edge triggering into a message. In another example, the counter value corresponding to the first moment of edge triggering can also be a default value, such as 1. In this case, the first FPGA will send a specific message for measuring interconnect delay when the second rising clock edge occurs. In summary, the counter value corresponding to the first moment of edge triggering can be obtained by the second FPGA processing the message.

[0048] Existing technology estimates the latency of interconnect lines solely based on the counter values ​​at the time of transmission and reception. This will be illustrated using a first embodiment. Specifically, the first FPGA transmits a message at time 110 and determines the corresponding counter value to be 1. Subsequently, the second FPGA receives a message at time 120 and determines the corresponding counter value to be 4. Thus, based on the counter value CV1 at the time of message transmission, the counter value CV2 at the time of message reception, and the time of adjacent counter values... Interval T cycleExisting technology estimates the latency of interconnect lines as follows: (4) Obviously, this method of measuring the time delay of interconnect lines has a large error. It can only achieve a measurement accuracy in the nanosecond (ns) range and cannot achieve more precise measurements.

[0049] In the measurement system proposed in this disclosure, the first FPGA sends a message at an edge-triggered moment, and the message is then transmitted to the second FPGA via interconnects. The second FPGA, upon receiving the message, delays it until another edge-triggered moment. Based on the entire operation process, combined with the counter values ​​during transmission and reception, and the delay time, a more accurate measurement of the interconnect delay can be achieved, for example, reaching a measurement accuracy at the picosecond (ps) level. Figure 1 In the example shown, interconnect line 100 is an electrical transmission line. In other examples, the interconnect line may be an electrical transmission line passing through a chip or other electronic devices.

[0050] Furthermore, the second FPGA includes a delay unit that delays messages in increments of a delay interval, which is less than the time interval between adjacent counter values. The second FPGA can implement this delay unit by calling and instantiating the IDELAYE primitive. For example, IDELAYE2 is a dedicated input delay primitive in Xilinx 7 series and later FPGA architectures, providing precise timing calibration. This hard-core module achieves fine-grained timing control of the input signal path through programmable tapped delay lines. For example, IDELAYE2 can provide 32 cascaded delay taps, each representing a fixed delay interval, such as 78 ps, for a total adjustable delay range of 2.469 ns. Meanwhile, assuming the FPGA system clock is 100 MHz, the corresponding clock period and the time interval T between adjacent counter values... cycle Both are 10ns. Clearly, the delay interval provided by the delay unit is significantly smaller than the time interval of the counter value. By using the delay unit for stepped delays, this measurement system can achieve a delay measurement accuracy at the ps level.

[0051] The delay time for messages in the second FPGA is determined based on the number of steps the delay unit takes on the delay interval and the delay interval itself. Using non-blocking assignment statements in digital logic, it can be determined that the received message has been delayed to the second edge-triggered moment. At this point, the delay unit stops delaying the message and outputs the number of steps it takes on the delay interval, i.e., how many delay taps were used. Based on the primitives used to implement the delay unit and the selected mode, the delay interval T can be determined. tapBased on the number of steps m output by the delay unit, the delay time T can be determined by the following formula (5). delay The following equation (5) is: (5)

[0052] In summary, by combining the digital logic functions within the FPGA with delay units, the delay of interconnect lines can be accurately measured. It is easy to understand that the delay units may be implemented using other suitable primitives within the FPGA, or they may be implemented using primitives with delay capabilities developed in the future.

[0053] Figure 4 A system according to a second embodiment of this disclosure is shown, which is also used to measure the delay of interconnect lines. The system is substantially the same as the system of the first embodiment in the specific details of delay measurement, the only difference being that the first FPGA and the second FPGA are the same FPGA.

[0054] refer to Figure 4 Both ends of the interconnect line 400 are located on the first FPGA. At the first edge-triggered moment, the first FPGA sends a message from its output pin, which is then transmitted to its input pin via the interconnect line. The first FPGA receives the message from the input pin and determines the counter value at the time of reception. Further, the first FPGA uses its internal delay unit to delay the message until the second edge-triggered moment. The first FPGA uses its internal counter to count. Since the counter is unique, the counter value at the time of transmission (i.e., the first edge-triggered moment) is comparable to the counter value at the time of reception. Apart from this, the method for determining the interconnect line delay is similar to the first embodiment and will not be described in detail here.

[0055] Furthermore, this disclosure also proposes a method 500 for measuring the time delay of interconnect lines. Figure 5 A flowchart of a delay measurement method for interconnect lines according to an embodiment of the present disclosure is shown. This measurement method 500 can be applied to the measurement system provided in the first embodiment. One end of the interconnect line is located on a first FPGA, and the other end of the interconnect line is located on a second FPGA. The counters of the first FPGA and the second FPGA are synchronized. The measurement method 500 includes steps S501 to S504.

[0056] Step S501: The first FPGA sends the message to the second FPGA via the interconnect line at the first moment of edge triggering.

[0057] Step S502: The second FPGA receives the message and determines the counter value at the time of reception.

[0058] Step S503: The second FPGA delays the message until the second edge-triggered moment, and the counter value corresponding to the second edge-triggered moment is the sum of the counter value at the time of reception and a predetermined integer value.

[0059] Step S504: Determine the interconnect delay based on the following: the counter value corresponding to the first moment of edge triggering, the counter value at reception, the message delay time of the second FPGA, a predetermined integer value, and the time interval between adjacent counter values. In one example, the second FPGA determines the interconnect delay based on the above parameters. In another example, the above parameters are aggregated into a computing device, which determines the interconnect delay.

[0060] Implementation details of measurement method 500 can be found in the first embodiment described above. Optionally, the second FPGA determines the delay of the interconnect line, and the counter value corresponding to the first edge-triggered moment is obtained by the second FPGA processing the message. For example, in one example, the message contains the counter value corresponding to the first edge-triggered moment.

[0061] Furthermore, the second FPGA includes a delay unit that delays the message in steps with a delay interval, the delay interval being less than the time interval between adjacent counter values. Further, the delay time of the message by the second FPGA is determined based on the number of steps the delay unit takes in the delay interval and the delay interval itself.

[0062] Furthermore, the measurement method 500 can also be applied to the measurement system provided in the second embodiment. In this case, the first FPGA and the second FPGA are the same FPGA.

[0063] In addition, this disclosure also proposes another system for measuring the delay of interconnect lines. Figure 6 A schematic diagram of a system according to a third embodiment of this disclosure is shown. The system includes a first FPGA, a second chip, and an interconnect line 600. One end of the interconnect line 600 is located on the first FPGA, and the other end of the interconnect line 600 is located on the second chip. The first FPGA has a counter.

[0064] Figure 7 An example message flow is shown in the third embodiment for measuring the latency of interconnect lines. Figure 8A timing diagram corresponding to message transmission and reception in the third embodiment is shown. In this system, a first FPGA is configured to transmit a message to a second chip via interconnect 600 at a first edge-triggered time 110. Further, the first FPGA is configured to receive the message returned from the second chip and determine a counter value at reception time 120. The first FPGA is also configured to delay the message until a second edge-triggered time 130, where the counter value corresponding to the second edge-triggered time 130 is the sum of the counter value at reception time and a predetermined integer value. Finally, the first FPGA is configured to determine the delay of interconnect 600 based on the counter value corresponding to the first edge-triggered time 110, the counter value at reception time 120, the delay time of the first FPGA for the message, the predetermined integer value, and the time interval between adjacent counter values. The second chip in the system is configured to immediately return the message to the first FPGA via interconnect 600 after receiving it.

[0065] refer to Figure 7 and Figure 8 The first FPGA sends a message at the first edge-triggered time 110, receives the returned message at time 120, and delays the returned message until the second edge-triggered time 130. The system only records the timestamps for message transmission, reception, and the delay on the first FPGA side, without paying attention to the timestamps from the second chip side. Therefore, only the first FPGA needs to have a counter. The first FPGA uses bidirectional I / O pins, one for sending messages and the other for receiving the returned message. The second chip uses bidirectional I / O pins to immediately send the received message back to the first FPGA. The second chip can be any suitable chip, such as an FPGA chip, a custom chip (i.e., an ASIC chip), etc.

[0066] Since the first FPGA has a counter, and the message is sent by the first FPGA at the first edge-triggered moment 110, the first FPGA can determine the counter value CV1 corresponding to the first edge-triggered moment 110. Figure 8 In the provided example, the counter value CV1 corresponding to the first edge-triggered moment 110 is 1. The first FPGA also determines the counter value CV2 corresponding to 120 when receiving the feedback message. Figure 8 Specifically, it is 4. When the predetermined integer value n is 1, the first FPGA delays this message until the 6th rising edge occurs (i.e., time 130), and the corresponding delay time is T. delay Furthermore, based on the counter information or internal clock frequency of the first FPGA, the time interval T between adjacent counter values ​​can be determined. cycle After determining the above necessary parameters, the time delay T of the interconnection line can be calculated using the following formula (6). The following formula (6) is: (6)

[0067] like Figure 6 As shown, the first FPGA includes a delay unit, which is similar to the delay unit mentioned in the first embodiment. Specifically, this delay unit delays the message in steps with a delay interval, the delay interval being less than the time interval between adjacent counter values. Further, the delay time of the message by the first FPGA is determined based on the number of steps the delay unit takes on the delay interval and the delay interval itself.

[0068] In the third embodiment, the system still accurately measures the interconnect delay by combining the digital logic functions within the FPGA with the adjustment of the delay unit. The digital logic functions within the FPGA are manifested, for example, by using non-blocking assignment statements to send messages at edge-triggered moments, and by using non-blocking assignment statements to determine that a message has been delayed to another edge-triggered moment. Unlike the first embodiment, messages sent from the first FPGA are immediately returned to the first FPGA after being relayed back by the second chip, and timestamps are recorded only on the first FPGA side. Therefore, the requirements for the second chip are reduced, and the system has a wider range of applications.

[0069] Furthermore, this disclosure also proposes a method 900 for measuring the time delay of interconnect lines. Figure 9 A flowchart of a delay measurement method for an interconnect line according to an embodiment of the present disclosure is shown. This measurement method 900 can be applied to the measurement system provided in the third embodiment. One end of the interconnect line is located on a first FPGA, and the other end of the interconnect line is located on a second chip. The first FPGA has a counter. The measurement method 900 includes steps S901 to S905.

[0070] Step S901: The first FPGA sends the message to the second chip via the interconnect line at the first moment of edge triggering.

[0071] Step S902: The second chip immediately transmits the message back to the first FPGA via the interconnect line.

[0072] Step S903: The first FPGA receives the returned message and determines the counter value at the time of reception.

[0073] Step S904: The first FPGA delays the message until the second edge-triggered moment, wherein the counter value corresponding to the second edge-triggered moment is the sum of the counter value at the time of reception and a predetermined integer value.

[0074] Step S905: Determine the interconnect delay based on the following: the counter value corresponding to the first moment of edge triggering, the counter value at reception, the delay time of the message by the first FPGA, a predetermined integer value, and the time interval between adjacent counter values. In one example, the first FPGA determines the interconnect delay based on the above parameters. In another example, the above parameters are aggregated into a computing device, which determines the interconnect delay.

[0075] Implementation details of measurement method 900 can be found in the third embodiment described above. Further, the first FPGA includes a delay unit that delays the message in steps with a delay interval, the delay interval being less than the time interval between adjacent counter values. Specifically, the delay time of the message by the first FPGA is determined based on the number of steps the delay unit takes in the delay interval and the delay interval itself.

[0076] Furthermore, although exemplary embodiments have been described herein, their scope includes any and all embodiments based on this disclosure that have equivalent elements, modifications, omissions, combinations (e.g., schemes involving intersections of various embodiments), adaptations, or alterations. Elements in the claims will be interpreted broadly based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of this disclosure, and such examples will be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered illustrative only, and the true scope and spirit are indicated by the various claims in the claims and the full scope of their equivalents.

[0077] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more thereof) can be used in combination with each other. Other embodiments can be used by those skilled in the art when reading the above description. Furthermore, in the above specific embodiments, various features may be grouped together to simplify the disclosure. Features disclosed that are not claimed in the claims are not essential to any claim. Rather, the subject matter of this disclosure may be less than all the features of a particular disclosed embodiment.

[0078] Therefore, the claims are incorporated herein by way of example or embodiment, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of protection of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A system for measuring the time delay of interconnect lines, the system comprising: The interconnection line has one end located on the first FPGA and the other end located on the second FPGA; The first FPGA is configured to send a message via the interconnect to the second FPGA at a first moment triggered by an edge; and The second FPGA, whose counter is synchronized with the counter of the first FPGA, is configured as follows: Receive the message and determine the counter value at the time of reception. The message is delayed until the second edge-triggered moment, and the counter value corresponding to the second edge-triggered moment is the sum of the counter value at the time of reception and a predetermined integer value. The delay of the interconnect is determined based on the following: the counter value corresponding to the first moment of edge triggering, the counter value at the time of reception, the delay time of the message by the second FPGA, the predetermined integer value, and the time interval between adjacent counter values.

2. The system according to claim 1, wherein, The first FPGA and the second FPGA are the same FPGA.

3. The system according to claim 1, wherein, The counter value corresponding to the first moment of edge triggering is obtained by the second FPGA processing the message.

4. The system according to claim 3, wherein, The message contains the counter value corresponding to the first moment of the edge triggering.

5. The system according to claim 1, wherein, The second FPGA includes a delay unit that delays the message in increments of a delay interval, the delay interval being less than the time interval between adjacent counter values.

6. The system according to claim 5, wherein, The delay time of the message by the second FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

7. A method for measuring the delay of an interconnect line, wherein one end of the interconnect line is located on a first FPGA, the other end of the interconnect line is located on a second FPGA, and the counters of the first FPGA and the second FPGA are synchronized, the method comprising: The first FPGA sends the message to the second FPGA via the interconnect at the first moment of edge triggering; The second FPGA receives the message and determines the counter value at the time of reception; The second FPGA delays the message until the second edge-triggered moment, and the counter value corresponding to the second edge-triggered moment is the sum of the counter value at the time of reception and a predetermined integer value; as well as The delay of the interconnect is determined based on the following: the counter value corresponding to the first moment of edge triggering, the counter value at the time of reception, the delay time of the message by the second FPGA, the predetermined integer value, and the time interval between adjacent counter values.

8. The time delay measurement method according to claim 7, wherein, The first FPGA and the second FPGA are the same FPGA.

9. The time delay measurement method according to claim 7, wherein, The second FPGA determines the delay of the interconnect line, and the counter value corresponding to the first moment of the edge trigger is obtained by the second FPGA processing the message.

10. The time delay measurement method according to claim 9, wherein, The message contains the counter value corresponding to the first moment of the edge triggering.

11. The time delay measurement method according to claim 7, wherein, The second FPGA includes a delay unit that delays the message in increments of a delay interval, the delay interval being less than the time interval between adjacent counter values.

12. The time delay measurement method according to claim 11, wherein, The delay time of the message by the second FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

13. A system for measuring the time delay of interconnect lines, the system comprising: The interconnection line has one end located on the first FPGA and the other end located on the second chip; The first FPGA, which has a counter, is configured as follows: The message is sent to the second chip via the interconnect at the first moment of edge triggering. Receive the message returned from the second chip and determine the counter value at the time of reception. The message is delayed until the second edge-triggered moment, and the counter value corresponding to the second edge-triggered moment is the sum of the counter value at the time of reception and a predetermined integer value. The latency of the interconnect is determined based on the following: the counter value corresponding to the first moment of edge triggering, the counter value at the time of reception, the delay time of the message by the first FPGA, the predetermined integer value, and the time interval between adjacent counter values; as well as The second chip is configured to immediately transmit the message back to the first FPGA via the interconnect line after receiving the message.

14. The system according to claim 13, wherein, The first FPGA includes a delay unit, which delays the message by a delay interval as a step length, the delay interval being less than the time interval between adjacent counter values.

15. The system according to claim 14, wherein, The delay time of the message by the first FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

16. A method for measuring the delay of an interconnect line, wherein one end of the interconnect line is located on a first FPGA, the other end of the interconnect line is located on a second chip, and the first FPGA has a counter, the method comprising: The first FPGA sends the message to the second chip via the interconnect at the first moment of edge triggering; The second chip immediately transmits the message back to the first FPGA via the interconnect line; The first FPGA receives the returned message and determines the counter value at the time of reception; The first FPGA delays the message until the second edge-triggered moment, and the counter value corresponding to the second edge-triggered moment is the sum of the counter value at the time of reception and a predetermined integer value; as well as The latency of the interconnect is determined based on the following: the counter value corresponding to the first moment of edge triggering, the counter value at the time of reception, the delay time of the message by the first FPGA, the predetermined integer value, and the time interval between adjacent counter values.

17. The time delay measurement method according to claim 16, wherein, The first FPGA includes a delay unit, which delays the message by a delay interval as a step length, the delay interval being less than the time interval between adjacent counter values.

18. The time delay measurement method according to claim 17, wherein, The delay time of the message by the first FPGA is determined based on the number of steps of the delay unit on the delay interval and the delay interval itself.

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