Back contact cell, cell assembly and photovoltaic system

Abstract

The invention relates to the technical field of solar cells, and provides a back contact cell, a cell assembly and a photovoltaic system, in the back contact cell, a first region and a second region are separated by a third region, and an insulating dielectric layer is arranged in the third region and extends to an overlapping region of a first doping layer; the second doped layer extends from the second region to an overlapping region of the third region and the first region. Thus, due to the arrangement of the insulating dielectric layer on the third region, effective electrical isolation between the first doping layer on the first region and the second doping layer on the second region can be realized without introducing a deep trench on the silicon substrate, the formation of the deep trench can be avoided, the strength of the silicon substrate can be improved, and the risk of wafer cracking can be effectively reduced. Meanwhile, due to the arrangement of the insulating dielectric layer on the third region and the second doping layer located above the insulating dielectric layer, the passivation effect of the isolation region can be further enhanced, and therefore the efficiency of the back contact battery is improved.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0002] As a typical example of high-efficiency photovoltaic devices, the core design of back-contact solar cells lies in integrating the P-type doped region, the N-type doped region, and the metal electrode all on the back of the silicon wafer. This avoids the problem of the front metal electrode blocking the incident light, effectively improving the short-circuit current density and the overall photoelectric conversion efficiency.

[0003] However, in related technologies, to achieve insulation between the P-type and N-type doped layers, a common method is to create deep trenches on the silicon wafer surface to form an insulating barrier. While this trench isolation structure can meet basic insulation requirements, on the one hand, although the trench design achieves isolation, the surface passivation effect in the trench area is poor, thus affecting the overall efficiency of the back contact cell. On the other hand, the trenches can easily reduce the strength of the silicon substrate, increasing the risk of wafer cracking during manufacturing and transportation. Summary of the Invention

[0004] This application provides a back-contact battery, a battery module, and a photovoltaic system.

[0005] This application is implemented as follows: the back contact battery in the embodiments of this application includes: A silicon substrate having opposing front and back sides, the back side including a first region, a second region, and a third region located between the first region and the second region; A first passivation layer and a first doped layer are sequentially stacked on the first region, wherein the surface of the first doped layer facing away from the silicon substrate includes a contact region and an overlap region. An insulating dielectric layer is stacked on the third region and extends to the overlapping region; A second passivation layer and a second doped layer are sequentially stacked on the second region, the second doped layer extending to the third region and the overlapping region and covering the insulating dielectric layer; A back passivation layer, the back passivation layer covering the second doped layer and the contact region, the back passivation layer contacting the first doped layer in the contact region; and A first electrode and a second electrode, wherein the first electrode is located in the contact area and at least partially penetrates the back passivation layer to make conductive contact with the first doped layer, and the second electrode is located in the second region and at least partially penetrates the back passivation layer to make conductive contact with the second doped layer.

[0006] In some embodiments, the second passivation layer also extends to the third region and the overlapping region and is located between the second doped layer and the insulating dielectric layer.

[0007] In some embodiments, the insulating dielectric layer includes at least one of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon oxynitride layer, a silicon oxycarbonate layer, a silicon oxycarbonate layer, an aluminum oxide layer, an amorphous silicon layer, a borosilicate glass layer, a phosphosilicate glass layer, and a polycrystalline silicon layer.

[0008] In some embodiments, the back passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon oxynitride layer, a silicon oxycarbonate layer, a silicon oxycarbonitrile layer, and an aluminum oxide layer.

[0009] In some embodiments, the insulating dielectric layer is made of a different material than the back passivation layer.

[0010] In some embodiments, the thickness of the insulating dielectric layer is 5nm-300nm.

[0011] In some embodiments, the thickness of the back passivation layer is 50nm-400nm.

[0012] In some embodiments, the thickness ratio of the insulating dielectric layer to the back passivation layer is 0.0125-6.

[0013] In some embodiments, the thickness ratio of the insulating dielectric layer to the second passivation layer is 2-50.

[0014] In some embodiments, a front passivation layer is provided on the front side of the silicon substrate, and the material of the insulating dielectric layer is different from the material of the front passivation layer.

[0015] In some embodiments, the surface of the third region is recessed into the silicon substrate relative to the surface of the first region, and the surface of the second region is recessed into the silicon substrate relative to the surface of the third region.

[0016] In some embodiments, the third region is recessed into the silicon substrate to a depth of 1 nm-5000 nm compared to the first region; The second region is recessed into the silicon substrate to a depth of 1nm-5000nm compared to the third region.

[0017] In some embodiments, the width of the third region is 10um-600um.

[0018] In some embodiments, the number of the first region, the second region, and the third region are all multiple; The first region and the second region are arranged alternately along a first direction, and the third region is located between adjacent first regions and second regions. The ratio between the sum of the areas of all the third regions and the area of ​​the entire back surface is 0.01-0.6.

[0019] In some embodiments, the surface of the third region is a velvety or polished surface.

[0020] In some embodiments, the surface of the third region is recessed into the silicon substrate relative to the surface of the first region, and the silicon substrate has a first connecting surface connecting the surface of the first region and the surface of the third region, the first connecting surface being a textured or polished surface.

[0021] In some embodiments, the surface of the second region is recessed into the silicon substrate relative to the surface of the third region, and the silicon substrate has a second connecting surface that connects the surface of the second region and the surface of the third region, the second connecting surface being a textured or polished surface.

[0022] In some embodiments, a contact hole is formed in the portion of the insulating dielectric layer located on the overlapping region, the first doped layer is exposed from the contact hole, the second passivation layer and the second doped layer at least partially fill the contact hole, the second passivation layer contacts the first doped layer at the contact hole, and the second doped layer is connected to the first doped layer at the contact hole through the second passivation layer.

[0023] In some embodiments, in the back contact battery, the ratio between the sum of the areas of all the contact holes and the area of ​​the entire back surface is 10. -8 -10 -3 .

[0024] In some embodiments, the silicon substrate has a first inner expansion layer formed in the first region, and the silicon substrate has a second inner expansion layer formed in the second region, wherein the second inner expansion layer and the first inner expansion layer are spaced apart through the third region.

[0025] This application also provides a battery assembly comprising a plurality of back contact batteries as described in any of the preceding claims.

[0026] This application also provides a photovoltaic system, which includes the aforementioned battery components.

[0027] In the back-contact cell, cell module, and photovoltaic system of this application embodiment, a first region and a second region are separated by a third region. An insulating dielectric layer is disposed in the third region and extends to the overlap region of the first doped layer. A second doped layer extends from the second region to the overlap region of the third region and the first region. Thus, due to the insulating dielectric layer on the third region, effective electrical isolation between the first doped layer on the first region and the second doped layer on the second region can be achieved without introducing deep trenches on the silicon substrate. This insulating dielectric layer provides effective electrical insulation, avoiding the creation of deep trenches, improving the strength of the silicon substrate, and effectively reducing the risk of wafer cracking. Simultaneously, the insulating dielectric layer on the third region and the second doped layer above it further enhance the passivation effect of the isolated region, thereby improving the efficiency of the back-contact cell.

[0028] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the photovoltaic system provided in the embodiments of this application.

[0030] Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application; Figure 3 This is a cross-sectional structural diagram of the back contact battery provided in an embodiment of this application; Figure 4 This is a schematic diagram of the silicon substrate structure of the back contact battery provided in the embodiments of this application; Figure 5 This is another cross-sectional structural diagram of the back contact battery provided in the embodiments of this application; Figure 6 This is another cross-sectional structural diagram of the back contact battery provided in the embodiments of this application.

[0031] Explanation of key component symbols: Photovoltaic system 1000, battery module 200, back contact cell 100, silicon substrate 10, front side 11, back side 12, first region 121, second region 122, third region 123, first passivation layer 20, first doped layer 30, contact region 31, overlapping region 32, insulating dielectric layer 40, contact hole 41, second passivation layer 50, second doped layer 60, back passivation layer 70, first electrode 80, second electrode 90, first connection surface 101, second connection surface 102, first inner expansion layer 103, second inner expansion layer 104. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be noted that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0033] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "several" means two or more, unless otherwise explicitly specified.

[0035] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0036] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] Please see Figure 1 and Figure 2 The photovoltaic system 1000 in this application embodiment may include the battery module 200 in this application embodiment, and the battery module 200 in this application embodiment may include a plurality of back contact batteries 100 in this application embodiment.

[0038] In embodiments of this application, multiple back-contact batteries 100 in the battery assembly 200 can be connected in series to form multiple battery strings. Each battery string can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between individual battery cells can be achieved by welding solder strips, or the connection between individual battery strings can be achieved by busbars. In some embodiments, the individual battery strings can form a battery cell array, and then be packaged together by a front plate, a front adhesive film, a rear adhesive film, and a back plate to form the battery assembly 200.

[0039] In the embodiments of this application, please refer to Figure 3 The back contact battery 100 in this application embodiment may include a silicon substrate 10, a first passivation layer 20, a first doped layer 30, an insulating dielectric layer 40, a second passivation layer 50, a second doped layer 60, a back passivation layer 70, a first electrode 80, and a second electrode 90.

[0040] like Figure 3 and Figure 4 As shown, the silicon substrate 1010 has a front side 11 and a back side 12. The back side 12 includes a first region 121, a second region 122, and a third region 123 located between the first region 121 and the second region 122. In some embodiments, there are multiple first regions 121 and second regions 122 (only two first regions 121 and one second region 122 are shown in the figure), and a third region 123 is provided between adjacent first regions 121 and second regions 122. In some possible embodiments, the third region 123 is the region between the first regions 121 and the second regions 122, and the first regions 121 and the second regions 122 are separated by the third region 123. That is, the back side 12 of the silicon substrate 10 can be divided into alternating first regions 121 and second regions 122, and the third region 123 exists as an isolation band between adjacent first regions 121 and second regions 122.

[0041] like Figure 3 As shown, the first passivation layer 20 and the first doped layer 30 are stacked sequentially on the first region 121. That is, the first passivation layer 20 is stacked on the first region 121, and the first doped layer 30 is stacked on the first passivation layer 20. The surface of the first doped layer 30 facing away from the silicon substrate 10 includes a contact region 31 and an overlapping region 32.

[0042] An insulating dielectric layer 40 is stacked on the third region 123 and extends to the overlap region 32 of the first doped layer 30. A second passivation layer 50 and a second doped layer 60 are stacked sequentially on the second region 122, that is, the second passivation layer 50 is stacked on the second region 122 and the second doped layer 60 is stacked on the second passivation layer 50.

[0043] like Figure 3 As shown, the second doped layer 60 extends to the third region 123 and the overlapping region 32 and covers the insulating dielectric layer 40. That is, the portion of the insulating dielectric layer 40 located in the third region 123 has a second passivation layer 50 and a second doped layer 60, and the portion of the insulating dielectric layer 40 located in the overlapping region 32 of the first doped layer 30 also has a second doped layer 60. In other words, in the first doped layer 30, only the portion located in the contact region 31 is not covered by the insulating dielectric layer 40 and the second doped layer 60. The back passivation layer 70 covers the second doped layer 60 and the contact region 31. In other words, the back passivation layer 70 can cover the entire back surface 12, and the back passivation layer 70 contacts the first doped layer 30 in the contact region 31 of the first doped layer 30.

[0044] The first electrode 80 is located in the contact area 31 and at least partially penetrates the back passivation layer 70 to make conductive contact with the first doped layer 30. The second electrode 90 is located in the second region 122 and at least partially penetrates the back passivation layer 70 to make conductive contact with the second doped layer 60.

[0045] In the back contact battery 100, battery module 200, and photovoltaic system 1000 of this application embodiment, the first region 121 and the second region 122 are separated by a third region 123. An insulating dielectric layer 40 is disposed in the third region 123 and extends to the overlap region 32 of the first doped layer 30. The second doped layer 60 extends from the second region 122 to the overlap region 32 of the third region 123 and the first region 121. Thus, due to the provision of the insulating dielectric layer 40 on the third region 123, effective electrical isolation between the first doped layer 30 on the first region 121 and the second doped layer 60 on the second region 122 can be achieved without introducing deep trenches on the silicon substrate 10. The insulating dielectric layer 40 provides effective electrical insulation, avoids the creation of deep trenches, improves the strength of the silicon substrate 10, and effectively reduces the risk of wafer cracking. Meanwhile, due to the presence of the insulating dielectric layer 40 on the third region 123 and the second doped layer 60 above it, the passivation effect of the isolation region (i.e., the third region 123) can be further enhanced, thereby improving the efficiency of the back contact battery 100.

[0046] In other words, compared with the existing technology that uses deep trenches to form isolation regions on silicon substrates, the structure of the present application embodiment can avoid the creation of deep trenches, thereby reducing the risk of chip cracking. At the same time, it can improve the passivation quality of the isolation region while achieving insulation isolation, thereby improving the efficiency of the back contact battery.

[0047] Specifically, such as Figure 3 As shown in the embodiments of this application, the contact area 31 refers to the area on the surface of the first doped layer 30 that is not covered by the insulating dielectric layer 40 and the second doped layer 60, and it is used for conductive contact with the electrode. The overlapping area 32 refers to the area on the surface of the first doped layer 30 that is covered by the insulating dielectric layer 40 and the second doped layer 60.

[0048] The silicon substrate 10 can be either a P-type or an N-type silicon substrate, and this is not specifically limited. In the embodiments of this application, one of the first doped layer 30 and the second doped layer 60 can be a P-type doped layer doped with a Group 3 element (e.g., boron), and the other can be an N-type doped layer doped with a Group 5 element (e.g., phosphorus), and this is not specifically limited. In some embodiments, the first doped layer 30 can be a P-type doped layer, and the second doped layer 60 can be an N-type doped layer.

[0049] In the embodiments of this application, both the first doped layer 30 and the second doped layer 60 can be doped polysilicon layers, and both the first passivation layer 20 and the second passivation layer 50 have tunneling functionality. For example, in some embodiments, both the first passivation layer 20 and the second passivation layer 50 can be tunneling silicon oxide layers. The first passivation layer 20 and the first doped layer 30 constitute a polar tunneling passivation contact structure, and the second passivation layer 50 and the second doped layer 60 constitute a different polar tunneling passivation contact structure, with opposite polarities.

[0050] In the embodiments of this application, the insulating dielectric layer 40 may be made of insulating material, which may be a single-layer film structure or a multi-layer film structure, and there is no specific limitation here. The main function of the insulating dielectric layer 40 is to insulatingly separate the first region 121 and the second region 123 and passivate the third region 123.

[0051] The first electrode 80 and the second electrode 90 are metal contacts used to draw out the battery current. They are in conductive contact with the first doped layer 30 and the second doped layer 60, respectively, for collecting charge carriers. The electrodes can be formed using techniques such as screen printing, physical vapor deposition, and electroplating. In some possible embodiments, before forming the electrodes, contact grooves can be etched on the back passivation layer 70 using methods such as laser etching to ensure good ohmic contact between the electrodes and the corresponding doped layers. Of course, in some possible embodiments, the electrode paste can be a burn-through paste. In this case, it is not necessary to pre-groove the back passivation layer 70; instead, the back passivation layer 70 can be directly burned through using the paste.

[0052] The back passivation layer 70 is one or more thin films covering the back structure 12 of the battery. It not only provides passivation effect and reduces surface recombination, but also serves as a protective layer. The back passivation layer 70 can be a single-layer or multi-layer film structure, and there is no specific limitation here.

[0053] In the embodiments of this application, the back contact battery 100 can be prepared by the following method, the specific process of which is illustrated below: S1: Provide a silicon substrate 10, which can be a P-type silicon substrate or an N-type silicon substrate; S2: A first passivation layer 20 and a first doped layer 30 are formed on the entire back side 12 of the silicon substrate 10; S3: Remove the first passivation layer 20 and the first doped layer 30 on the second region 122 and the third region 123, and retain the first passivation layer 20 and the first doped layer 30 on the first region 121; S4: An insulating dielectric layer 40 is prepared across the entire back side 12; S5: Remove the insulating dielectric layer 40 located on the second region 122; S6: Prepare a second passivation layer 50 and a second doped layer 60 on the entire back side 12; S7: Remove the second doped layer 60, the second passivation layer 50, and the insulating dielectric layer 40 located on the contact area 31 of the first doped layer 30 to expose the contact area 31 of the first doped layer 30. S8: A back passivation layer 70 is prepared on the entire back surface 12, and the back passivation layer 70 is in contact with the first doped layer 30 in the contact region 31; S9: A first electrode 80 is prepared in the contact region 31 and a second electrode 90 is prepared in the second region 122. The first electrode 80 at least partially penetrates the back passivation layer 70 and makes conductive contact with the first doped layer 30, and the second electrode 90 at least partially penetrates the back passivation layer 70 and makes conductive contact with the second doped layer 60.

[0054] In some embodiments, the insulating dielectric layer 40 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon oxynitride layer, a silicon oxycarbonate layer, a silicon oxycarbonitrile layer, and an aluminum oxide layer.

[0055] Thus, by configuring the insulating dielectric layer 40 with at least one material selected from silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonate, silicon oxycarbonitrile, and aluminum oxide, the electrical insulation performance and surface passivation effect of the insulating dielectric layer 40 can be significantly improved. Simultaneously, the passivation effect of the third region 123 can be enhanced, reducing recombination losses on the surface of the silicon substrate 10, thereby enabling the battery to collect photogenerated carriers more efficiently and improving the conversion efficiency of the back contact battery 100.

[0056] Specifically, in this application, the main functions of the insulating dielectric layer 40 are to provide electrical insulation and surface passivation. Electrical insulation ensures effective isolation between different regions, preventing unnecessary current short circuits and thus guaranteeing effective carrier collection. Simultaneously, good surface passivation significantly reduces the defect state density on the surface of the silicon substrate 10, reducing carrier recombination losses and thereby improving cell efficiency.

[0057] Specifically, silicon oxide layers possess excellent electrical insulation and passivation properties, and can be formed through methods such as thermal oxidation or chemical vapor deposition. Silicon nitride layers exhibit high dielectric constant and excellent passivation, particularly in hydrogen passivation, effectively saturating dangling bonds on the silicon surface; they can be deposited using techniques such as plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. Silicon carbide layers possess excellent chemical stability and passivation, maintaining stable insulation properties even at high temperatures; they can be prepared through methods such as vapor deposition. Silicon oxynitride layers combine the advantages of silicon oxide and silicon nitride, exhibiting good passivation performance; they are typically obtained by introducing oxygen or nitrogen during the deposition of silicon oxide or silicon nitride. Alumina layers possess high dielectric constant and excellent passivation properties, and can be formed through methods such as atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0058] Of course, in some possible embodiments, the insulating dielectric layer 40 may also include at least one of the following: an amorphous silicon layer, an amorphous silicon layer, a borosilicate glass layer, a phosphosilicate glass layer, and a polycrystalline silicon layer, all of which have insulating functions. That is, in some possible embodiments, the insulating dielectric layer 40 may include at least one of the following: a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon oxynitride layer, a silicon oxycarbonate layer, a silicon oxycarbonitrile layer, an aluminum oxide layer, an amorphous silicon layer, a borosilicate glass layer, a phosphosilicate glass layer, and a polycrystalline silicon layer.

[0059] Specifically, the amorphous silicon layer provides good surface passivation and can be deposited using methods such as physical vapor deposition or chemical vapor deposition. The borosilicate glass layer and phosphosilicate glass layer can be obtained by depositing an amorphous silicon layer or a polycrystalline silicon layer and then performing boron doping or phosphorus doping treatment. When the insulating dielectric layer 40 is a polycrystalline silicon layer, it is a high-resistivity polycrystalline silicon layer, which itself is undoped or only lightly doped. That is to say, when the polycrystalline silicon layer is used as the insulating dielectric layer 40, in order to ensure its insulating performance, it needs to be set as an undoped or lightly doped polycrystalline silicon layer.

[0060] Furthermore, in this application, in order to ensure the passivation effect while ensuring the insulation performance of the insulating dielectric layer 40, the insulating dielectric layer 40 may preferably be at least one of the following: silicon oxide layer, silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbonate layer, silicon oxycarbonitrile layer, and aluminum oxide layer.

[0061] In this application, the insulating dielectric layer 40 may be a single-layer film structure, a double-layer film structure, or a multi-layer film structure, and no specific limitation is made here.

[0062] In some embodiments, the second passivation layer 50 may also extend to the third region 123 and the overlapping region 32 and be located between the second doped layer 60 and the insulating dielectric layer 40. Thus, the second passivation layer 50 is also present on the overlapping region 32, which can further enhance the passivation effect of the region.

[0063] Of course, it is understandable that in some embodiments, the second passivation layer 50 is not present on the overlapping region 32.

[0064] Specifically, in some embodiments, the insulating dielectric layer 40 may be a silicon oxide layer, and the second passivation layer 50 may be a tunneling silicon oxide layer. When the second passivation layer 50 is formed by thermal oxidation, the insulating dielectric layer 40 cannot be oxidized to form the second passivation layer 50. In this case, the overlapping region 32 does not have the second passivation layer 50. When the second passivation layer 50 is deposited by physical vapor deposition or chemical vapor deposition, the insulating dielectric layer 40 has the second passivation layer 50, that is, the overlapping region 32 has the second passivation layer 50. Furthermore, in some embodiments, the insulating dielectric layer 40 may also be a film layer other than the silicon oxide layer mentioned above. In this case, regardless of whether the second passivation layer 50 is formed by thermal oxidation or deposition, the overlapping region 32 will have the second passivation layer.

[0065] In some embodiments, the back passivation layer 70 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon oxynitride layer, a silicon oxycarbonate layer, a silicon oxycarbonitrile layer, and an aluminum oxide layer. This can improve the passivation effect of the back contact battery 100.

[0066] Furthermore, in some embodiments, the back passivation layer 70 may preferably be at least one of a silicon nitride layer and an aluminum oxide layer.

[0067] Thus, by configuring the back passivation layer 70 to include at least one of an aluminum oxide layer and a silicon nitride layer, the passivation effect of the back contact cell 100 can be significantly improved. The excellent field-effect passivation and chemical passivation provided by the aluminum oxide layer, and the good passivation and protection provided by the silicon nitride layer, work together on the back side 12 of the silicon substrate 10 to effectively reduce the carrier recombination rate and improve the cell conversion efficiency.

[0068] In some embodiments, the insulating dielectric layer 40 is made of a different material than the back passivation layer 70.

[0069] Thus, by using different materials for the insulating dielectric layer 40 and the back passivation layer 70, the third region 123 can be efficiently passivated using multiple layers of different materials, thereby further improving the passivation effect of the third region 123. In other words, in this embodiment, the third region 123 has multiple passivation layers of different materials. This differentiated arrangement allows for more efficient passivation of the third region 123, thereby improving the efficiency of the back contact battery 100. In other words, by designing the insulating dielectric layer 40 and the back passivation layer 70 to be made of different materials, the problem of insufficient passivation effect from a single material is avoided.

[0070] For example, in some embodiments, the insulating dielectric layer 40 may be a silicon oxide layer, and the back passivation layer 70 may be at least one of aluminum oxide and silicon nitride layers. Thus, the insulating dielectric layer 40 can achieve excellent insulation while also providing good passivation. The silicon oxide layer, in combination with the aluminum oxide and / or silicon nitride layers, can achieve more efficient passivation of the third region 123. Furthermore, this arrangement of the insulating dielectric layer 40 and the back passivation layer 70 can also protect the back contact battery 100, effectively reducing the risk of scratches to the back contact battery 100 during manufacturing and transportation.

[0071] For example, in some embodiments, the insulating dielectric layer 40 may be one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxycarbide layer. The back passivation layer 70 may be at least one of an aluminum oxide layer and a silicon nitride layer. In this way, through such differentiated combinations, efficient passivation of the third region 123 can be achieved while realizing the insulation function.

[0072] In some embodiments, the thickness of the insulating dielectric layer 40 may be 5 nm to 300 nm.

[0073] Thus, by optimizing and limiting the thickness of the insulating dielectric layer 40 to the range of 5nm-300nm, it is possible to ensure that it provides effective electrical insulation while providing efficient chemical passivation to the area it covers. At the same time, it can avoid breakdown or tunneling effect due to excessive thinness, as well as stress increase and material waste due to excessive thickness.

[0074] Specifically, the insulating dielectric layer 40 is stacked in the third region 123 and extends to the overlapping region 32. Its main function is to electrically isolate the first doped layer 30 and the second doped layer 60, preventing short circuits between them and reducing carrier recombination at the interface. By precisely controlling the thickness of the insulating dielectric layer 40 within the range of 5nm-300nm, sufficient dielectric strength can be ensured to effectively block leakage current, thereby maintaining the open-circuit voltage and fill factor of the battery. If the thickness of the insulating dielectric layer 40 is less than 5nm, its insulation performance may be insufficient to withstand the electric field strength during battery operation, leading to electrical breakdown or significant tunneling current, thereby reducing battery efficiency. Conversely, if the thickness of the insulating dielectric layer 40 exceeds 300nm, excessive mechanical stress may be introduced into the silicon substrate 10, especially during subsequent high-temperature processing, which may lead to film cracking, peeling, or interface defects, thus affecting the long-term reliability of the battery. In addition, an excessively thick insulating dielectric layer 40 will also increase material costs. Therefore, the setting of this thickness range allows the insulating dielectric layer 40 to ensure excellent electrical insulation performance while taking into account mechanical stability, optical properties and manufacturing costs, thereby optimizing the performance and reliability of the entire back contact battery 100.

[0075] In such embodiments, the thickness of the insulating dielectric layer 40 can be, for example, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 120nm, 140nm, 160nm, 180nm, 200nm, 220nm, 240nm, 260nm, 280nm, 300nm, or other values ​​between 5nm and 300nm. Specifically, after repeated research and demonstration by the inventors of this application, it has been found that the thickness of the insulating dielectric layer 40 is preferably 10nm-50nm, for example, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, or other values ​​between 10nm and 50nm. Thus, by further optimizing the design of the thickness of the insulating dielectric layer 40, material costs can be further reduced while ensuring insulation performance.

[0076] In some embodiments, the thickness of the back passivation layer 70 may be 50 nm to 400 nm.

[0077] As shown below, by optimizing and controlling the thickness of the back passivation layer 70 within the range of 50nm-400nm, it is possible to avoid the back passivation layer 70 being too thin, which would result in insufficient passivation effect, and also to avoid the back passivation layer 70 being too thick, which would result in additional light absorption loss and increased material cost.

[0078] In such embodiments, the thickness of the back passivation layer 70 can be, for example, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, or other values ​​between 50nm and 400nm. Specifically, after repeated research and demonstration by the inventors of this application, it has been found that the thickness of the insulating dielectric layer 40 is preferably 80nm-150nm, for example, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, or other values ​​between 80nm and 150nm. Thus, by further optimizing the design of the thickness of the back passivation layer 70, this optimized thickness ensures that the back passivation layer 70 can provide efficient surface passivation, effectively reducing carrier recombination losses, thereby improving the open-circuit voltage and short-circuit current of the battery. At the same time, this thickness range also helps to optimize the optical properties of the back of the battery 12, reduce unnecessary light absorption, and improve light utilization.

[0079] In some embodiments, the thickness ratio of the insulating dielectric layer 40 to the back passivation layer 70 is 0.0125-6.

[0080] Thus, by limiting the thickness ratio of the insulating dielectric layer 40 to the back passivation layer 70 to the range of 0.0125-6, superior passivation effect and electrical isolation performance can be achieved. Simultaneously, this precise thickness ratio optimization helps balance the mechanical stress of the two layers, significantly reducing the risk of battery structure cracking or delamination caused by interlayer stress mismatch, thereby improving the long-term reliability and stability of the battery. Furthermore, setting this ratio range can enhance the passivation effect of the third region 123, effectively suppressing carrier recombination losses on the back surface 12 of the silicon substrate 10.

[0081] Specifically, the thickness of the insulating dielectric layer 40 and the back passivation layer 70, as key passivation and isolation structures, is crucial to the battery's performance. If the relative thicknesses of these two layers are not properly selected, excessive interlayer stress may occur, affecting the battery's mechanical stability and potentially causing the passivation effect to fall short of expectations. Based on this, the inventors of this application, after research and demonstration, discovered that when the thickness ratio of the insulating dielectric layer 40 to the back passivation layer 70 is limited to the range of 0.0125-6, it can help balance the mechanical stress of the two layers, significantly reducing the risk of battery structural cracking or delamination caused by interlayer stress mismatch, thereby improving the battery's long-term reliability and stability, and also enhancing the passivation effect of the third region 123.

[0082] In such embodiments, the thickness ratio of the insulating dielectric layer 40 to the back passivation layer 70 may be, for example, 0.0125, 0.02, 0.04, 0.06, 0.08, 0.1, 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6 or other values ​​between 0.0125 and 6.

[0083] Furthermore, research and verification have shown that the ratio range is preferably 0.06-0.625. That is to say, in the embodiments of this application, the thickness of the insulating dielectric layer 40 is preferably less than the thickness of the back passivation layer 70, and the thickness of the insulating dielectric layer 40 is 0.06 times to 0.625 times the thickness of the back passivation layer 70, for example, 0.06 times, 0.07 times, 0.08 times, 0.09 times, 0.1 times, 0.15 times, 0.2 times, 0.25 times, 0.3 times, 0.35 times, 0.4 times, 0.45 times, 0.5 times, 0.55 times, 0.6 times, 0.625 times, or other values ​​between 0.06 times and 0.625 times.

[0084] For example, when the insulating dielectric layer 40 is a silicon oxide layer, its thickness can be controlled to 20 nm, and the back passivation layer 70 can be a stacked structure of an aluminum oxide layer and a silicon nitride layer, with a total thickness controlled to 100 nm. In this case, the thickness ratio of the insulating dielectric layer 40 to the back passivation layer 70 is 20 nm / 100 nm = 0.2, which falls within the range of 0.06-0.625. In another example, the insulating dielectric layer 40 can be a silicon oxynitride layer with a thickness of 50 nm, and the back passivation layer 70 can be an aluminum oxide layer and / or a silicon nitride layer, with a total thickness of 100 nm. In this case, the thickness ratio of the insulating dielectric layer 40 to the back passivation layer 70 is 50 nm / 100 nm = 0.5, which also falls within the range of 0.06-0.625.

[0085] Thus, by further optimizing the thickness range of both materials, the interlayer stress matching performance can be further improved, the risk of cracking and delamination can be further reduced, and the reliability can be improved. At the same time, it can also avoid poor insulation performance caused by the insulating dielectric layer 40 being too thin.

[0086] In some embodiments, the thickness of the first passivation layer 20 and the second passivation layer 50 can be 1 nm to 5 nm. This avoids the passivation effect being poor due to the first passivation layer 20 and the second passivation layer 50 being too thin, and also avoids the tunneling efficiency being low or even impossible due to the thickness of both being too thick.

[0087] Specifically, the thickness of the first passivation layer 20 and the second passivation layer 50 may be, for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm, 3nm, 3.2nm, 3.4nm, 3.6nm, 3.8nm, 4nm, 4.2nm, 4.4nm, 4.6nm, 4.8nm, 5nm, or other values ​​between 1nm and 5nm.

[0088] In some embodiments, the thickness ratio of the insulating dielectric layer 40 to the second passivation layer 50 can be 2-50, such as 2, 4, 6, 8, 10, 15, 20, 25, 30, 35, 40, 45, 50, or other values ​​between 2 and 50. Thus, by optimizing the thickness of both layers, setting the thickness of the insulating dielectric layer 40 to be 2-50 times the thickness of the second passivation layer 50, it is possible to avoid the insulating dielectric layer 40 being too thin, resulting in poor insulation and passivation effects, and to avoid the insulating dielectric layer 40 being too thick, resulting in increased costs and greater light absorption. Furthermore, it also avoids excessive processing difficulties in subsequent steps.

[0089] For example, in some embodiments, the insulating dielectric layer 40 may be a silicon oxide layer with a thickness of 20 nm, while the second passivation layer 50 may be a silicon oxide layer with a thickness of 4 nm. In this configuration, the thickness ratio of the insulating dielectric layer 40 to the second passivation layer 50 is 5, falling within the range of 2-50. In this case, the thinner second passivation layer 50 can provide effective passivation while ensuring carrier tunneling efficiency, while the thicker insulating dielectric layer 40 can provide excellent interface passivation and electrical insulation properties.

[0090] In some embodiments, in the back contact battery 100, a front passivation layer (not shown) may be provided on the front side of the silicon substrate 10, and the material of the insulating dielectric layer 40 is different from the material of the front passivation layer. For example, in some embodiments, the insulating dielectric layer 40 may be a silicon oxide layer, and the front passivation layer may be at least one of a silicon nitride layer and / or an aluminum oxide layer.

[0091] In this way, by using different materials, the passivation effect of the entire silicon substrate 10 can be effectively improved, thereby improving the efficiency of the back contact cell 100.

[0092] Please see Figure 3 and Figure 4 In some embodiments, the surface of the third region 123 is recessed into the silicon substrate 10 relative to the surface of the first region 121, and the surface of the second region 122 is recessed into the silicon substrate 10 relative to the surface of the third region 123.

[0093] Specifically, the surface of the third region 123 is recessed into the silicon substrate 10 compared to the surface of the first region 121, meaning that the surface of the third region 123 is closer to the front surface 11 of the silicon substrate 10 than the surface of the first region 121. This recessed structure forms a stepped surface, creating a height difference between the first region 121 and the third region 123. Similarly, the surface of the second region 122 is recessed into the silicon substrate 10 compared to the surface of the third region 123, meaning that the surface of the second region 122 is closer to the front surface 11 of the silicon substrate 10 than the surface of the third region 123. This further forms a multi-level stepped surface, creating a progressively increasing height difference between the first region 121, the third region 123, and the second region 122.

[0094] Thus, on the one hand, the surface of the third region 123 is recessed into the silicon substrate 10 relative to the surface of the first region 121. It can be concluded that in the actual manufacturing process, after the first passivation layer 20 and the first doped layer 30 are formed to cover the back side 12, the portion of the first passivation layer 20 and the first doped layer 30 located on the third region 123 has been completely removed, so that the third region 123 does not have the first doped layer 30, thereby improving the insulation performance. On the other hand, the surface of the second region 122 is recessed into the silicon substrate 10 relative to the third region 123. It can be concluded that in the actual manufacturing process, after the insulating dielectric layer 40 covering the first doped layer 30 and the second region 122 is formed, the insulating dielectric layer 40 on the second region 122 has been completely removed, thereby preventing the second doped layer 60 from failing to form an effective conductive connection with the silicon substrate 10.

[0095] On the other hand, a stepped recessed structure is formed on the back side 12 of the silicon substrate 10, that is, the surface of the third region 123 is recessed into the silicon substrate 10 relative to the surface of the first region 121, and the surface of the second region 122 is recessed into the silicon substrate 10 relative to the surface of the third region 123, thereby providing an optimized physical interface for each layer of the back contact cell 100. This multi-level recessed structure allows the first region 121, the third region 123 and the second region 122 to have different heights in the vertical direction, forming a non-flat substrate. After the first passivation layer 20 and the first doped layer 30 are deposited, when the second passivation layer 50, the second doped layer 60, the insulating dielectric layer 40 and the back passivation layer 70 are sequentially deposited on these stepped regions, the recessed structure can effectively disperse and release the mechanical stress caused by the difference in the thermal expansion coefficients of different materials, and avoid layer cracking or peeling caused by stress concentration. This structured back 12 design allows each functional layer to be integrated more stably and efficiently on the silicon substrate 10, thereby improving the overall performance of the back contact cell 100.

[0096] In some embodiments, the depth H1 of the third region 123 recessed into the silicon substrate 10 relative to the first region 121 can be 1nm-5000nm, i.e., 1nm-5um; the depth H2 of the second region 122 recessed into the silicon substrate 10 relative to the third region 123 can be 1nm-5000nm, i.e., 1nm-5um.

[0097] Thus, by optimizing and controlling the recess depth of the third region 123 relative to the first region 121 and the recess depth of the second region 122 relative to the third region 123 within the aforementioned range, it can be ensured that the subsequently deposited insulating dielectric layer 40, second passivation layer 50, second doped layer 60, and back passivation layer 70 can cover these stepped surfaces with better thickness and morphology, avoiding layer cracking or peeling caused by stress concentration. Furthermore, the second region 122 is recessed into the silicon substrate 10 more deeply than the third region 123. Therefore, by setting the recess depth of the third region 123 relative to the first region 121 and the recess depth of the second region 122 relative to the third region 123 within the aforementioned range, it is possible to prevent the surface of the second region 122 from being recessed too deeply into the silicon substrate 10, which could reduce the strength of the silicon substrate 10 and increase the risk of wafer cracking. In other words, this setting can reduce the risk of wafer cracking.

[0098] Specifically, in such an embodiment, the depth H1 of the third region 123 recessed into the silicon substrate 10 relative to the first region 121 can be, for example, 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 500nm, 1000nm, 1500nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, or other values ​​between 1nm and 5000nm. The depth H2 of the second region 122 recessed into the silicon substrate 10 relative to the third region 123 can be, for example, 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 500nm, 1000nm, 1500nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, or other values ​​between 1nm and 5000nm.

[0099] Please see Figure 4 In some embodiments, the width L1 of the third region 123 can be 10um-600um. The width L1 of the third region 123 refers to the size of the third region 123 in the arrangement direction of the first region 121, the third region 123 and the second region 122, and this width determines the physical spacing between the first doped layer 30 and the second doped layer 60.

[0100] Thus, by limiting the width L1 of the third region 123 to the range of 10µm-600µm, the charge carrier transport path can be optimized. If the width L1 of the third region 123 is too small, it may lead to insufficient electrical isolation between the first doped layer 30 and the second doped layer 60, increasing the risk of leakage current and interface recombination. Conversely, if the width L1 of the third region 123 is too large, it will increase the transport distance of minority carriers to the collecting electrode, resulting in increased series resistance, which in turn reduces short-circuit current and overall conversion efficiency. Therefore, by controlling the width L1 of the third region 123 within the specific range of 10µm-600µm, sufficient electrical isolation between the first doped layer 30 and the second doped layer 60 can be ensured, while minimizing losses in the carrier transport path, thereby enabling photogenerated carriers to be efficiently collected by the first electrode 80 and the second electrode 90. In other words, this configuration allows for optimal electrical isolation between the first doped layer 30 and the second doped layer 60, while also avoiding the problem of extended carrier transport paths caused by an excessively wide third region 123, thus ensuring that photogenerated carriers can be efficiently collected with minimal loss.

[0101] Specifically, in such an embodiment, the width L1 of the third region 123 may be, for example, 10um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 150um, 200um, 250um, 300um, 350um, 400um, 450um, 500um, 550um, 600um, or other values ​​between 10um and 600um.

[0102] In some embodiments, there are multiple first regions 121, second regions 122, and third regions 123; the first regions 121 and second regions 122 are arranged alternately along a first direction, and a third region 123 is located between adjacent first regions 121 and second regions 122; wherein the ratio between the sum of the areas of all third regions 123 and the area of ​​the entire back surface 12 is 0.01-0.6, for example, 0.01, 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, and 0.6. It should be noted that the ratio between the sum of the areas of all third regions 123 and the area of ​​the entire back surface 12 refers to the ratio between the sum of the projected areas of all third regions 123 and the projected area of ​​the back surface 12 in the thickness direction.

[0103] Thus, by setting the ratio between the sum of the areas of all the third regions 123 and the area of ​​the entire back surface 12 in the range of 0.01-0.6, it is possible to avoid insufficient insulation and low bifaciality caused by the area of ​​the insulating region being too small, and also to avoid the effective doping area being reduced due to the area of ​​the insulating region being too large, thereby affecting the current collection efficiency. In some embodiments, the surface of the third region 123 may be velvety. Thus, by setting the surface of the third region 123 to velvety, the light trapping effect can be improved, and the light utilization rate can be increased.

[0104] Of course, it is understandable that in some possible embodiments, the surface of the third region 123 may also be a polished surface, and no specific limitation is made here.

[0105] Please combine Figure 3 and Figure 4In some embodiments, the surface of the third region 123 is recessed into the silicon substrate 10 compared to the surface of the first region 121. The silicon substrate 10 has a first connecting surface 101 connecting the surfaces of the first region 121 and the third region 123, and the first connecting surface 101 is textured. It is easy to understand that because the recessed depths of the first region 121 and the third region 123 are different, a surface structure with varying heights is formed on the silicon substrate 10. The first connecting surface 101 refers to the surfaces of the first region 121 and the third region 123 at different depths. The first connecting surface 101 can be a vertical surface, an inclined surface, or an irregular surface; no specific limitation is made here.

[0106] Thus, in the back contact battery 100, the first connecting surface 101 is set as a velvety surface. Whether the light directly incident from the back side 12 or the light that has undergone multiple reflections inside the battery, it will be further reflected when it shines on these sides, thereby further improving the light trapping effect and improving the light utilization rate.

[0107] Of course, it is understood that in some possible embodiments, the first connecting surface 101 may also be a polished surface, and no specific limitation is made here.

[0108] Please combine Figure 3 and Figure 4 In some embodiments, the surface of the second region 122 is recessed into the silicon substrate 10 compared to the surface of the third region 123. The silicon substrate 10 has a second connecting surface 102 connecting the surfaces of the second region 122 and the third region 123, and the second connecting surface 102 is textured. It is easy to understand that because the recessed depths of the second region 122 and the third region 123 are different, a surface structure with varying heights is formed on the silicon substrate 10. The second connecting surface 102 refers to the surfaces of the second region 122 and the third region 123 at different depths. The second connecting surface 102 can be a vertical surface, an inclined surface, or an irregular surface; no specific limitation is made here.

[0109] Thus, in the back contact battery 100, the second connecting surface 102 is set as a velvety surface. Whether the light directly incident from the back side 12 or the light that has undergone multiple reflections inside the battery, it will be further reflected when it shines on these sides, thereby further improving the light trapping effect and improving the utilization rate of light.

[0110] Of course, it is understood that in some possible embodiments, the second connecting surface 102 may also be a polished surface, and no specific limitation is made here.

[0111] Please see Figure 5In some embodiments, the portion of the insulating dielectric layer 40 located on the overlapping region 32 has a contact hole 41, the first doped layer 30 is exposed from the contact hole 41, the second passivation layer 50 and the second doped layer 60 at least partially fill the contact hole 41, the second passivation layer 50 is in contact with the first doped layer 30 at the contact hole 41, and the second doped layer 60 is connected to the first doped layer 30 at the contact hole 41 through the second passivation layer 50.

[0112] Thus, by forming a contact hole 41 in the portion of the insulating dielectric layer 40 located on the overlapping region 32, the underlying first doped layer 30 is partially exposed. Subsequently, when depositing the second passivation layer 50 and the second doped layer 60, these layers will enter and at least partially fill the contact hole 41, and the first doped layer 30 and the second doped layer 60 can achieve conductivity at the location of the contact hole 41, thereby forming a local leakage current composite contact structure, thereby improving the hot spot resistance of the back contact battery 100.

[0113] Specifically, the contact hole 41 can be formed by laser or chemical etching. In such an embodiment, between the preparation of the second passivation layer 50 and the second doped layer 60, the contact hole 41 can be formed on the portion of the insulating dielectric layer 40 located on the overlapping region 32 by laser etching or other means, and then the second passivation layer 50 and the second doped layer 60 are prepared. In this case, the second passivation layer 50 contacts the first doped layer 30 at the contact hole 41, and the second doped layer 60 is also partially located at the contact hole 41 and forms a leakage current composite contact with the first doped layer 30 through the second passivation layer 50.

[0114] In the embodiments of this application, there are multiple first regions 121. On a single first region 121, the number of contact holes 41 can be single or multiple, and there is no specific limitation here. In the back contact battery 100, all the insulating dielectric layers 40 on the first regions 121 may have contact holes 41, or only some of the insulating dielectric layers 40 on the first regions 121 may have contact holes 41, and there is no specific limitation here.

[0115] Furthermore, in some embodiments, in the back contact battery 100, the ratio between the sum of the areas of all contact holes 41 and the area of ​​the entire back surface 12 is 10. -8 -10 -3 It should be noted that "the area of ​​contact hole 41" refers to the orthographic projection area of ​​contact hole 41 in the thickness direction, and the area of ​​the back surface 12 also refers to the orthographic projection area in the thickness direction.

[0116] Thus, by setting the area ratio of the contact hole 41 within this reasonable range, it is possible to effectively avoid the poor performance of hot spot resistance caused by the small area ratio of the contact hole 41, and also to avoid the excessive composite loss caused by the large area ratio of the contact hole 41.

[0117] Please see Figure 6 In some embodiments, the silicon substrate 10 has a first inner expansion layer 103 formed in a first region 121, and a second inner expansion layer 104 formed in a second region 122. The second inner expansion layer 104 and the first inner expansion layer 103 are separated by a third region 123.

[0118] In this way, recombination caused by the first inner expansion layer 103 and the second inner expansion layer 104 contacting within the bulk region can be avoided, thereby significantly reducing carrier recombination losses within the bulk region and improving the efficiency of the back contact battery 100. Specifically, in such an embodiment, the first inner expansion layer 103 is diffused within the first region 121 of the silicon substrate 10 during the fabrication of the first doped layer 30, and its doping element is the same as that in the first doped layer 30. The second inner expansion layer 104 is diffused within the second region 122 during the fabrication of the second doped layer 60, and its doping element is the same as that in the second doped layer 60.

[0119] In the description of this specification, the references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0120] Furthermore, the above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate having opposing front and back sides, the back side including a first region, a second region, and a third region located between the first region and the second region; A first passivation layer and a first doped layer are sequentially stacked on the first region, wherein the surface of the first doped layer facing away from the silicon substrate includes a contact region and an overlap region. An insulating dielectric layer is stacked on the third region and extends to the overlapping region; A second passivation layer and a second doped layer are sequentially stacked on the second region, the second doped layer extending to the third region and the overlapping region and covering the insulating dielectric layer; A back passivation layer covers the second doped layer and the contact region, and the back passivation layer contacts the first doped layer in the contact region; and A first electrode and a second electrode, wherein the first electrode is located in the contact area and at least partially penetrates the back passivation layer to make conductive contact with the first doped layer, and the second electrode is located in the second region and at least partially penetrates the back passivation layer to make conductive contact with the second doped layer.

2. The back contact battery according to claim 1, characterized in that, The second passivation layer also extends to the third region and the overlapping region and is located between the second doped layer and the insulating dielectric layer.

3. The back contact battery according to claim 1, characterized in that, The insulating dielectric layer includes at least one of the following: silicon oxide layer, silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbonate layer, silicon oxycarbonitride layer, aluminum oxide layer, amorphous silicon layer, borosilicate glass layer, phosphosilicate glass layer, and polycrystalline silicon layer.

4. The back contact battery according to claim 1, characterized in that, The back passivation layer includes at least one of the following: silicon oxide layer, silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbonate layer, silicon oxycarbonitrile layer, and aluminum oxide layer.

5. The back contact battery according to claim 1, characterized in that, The insulating dielectric layer is made of a different material than the back passivation layer.

6. The back contact battery according to claim 1, characterized in that, The thickness of the insulating dielectric layer is 5nm-300nm.

7. The back contact battery according to claim 1, characterized in that, The thickness of the back passivation layer is 50nm-400nm.

8. The back contact battery according to claim 1, characterized in that, The thickness ratio of the insulating dielectric layer to the back passivation layer is 0.0125-6.

9. The back contact battery according to claim 1, characterized in that, The thickness ratio of the insulating dielectric layer to the second passivation layer is 2-50.

10. The back contact battery according to claim 1, characterized in that, The silicon substrate has a front passivation layer on its front side, and the material of the insulating dielectric layer is different from the material of the front passivation layer.

11. The back contact battery according to claim 1, characterized in that, The surface of the third region is recessed into the silicon substrate relative to the surface of the first region, and the surface of the second region is recessed into the silicon substrate relative to the surface of the third region.

12. The back contact battery according to claim 11, characterized in that, The third region is recessed into the silicon substrate to a depth of 1nm-5000nm compared to the first region; The second region is recessed into the silicon substrate to a depth of 1nm-5000nm compared to the third region.

13. The back contact battery according to claim 1, characterized in that, The width of the third region is 10um-600um.

14. The back contact battery according to claim 1, characterized in that, There are multiple first regions, second regions, and third regions; The first region and the second region are arranged alternately along a first direction, and the third region is located between adjacent first regions and second regions. The ratio between the sum of the areas of all the third regions and the area of ​​the entire back surface is 0.01-0.

6.

15. The back contact battery according to claim 1, characterized in that, The surface of the third region is either velvety or polished.

16. The back contact battery according to claim 1, characterized in that, The surface of the third region is recessed into the silicon substrate relative to the surface of the first region. The silicon substrate has a first connecting surface that connects the surface of the first region and the surface of the third region. The first connecting surface is a textured or polished surface.

17. The back contact battery according to claim 1, characterized in that, The surface of the second region is recessed into the silicon substrate relative to the surface of the third region. The silicon substrate has a second connecting surface that connects the surfaces of the second region and the third region. The second connecting surface is a textured or polished surface.

18. The back contact battery according to claim 1, characterized in that, The portion of the insulating dielectric layer located on the overlapping region has a contact hole, the first doped layer is exposed from the contact hole, the second passivation layer and the second doped layer at least partially fill the contact hole, the second passivation layer contacts the first doped layer at the contact hole, and the second doped layer is connected to the first doped layer at the contact hole through the second passivation layer.

19. The back contact battery according to claim 18, characterized in that, In the back contact battery, the ratio between the sum of the areas of all the contact holes and the total area of ​​the back surface is 10. -8 -10 -3 .

20. The back contact battery according to claim 1, characterized in that, The silicon substrate has a first inner expansion layer formed in the first region, and a second inner expansion layer formed in the second region, wherein the second inner expansion layer and the first inner expansion layer are separated by the third region.

21. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1-20.

22. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 21.

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