Light emitting diode for improving scribing damage and preparation method thereof
By designing a chamfered structure at the junction of adjacent sidewalls of the LED chip, the problems of chipping and microcracks caused by stress concentration during laser scribing are solved, resulting in higher scribing yield and reliability, and ensuring chip quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-12
- Publication Date
- 2026-04-03
AI Technical Summary
In the manufacturing of LED chips, localized chipping and microcrack defects caused by stress concentration during the laser scribing process affect the scribing yield and reliability.
The junction of adjacent sidewalls of the LED is designed with a first chamfer with a radius of 18μm to 26μm. Pads and passivation layers are set on the epitaxial layer. The sidewalls of the pads and the sidewalls of the passivation layer are designed with a second chamfer and a third chamfer, respectively, to form a gradient transition structure and reduce stress concentration.
It effectively disperses stress, avoids localized chipping and microcracks, improves dicing yield and reliability, ensures a smooth dicing process, reduces crack propagation, and improves chip quality.
Smart Images
Figure CN121793533A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved dicing damage and a method for its fabrication. Background Technology
[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. Due to their high luminous efficiency, high power, and excellent heat dissipation, LED chips are widely used in lighting and display fields.
[0003] In related technologies, when manufacturing LED chips, it is necessary to divide the epitaxial layer array grown on a large-size substrate into multiple independent light-emitting chips. The division process requires a laser dicing machine to emit a laser beam, which is used to directionally cut the epitaxial layer, ultimately decomposing it into multiple light-emitting chips.
[0004] Because most light-emitting chips adopt a rectangular design and are not optimized for the mechanical stress characteristics of the laser scrubbing process, during actual scrubbing, the high-energy laser is focused on the corner area of the light-emitting chip. Due to the geometric change, the stress is highly concentrated, exceeding the material's tolerance threshold, which in turn causes local chipping or microcrack defects, affecting the chip scrubbing yield and reliability. Summary of the Invention
[0005] This disclosure provides a method for improving the scratch-damage performance of light-emitting diodes (LEDs) and its fabrication, which can mitigate the problem of localized chipping of LEDs during laser scratching, thereby improving the scratching yield and reliability of LEDs. The technical solution is as follows: On one hand, embodiments of this disclosure provide a light-emitting diode, the light-emitting diode including an epitaxial layer, wherein the junction of two adjacent sidewalls on the epitaxial layer has a first chamfer, the radius of the first chamfer being 18 μm to 26 μm.
[0006] In one implementation of this disclosure, the peripheral edge of the epitaxial layer is rectangular, and the ratio of the radius of the first chamfer to the long side of the peripheral edge of the epitaxial layer is 0.04 to 0.06.
[0007] In another implementation of this disclosure, the ratio of the radius of the first chamfer to the shorter side of the peripheral edge of the epitaxial layer is 0.16 to 0.26.
[0008] In another implementation of the present disclosure, the light-emitting diode further includes a pad located on the epitaxial layer, and at least a portion of the pad is located in a corner region of the epitaxial layer, wherein the sidewall of the pad located in the corner region of the epitaxial layer has a second chamfer.
[0009] In another implementation of the present disclosure, the radius of the second chamfer is less than or equal to the radius of the first chamfer, and the radius of the second chamfer is 18 μm to 26 μm.
[0010] In another implementation of the present disclosure, the light-emitting diode further includes a passivation layer covering the surface of the epitaxial layer and the sidewalls of the epitaxial layer, and the area of the first chamfer covered by the passivation layer has a third chamfer with a radius of 18 μm to 26 μm.
[0011] In another implementation of this disclosure, the passivation layer has a plurality of blind holes spaced apart on the surface corresponding to the third chamfer, and the depth of the blind holes is less than the thickness of the passivation layer.
[0012] In another implementation of the present disclosure, the aperture of the blind hole is 1 μm to 5 μm.
[0013] On the other hand, embodiments of this disclosure provide a method for fabricating a light-emitting diode, the method comprising: fabricating an epitaxial layer on a substrate; and patterning the epitaxial layer such that a first chamfer is formed at the junction of two adjacent sidewalls on the epitaxial layer, the radius of the first chamfer being 18 μm to 26 μm.
[0014] In another implementation of this disclosure, after patterning the epitaxial layer, the method further includes: forming a passivation layer on the epitaxial layer, the passivation layer covering the surface and sidewalls of the epitaxial layer, the passivation layer covering the region of the first chamfer having a third chamfer, the radius of the third chamfer being 18 μm to 26 μm; forming a pad on the passivation layer, such that the pad is connected to the epitaxial layer through a via of the passivation layer, at least a portion of the pad being located in the corner region of the epitaxial layer, the sidewall of the pad located in the corner region of the epitaxial layer having a second chamfer, the radius of the second chamfer being less than or equal to the radius of the first chamfer, the radius of the second chamfer being 18 μm to 26 μm.
[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The light-emitting diode provided in this disclosure designes a first chamfer at the junction of adjacent sidewalls, replacing the sharp right angles in related technologies with the arc transition of the first chamfer. This transforms the stress field in the laser-affected area from a concentrated peak distribution to a gradual gradient distribution, resulting in a smoother stress distribution. Furthermore, the radius of the first chamfer is increased to 18μm to 26μm, which significantly reduces the maximum principal stress at the corner compared to a right-angle structure, and also significantly reduces the area of the high-stress region. The stress concentration effect is effectively dispersed over a larger arc-shaped area, preventing the material from exceeding its tolerance threshold and avoiding localized chipping or microcrack defects.
[0016] Meanwhile, the energy focusing intensity of the laser spot at the corner is inversely proportional to the effective area. Increasing the chamfer radius increases the equivalent spot area at the corner under the same laser parameters, while decreasing the energy density per unit area. This avoids material vaporization and cracking caused by localized overheating, transforming the cutting process from impact-driven fracture to gradual separation. In other words, it reduces the energy density concentration of the laser beam at the corner, making the cutting process smoother and preventing chipping.
[0017] Furthermore, unlike sharp-corner structures, the curved surface structure's geometry alters the smooth path of crack propagation along grain boundaries. When a crack encounters a curved surface structure, due to the geometric constraints of the curved surface, the crack cannot continue propagating along the original low-energy grain boundary path and must seek a new direction of propagation. At this point, the crack will turn towards the low-energy release direction, thereby inhibiting the longitudinal penetration and lateral propagation of the crack, fundamentally suppressing the propagation of microcracks. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure; Figure 2 It is along Figure 1 A cross-sectional view of the light-emitting diode taken from section AA; Figure 3 This is a schematic diagram of the structure of a corner region of a light-emitting diode provided in an embodiment of this disclosure; Figure 4 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure.
[0020] The markings in the diagram are explained as follows: 10. Epitaxial layer; 11. First chamfer; 20. Solder pad; 21. Second chamfer; 30. Passivation layer; 31. Third chamfer; 32. Blind via; 41. Current blocking layer; 42. Current spreading layer; 51. First electrode; 52. Second electrode; 60. Substrate. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0023] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 It is along Figure 1 A cross-sectional view of the light-emitting diode taken from section AA.
[0024] like Figure 1 , 2 As shown, the light-emitting diode includes an epitaxial layer 10, and the junction of two adjacent sidewalls on the epitaxial layer 10 has a first chamfer 11. The radius of the first chamfer 11 is 18 μm to 26 μm.
[0025] The light-emitting diode provided in this embodiment features a first chamfer 11 at the junction of adjacent sidewalls. This chamfer 11, with its curved surface transition, replaces the sharp right angles of related technologies. Consequently, the stress field in the laser-affected area changes from a concentrated peak distribution to a gradual gradient distribution, resulting in a smoother stress distribution. Furthermore, the radius of the first chamfer 11 is increased to 18μm to 26μm, significantly reducing the maximum principal stress at the corner compared to a right-angle structure. The area of the high-stress region is also significantly reduced, effectively dispersing the stress concentration effect over a larger curved surface area. This prevents the material from exceeding its tolerance threshold and avoids localized chipping or microcrack defects.
[0026] Meanwhile, the energy focusing intensity of the laser spot at the corner is inversely proportional to the effective area. Increasing the chamfer radius increases the equivalent spot area at the corner under the same laser parameters, while decreasing the energy density per unit area. This avoids material vaporization and cracking caused by localized overheating, transforming the cutting process from impact-driven fracture to gradual separation. In other words, it reduces the energy density concentration of the laser beam at the corner, making the cutting process smoother and preventing chipping.
[0027] Furthermore, unlike sharp-corner structures, the curved surface structure's geometry alters the smooth path of crack propagation along grain boundaries. When a crack encounters a curved surface structure, due to the geometric constraints of the curved surface, the crack cannot continue propagating along the original low-energy grain boundary path and must seek a new direction of propagation. At this point, the crack will turn towards the low-energy release direction, thereby inhibiting the longitudinal penetration and lateral propagation of the crack, fundamentally suppressing the propagation of microcracks.
[0028] Optionally, such as Figure 1 As shown, the peripheral edge of the epitaxial layer 10 is rectangular, and the ratio of the radius of the first chamfer 11 to the long side of the peripheral edge of the epitaxial layer 10 is 0.04 to 0.06.
[0029] In this embodiment, the peripheral edge of the epitaxial layer 10 is rectangular, meaning the lines connecting the sides of the epitaxial layer 10 form a rectangle. By setting the ratio of the radius of the first chamfer 11 to the long side of the peripheral edge of the epitaxial layer 10 between 0.04 and 0.06, the proportion of the first chamfer 11 radius on the long side is significantly increased, resulting in a substantial increase in the radius of the first chamfer 11. A larger chamfer radius can more effectively smooth stress distribution, dispersing stress that was originally concentrated at the apex to a wider arc surface, thus reducing stress concentration. Simultaneously, it reduces the energy density concentration of the laser beam at the corners, making the cutting process smoother. Moreover, it can better disperse and absorb mechanical stress, suppressing the generation and propagation of chipping and microcracks at the source, thereby improving the chip scratch yield and reliability, providing a strong guarantee for manufacturing high-quality LED chips.
[0030] For example, the ratio of the radius of the first chamfer 11 to the long side of the peripheral edge of the epitaxial layer 10 is 0.05.
[0031] If the ratio of the radius of the first chamfer 11 to the long side of the peripheral edge of the epitaxial layer 10 is less than 0.05, the chamfer radius is relatively small, the stress dispersion effect is limited, and the laser energy is still easily concentrated, making it difficult to fully suppress cracks. On the other hand, if the ratio of the radius of the first chamfer 11 to the long side of the peripheral edge of the epitaxial layer 10 is greater than 0.05, although the stress dispersion is good, it may increase the difficulty of process control and cost.
[0032] Optionally, such as Figure 1 As shown, the ratio of the radius of the first chamfer 11 to the short side of the peripheral edge of the epitaxial layer 10 is 0.16 to 0.26.
[0033] By setting the ratio of the radius of the first chamfer 11 to the shorter side of the peripheral edge of the epitaxial layer 10 between 0.16 and 0.26, the proportion of the first chamfer 11 radius on the shorter side is significantly increased, resulting in a substantial increase in the radius of the first chamfer 11. A larger chamfer radius can more effectively smooth stress distribution, dispersing the stress at the sharp points during laser cutting to a wider arc area, significantly reducing stress peaks. Simultaneously, it reduces the energy density concentration of the laser beam at the corners, making the cutting process smoother. Furthermore, a larger chamfer can better absorb and disperse mechanical stress, fundamentally inhibiting crack initiation and propagation, thereby improving chip scratch yield and long-term reliability.
[0034] For example, the ratio of the radius of the first chamfer 11 to the short side of the peripheral edge of the epitaxial layer 10 is 0.2.
[0035] When the ratio of the radius of the first chamfer 11 to the shorter side of the peripheral edge of the epitaxial layer 10 is 0.2, the chamfer radius is relatively moderate and reasonable compared to the shorter side, achieving excellent stress dispersion. During laser scribing, the stress generated by the high-energy laser focusing at the corner can be evenly distributed over a larger arc area, greatly reducing stress concentration.
[0036] Optionally, such as Figure 1 As shown, the light-emitting diode also includes a pad 20 located on the epitaxial layer 10, and at least a portion of the pad 20 is located in the corner region of the epitaxial layer 10. The sidewall of the pad 20 located in the corner region of the epitaxial layer 10 has a second chamfer 21.
[0037] In the above implementation, the pad 20 is partially disposed in the corner region of the epitaxial layer 10 and a second chamfer 21 is provided on its sidewall. Since the corner region is usually a critical area where stress concentration and problems are prone to occur during laser scribing, the pad 20 is disposed here with the second chamfer 21. The second chamfer 21 effectively disperses the stress of the pad 20, avoiding microcracks or peeling of the pad 20 and the epitaxial layer 10 below the pad due to stress concentration, thereby enhancing the stability of the chip structure.
[0038] Furthermore, during the laser scribing process, laser energy tends to concentrate in the corner area. The second chamfer 21 can reduce the energy density of the laser in this area, reduce the damage to the epitaxial layer 10 and pad 20 caused by excessive energy concentration, make the cutting process more stable and controllable, and improve the scribing yield.
[0039] Optionally, the radius of the second chamfer 21 is less than or equal to the radius of the first chamfer 11, and the radius of the second chamfer 21 is 18 μm to 26 μm.
[0040] By controlling the radius of the second chamfer 21 within the aforementioned range, the stress in the corner region of the pad 20 can be effectively dispersed, preventing stress concentration from causing microcracks. Simultaneously, by controlling the radius of the second chamfer 21 to not exceed the radius of the first chamfer 11, the outer contour of the pad 20 located in the corner region can be prevented from exceeding the outer contour of the epitaxial layer 10. Since the laser path will deviate laterally during the actual laser scrubbing process, ensuring that the pad 20 does not exceed the outer contour of the epitaxial layer 10 ensures that the laser will not irradiate the pad 20, thus protecting the pad 20.
[0041] Optionally, such as Figure 1 As shown, the light-emitting diode also includes a passivation layer 30, which covers the surface of the epitaxial layer 10 and the sidewalls of the epitaxial layer 10. The area covered by the passivation layer 30 with a first chamfer 11 has a third chamfer 31 with a radius of 18 μm to 26 μm.
[0042] By designating the area surrounding the first chamfer 11 with the passivation layer 30 as the third chamfer 31, a gradient transition structure is formed between the third chamfer 31, the first chamfer 11, and the second chamfer 21, effectively alleviating the stress concentration problem of the passivation layer 30 in the corner region. Furthermore, the 18μm to 26μm radius of the third chamfer 31 on the passivation layer 30 enables a smooth stress transition, dispersing the originally concentrated stress to a larger arc area, thus improving the integrity and protective effect of the passivation layer 30.
[0043] Meanwhile, the third chamfer 31 enables the chamfer of the passivation layer 30 and the epitaxial layer 10 to form a synergistic protection, reducing the abnormal accumulation of laser energy at the corner and avoiding damage to the passivation layer 30 or the epitaxial layer 10 caused by energy concentration.
[0044] Figure 3This is a schematic diagram of the structure of a corner region of a light-emitting diode provided in an embodiment of this disclosure. For example... Figure 3 As shown, the surface of the passivation layer 30 corresponding to the third chamfer 31 has a plurality of blind holes 32 arranged at intervals, and the depth of the blind holes 32 is less than the thickness of the passivation layer 30.
[0045] By setting multiple spaced blind holes 32, the continuity of the material can be disrupted, creating a micro-flexible buffer zone in the stress concentration area. When external force or thermal stress is applied to the third chamfer 31, these micropores absorb and disperse energy through controllable elastic deformation, reducing the local stress peak and effectively avoiding the brittle cracking problem that easily occurs at corners in traditional continuous passivation layers 30.
[0046] Furthermore, the connecting walls between the blind holes 32 form a non-linear propagation path, forcing multiple deflections and bifurcations during crack propagation. This structure forces the crack to traverse more interfaces and walls, effectively increasing the resistance to crack propagation.
[0047] Meanwhile, the depth of the blind hole 32 is controlled within the thickness of the passivation layer 30. For example, the ratio of the depth of the blind hole 32 to the thickness of the passivation layer 30 is 0.5 to 0.7. This maintains the complete protective function of the underlying passivation layer 30 and achieves a balance between stress regulation and mechanical strength through precise microstructure design, avoiding protection failure caused by excessive thinning.
[0048] Optionally, the diameter of the blind aperture 32 is 1 μm to 5 μm, and the spacing between the blind apertures 32 is 3 μm to 5 μm.
[0049] In the above implementation, the size of the blind vias 32 is small, and the reasonable spacing of the blind vias 32 can form a dense and uniform microstructure network. When the chip is subjected to external stress, these tiny blind vias 32 can effectively disperse the stress and prevent stress concentration at a certain point. Furthermore, the arrangement spacing of 3μm to 5μm can make the stress more evenly distributed throughout the passivation layer 30, reducing the situation of excessive local stress, thereby reducing the probability of crack formation due to stress concentration.
[0050] For example, the diameter of the blind hole 32 is 2μm, and the spacing between the blind holes 32 is 3.5μm.
[0051] Alternatively, the blind hole 32 may be filled with polydimethylsiloxane and epoxy resin.
[0052] Among them, low-modulus polymers such as polydimethylsiloxane and epoxy resin have low elastic modulus, forming a modulus gradient with the surrounding passivation layer 30 material. When the chip is subjected to stress, they can undergo elastic deformation, playing a role in buffering and absorbing energy, further dispersing stress and reducing stress concentration. Moreover, the polymer material has good flexibility and insulation, which can enhance the overall crack propagation resistance of the passivation layer 30 without affecting the electrical performance of the chip.
[0053] Optionally, the blind hole 32 may be filled with nano-silica and nano-silicon carbide particles.
[0054] Because nanoparticles possess high hardness and strength, they can enhance the mechanical properties of composite materials. When filled in blind vias 32, nanoparticles can prevent crack propagation and improve the fracture toughness of the material. Simultaneously, the presence of nanoparticles can also improve the thermal expansion properties of the material, reduce thermal stress caused by temperature changes, and further enhance the stability of the chip under different environments.
[0055] Optionally, the blind aperture 32 can be filled with silver nanoparticles and gold nanoparticles.
[0056] Metal nanomaterials possess excellent electrical and thermal conductivity. Filling the passivation layer 30 with metal nanomaterials can improve its electrical conductivity and heat dissipation capacity. Furthermore, metal nanomaterials can form a good interfacial bond with the surrounding passivation layer 30 material, enhancing the overall mechanical properties.
[0057] Optionally, such as Figure 1 , 2 As shown, the light-emitting diode also includes a substrate 60, and an epitaxial layer 10 is located on the surface of the substrate 60.
[0058] For example, the substrate 60 is a sapphire substrate 60. The sapphire substrate 60 has high light transmittance, that is, the substrate 60 is a transparent substrate 60. In addition, sapphire material is relatively hard and has relatively stable chemical properties, which enables the light-emitting diode to have good light-emitting effect and stability.
[0059] In this embodiment of the present disclosure, the epitaxial layer 10 includes a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer sequentially stacked on the substrate 60, and the surface of the second semiconductor layer has a groove exposing the first semiconductor layer.
[0060] In this embodiment of the present disclosure, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.
[0061] For example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.
[0062] In this embodiment, the first semiconductor layer is Al.x Ga （1-x） N is a material layer, where X is greater than or equal to 0 and less than or equal to 1.
[0063] For example, when X is 0, the first semiconductor layer is a GaN layer. For instance, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.
[0064] Optionally, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.
[0065] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.
[0066] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.
[0067] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.
[0068] Optionally, such as Figure 2 As shown, the light-emitting diode also includes: a current blocking layer 41, a current spreading layer 42, a first electrode 51, a second electrode 52, and a pad 20.
[0069] like Figure 2 As shown, the current blocking layer 41 is located on the surface of the second semiconductor layer, and the current spreading layer 42 is located on the surface of the second semiconductor layer and covers the current blocking layer 41.
[0070] The first electrode 51 is located in the groove and connected to the first semiconductor layer, and the second electrode 52 is located on the surface of the current spreading layer 42.
[0071] For example, the first semiconductor layer is an n-type layer, the second semiconductor layer is a p-type layer, the first electrode 51 is an n-type electrode, and the second electrode 52 is a p-type electrode.
[0072] like Figure 2 As shown, the passivation layer 30 is located on the substrate 60, and the passivation layer 30 is located on the surface of the first semiconductor layer and the second semiconductor layer, and covers the first electrode 51 and the second electrode 52. The passivation layer 30 also has vias that expose the first electrode 51 and the second electrode 52 respectively.
[0073] The passivation layer 30 has at least two pads 20 on its surface. One part of the pads 20 is connected to the first electrode 51 through a via, and the other part of the pads 20 is connected to the second electrode 52 through a via.
[0074] For example, both the first electrode 51 and the second electrode 52 may include at least one of the following: Al layer, Ag layer, Ni layer, Pt layer, Au layer and AlCu layer.
[0075] For example, both the first electrode 51 and the second electrode 52 may include Al layer, Ti layer, Ni layer, Pt layer and Au layer stacked sequentially.
[0076] For example, the thickness of the Al layer is 1500 angstroms to 2500 angstroms.
[0077] For example, the thickness of the Ti layer is 300 to 700 angstroms.
[0078] For example, the thickness of the Ni layer is 800 angstroms to 1200 angstroms.
[0079] For example, the thickness of the Pt layer is 1500 angstroms to 2500 angstroms.
[0080] For example, the thickness of the Au layer is 6,000 angstroms to 10,000 angstroms.
[0081] Optionally, the pad 20 may include at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.
[0082] The aforementioned metallic materials have excellent heat dissipation properties. Therefore, the pads 20 prepared using these materials also have excellent heat dissipation properties, which can improve the heat dissipation effect of the light-emitting diode.
[0083] Optionally, the pad 20 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked sequentially.
[0084] For example, the thickness of the first Ti layer is 20 to 100 angstroms. For instance, the thickness of the first Ti layer is 50 angstroms.
[0085] For example, the thickness of the Al layer is between 10,000 and 20,000 angstroms. For instance, the thickness of the Al layer is 15,000 angstroms.
[0086] For example, the thickness of the second Ti layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the second Ti layer is 1000 angstroms.
[0087] For example, the thickness of the Pt layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the Pt layer is 1000 angstroms.
[0088] For example, the thickness of the Ni layer is between 60,000 and 80,000 angstroms. For instance, the thickness of the Ni layer is 70,000 angstroms.
[0089] For example, the thickness of the Au layer is between 1500 angstroms and 2500 angstroms. For instance, the thickness of the Au layer is 2000 angstroms.
[0090] Optionally, the passivation layer 30 includes at least one of an aluminum oxide layer, a silicon oxide layer, a titanium oxide layer, and a silicon oxynitride layer.
[0091] For example, the passivation layer 30 includes an aluminum oxide layer.
[0092] Alumina has extremely high dielectric strength, which can effectively withstand the high voltage during LED operation, reduce the risk of passivation layer 30 breakdown, and prevent short circuits between electrodes and pads 20. Furthermore, alumina is chemically stable, resistant to acid and alkali corrosion, and does not easily undergo hydrolysis or oxidation reactions in the humid and hot environment of chip packaging, maintaining its insulating properties over a long period.
[0093] As an example, the thickness of the alumina layer can be from 100 nm to 500 nm.
[0094] For example, the passivation layer 30 includes a silicon oxide layer.
[0095] Silicon oxide has a good match with the thermal expansion coefficient of epitaxial layer 10, resulting in low stress after deposition, which can reduce the risk of cracking or peeling of passivation layer 30 due to thermal stress. Although the dielectric strength of silicon oxide is slightly lower than that of aluminum oxide, the insulation requirements of LEDs can still be met by increasing the thickness, for example, controlling the thickness of silicon oxide to be more than 1 μm.
[0096] As an example, the thickness of the silicon oxide layer can be from 0.5 μm to 2 μm.
[0097] For example, the passivation layer 30 includes a titanium oxide layer.
[0098] Titanium oxide has a high dielectric constant and can act as a field plate in the passivation layer 30. By dispersing the electric field concentration effect at the electrode edge through the high dielectric constant material, the probability of insulation breakdown caused by local high electric field is reduced.
[0099] As an example, the thickness of the titanium oxide layer can be from 50 nm to 200 nm.
[0100] Optionally, the current blocking layer 41 may include at least one of an aluminum oxide layer, a silicon oxide layer, a titanium oxide layer, and a silicon oxynitride layer.
[0101] Optionally, the current spreading layer 42 may include an ITO layer or an IZO layer.
[0102] Figure 4 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 4 As shown, the preparation method includes: S11: Prepare an epitaxial layer on the substrate.
[0103] The epitaxial layer may include a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer sequentially stacked on the substrate.
[0104] S12: Graphical processing of the epitaxial layer to form the first chamfer at the junction of two adjacent sidewalls on the epitaxial layer.
[0105] The radius of the first chamfer is between 18 μm and 26 μm.
[0106] The light-emitting diode fabricated by the method provided in this disclosure features a first chamfer at the junction of adjacent sidewalls. This chamfer, replacing the sharp right angles of related technologies with a smoother, more gradual stress distribution in the laser-affected region, transforms the concentrated peak distribution into a gradual gradient distribution. Furthermore, the radius of the first chamfer is increased to 18 μm to 26 μm, significantly reducing the maximum principal stress at the corner compared to a right-angled structure. The area of high-stress regions is also significantly reduced, effectively dispersing the stress concentration effect over a larger arc-shaped region. This prevents the material from exceeding its tolerance threshold and avoids localized chipping or microcrack defects.
[0107] Meanwhile, the energy focusing intensity of the laser spot at the corner is inversely proportional to the effective area. Increasing the chamfer radius increases the equivalent spot area at the corner under the same laser parameters, while decreasing the energy density per unit area. This avoids material vaporization and cracking caused by localized overheating, transforming the cutting process from impact-driven fracture to gradual separation. In other words, it reduces the energy density concentration of the laser beam at the corner, making the cutting process smoother and preventing chipping.
[0108] Furthermore, unlike sharp-corner structures, the curved surface structure's geometry alters the smooth path of crack propagation along grain boundaries. When a crack encounters a curved surface structure, due to the geometric constraints of the curved surface, the crack cannot continue propagating along the original low-energy grain boundary path and must seek a new direction of propagation. At this point, the crack will turn towards the low-energy release direction, thereby inhibiting the longitudinal penetration and lateral propagation of the crack, fundamentally suppressing the propagation of microcracks.
[0109] Secondly, the chip's continuous and smooth geometric contours allow it to more effectively resist external stresses. During subsequent pick-up, packaging, and service, the chamfered structure enhances the chip's resistance to mechanical and thermal shocks. This optimization strengthens the chip's mechanical robustness and extends its lifespan under high loads or harsh environments.
[0110] Furthermore, the optimized chamfer design directly reduces the chip scrap rate caused by edge chipping during laser scrubbing. Smooth, complete corners reduce microscopic defects, making the chips more compliant with quality inspection standards, thereby improving overall production yield. In addition, this improvement only involves the layout design of the chip mask pattern, which can be achieved by adjusting the chamfer radius graphic data, without modifying existing processes or adding extra equipment. This method is low-cost to implement, does not introduce complex process variables, yet improves the chip's mechanical properties and yield.
[0111] The process of preparing the epitaxial layer in step S11 may include the following steps: First, a substrate is provided.
[0112] The substrate can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.
[0113] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.
[0114] The sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.
[0115] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.
[0116] Growing an epitaxial layer on a substrate can include: sequentially forming a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer on a sapphire substrate using MOCVD technology.
[0117] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.
[0118] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.
[0119] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.
[0120] Optionally, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.
[0121] When growing multiple quantum well layers, the MOCVD reaction chamber pressure is controlled at 200 torr. When growing InGaN quantum well layers, the reaction chamber temperature is 760℃ to 780℃. When growing GaN quantum barrier layers, the reaction chamber temperature is 860℃ to 890℃.
[0122] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.
[0123] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.
[0124] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.
[0125] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.
[0126] Then, the second semiconductor layer is etched to form a groove that exposes the first semiconductor layer.
[0127] Step S12 may include: firstly, forming a patterned mask with chamfer features on the surface of the epitaxial layer through photolithography steps such as coating, exposure, and development; then, using the mask as a protective layer, selectively removing the epitaxial layer using directional etching techniques such as plasma etching or wet etching, so that a first chamfer with a radius of 18μm to 26μm is naturally formed at the junction of two adjacent sidewalls, thereby achieving the precise construction of the stress buffer structure.
[0128] For example, the peripheral edge of the epitaxial layer is rectangular, and the ratio of the radius of the first chamfer to the long side of the peripheral edge of the epitaxial layer is 0.04 to 0.06.
[0129] For example, the ratio of the radius of the first chamfer to the shorter side of the peripheral edge of the epitaxial layer is 0.16 to 0.26.
[0130] The process after step S12 also includes: The first step is to form a current blocking layer on the surface of the epitaxial layer.
[0131] Specifically, this may include: using processes such as plasma-enhanced chemical vapor deposition or electron beam evaporation, using silicon dioxide or silicon nitride as the material, to uniformly deposit a current blocking layer on the surface of the completed epitaxial layer.
[0132] The second step is to form a current spreading layer covering the current blocking layer on the surface of the epitaxial layer.
[0133] In the example selection, the current spreading layer can be an ITO layer or an IZO layer.
[0134] The third step is to deposit metal material in the groove and on the surface of the second semiconductor layer to form the first electrode and the second electrode.
[0135] For example, both the first electrode and the second electrode may include Al layer, Ti layer, Ni layer, Pt layer and Au layer stacked sequentially.
[0136] For example, the thickness of the Al layer is 1500 angstroms to 2500 angstroms.
[0137] For example, the thickness of the Ti layer is 300 to 700 angstroms.
[0138] For example, the thickness of the Ni layer is 800 angstroms to 1200 angstroms.
[0139] For example, the thickness of the Pt layer is 1500 angstroms to 2500 angstroms.
[0140] For example, the thickness of the Au layer is 6,000 angstroms to 10,000 angstroms.
[0141] The fourth step is to form a passivation layer on the epitaxial layer.
[0142] The passivation layer covers the surface and sidewalls of the epitaxial layer, and the area of the passivation layer covering the first chamfer has a third chamfer with a radius of 18 μm to 26 μm.
[0143] Optionally, the passivation layer includes at least one of an aluminum oxide layer, a silicon oxide layer, a titanium oxide layer, and a silicon oxynitride layer.
[0144] For example, the passivation layer is a DBR layer, which includes multiple silicon oxide layers and multiple titanium oxide layers. The thickness of the DBR layer is 3 μm to 4 μm.
[0145] The fifth step is to etch the passivation layer to form vias on the surface of the passivation layer that expose the first and second electrodes.
[0146] The sixth step is to form pads on the passivation layer, and connect the pads to the epitaxial layer through vias in the passivation layer.
[0147] Wherein, at least a portion of the pad is located in the corner region of the epitaxial layer, and the sidewall of the pad located in the corner region of the epitaxial layer has a second chamfer, the radius of the second chamfer being less than or equal to the radius of the first chamfer, and the radius of the second chamfer being 18μm to 26μm.
[0148] Optionally, the pad includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked sequentially.
[0149] For example, the thickness of the first Ti layer is 20 to 100 angstroms. For instance, the thickness of the first Ti layer is 50 angstroms.
[0150] For example, the thickness of the Al layer is between 10,000 and 20,000 angstroms. For instance, the thickness of the Al layer is 15,000 angstroms.
[0151] For example, the thickness of the second Ti layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the second Ti layer is 1000 angstroms.
[0152] For example, the thickness of the Pt layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the Pt layer is 1000 angstroms.
[0153] For example, the thickness of the Ni layer is 6,000 to 8,000 angstroms. For instance, the thickness of the Ni layer is 7,000 angstroms.
[0154] For example, the thickness of the Au layer is between 1500 angstroms and 2500 angstroms. For instance, the thickness of the Au layer is 2000 angstroms.
[0155] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (10), and the junction of two adjacent sidewalls on the epitaxial layer (10) has a first chamfer (11), the radius of which is 18 μm to 26 μm.
2. The light-emitting diode according to claim 1, characterized in that, The peripheral edge of the epitaxial layer (10) is rectangular, and the ratio of the radius of the first chamfer (11) to the long side of the peripheral edge of the epitaxial layer (10) is 0.04 to 0.
06.
3. The light-emitting diode according to claim 2, characterized in that, The ratio of the radius of the first chamfer (11) to the short side of the peripheral edge of the epitaxial layer (10) is 0.16 to 0.
26.
4. The light-emitting diode according to claim 2, characterized in that, The light-emitting diode further includes a pad (20) located on the epitaxial layer (10), and at least a portion of the pad (20) is located in the corner region of the epitaxial layer (10), and the sidewall of the pad (20) located in the corner region of the epitaxial layer (10) has a second chamfer (21).
5. The light-emitting diode according to claim 4, characterized in that, The radius of the second chamfer (21) is less than or equal to the radius of the first chamfer (11), and the radius of the second chamfer (21) is 18 μm to 26 μm.
6. The light-emitting diode according to any one of claims 1 to 5, characterized in that, The light-emitting diode further includes a passivation layer (30) that covers the surface of the epitaxial layer (10) and the sidewalls of the epitaxial layer (10). The area of the passivation layer (30) covering the first chamfer (11) has a third chamfer (31) with a radius of 18 μm to 26 μm.
7. The light-emitting diode according to claim 6, characterized in that, The passivation layer (30) has a plurality of blind holes (32) spaced apart on the surface of the third chamfer (31), and the depth of the blind holes (32) is less than the thickness of the passivation layer (30).
8. The light-emitting diode according to claim 7, characterized in that, The diameter of the blind hole (32) is 1 μm to 5 μm.
9. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: An epitaxial layer is fabricated on a substrate; The epitaxial layer is graphically processed to form a first chamfer at the junction of two adjacent sidewalls on the epitaxial layer, the radius of which is 18 μm to 26 μm.
10. The preparation method according to claim 9, characterized in that, After graphically processing the epitaxial layer, the method further includes: A passivation layer is formed on the epitaxial layer, the passivation layer covering the surface of the epitaxial layer and the sidewalls of the epitaxial layer, and the area of the first chamfer covered by the passivation layer has a third chamfer with a radius of 18 μm to 26 μm; A pad is formed on the passivation layer, and the pad is connected to the epitaxial layer through a via in the passivation layer. At least a portion of the pad is located in the corner region of the epitaxial layer. The sidewall of the pad located in the corner region of the epitaxial layer has a second chamfer. The radius of the second chamfer is less than or equal to the radius of the first chamfer. The radius of the second chamfer is 18 μm to 26 μm.