Incremental circular grating encoder adaptive acquisition and simulation device and method

Abstract

The application discloses an incremental circular grating encoder adaptive acquisition and simulation device and method, and belongs to the technical field of encoder data acquisition. The technical problem to be solved is that a subsequent information processing system is difficult to use and has poor universality. The technical solution is as follows: the device comprises an incremental encoder, an encoder acquisition and simulation device, a motor controller and an upper computer. The incremental encoder is used for generating A signals, B signals and Z signals and inputting the signals into the encoder acquisition and simulation device. The encoder acquisition and simulation device is in communication with the motor controller and the upper computer. The encoder acquisition and simulation device comprises a simulation incremental encoder. The simulation incremental encoder is arranged in parallel with the incremental encoder. The simulation incremental encoder and the incremental encoder are used alternatively.

Description

Technical Field

[0001] This invention relates to the field of encoder data acquisition technology, and in particular to an adaptive acquisition and simulation device and method for incremental circular grating encoders. Background Technology

[0002] Currently, incremental circular grating encoders are widely used in high-precision measurements such as search radar, photoelectric search, and engineering machinery to measure position information and speed in real time. Compared with absolute encoders, incremental encoders have the advantages of high output data rate, high accuracy, and low price. The circular grating can rotate 360 ​​degrees to meet the measurement requirements.

[0003] In most applications, a fixed rotation direction of the equipment is required to provide a stable scanning environment for the scanning and detection devices. However, due to differences in encoder manufacturers or different mechanical structures and installation conditions, incremental encoders exhibit different A and B phases even when the equipment rotates in a fixed direction. Furthermore, different devices have varying resolutions, causing inconsistent encoder count values ​​output by existing incremental encoder acquisition systems. This creates difficulties for subsequent information processing systems. The output signal pulse width of the encoder also varies at different speeds or resolutions, requiring manual modification of the encoder's resolution and filtering parameters, a time-consuming and labor-intensive task for designers. Because incremental grating encoders require high sealing and are installed inside the turntable, encoder system fault detection is inconvenient and maintenance costs are high.

[0004] This document, published in China (CN116317725A) on June 23, 2023, discloses an incremental encoder absolute position reconstruction system and method. It employs an FPGA+MCU control architecture. Specifically, when the synchronous motor rotates, the incremental encoder outputs an ABZ signal. After signal conditioning and level conversion by the control system, the signal enters the FPGA chip. Based on the ABZ signal, the FPGA chip software is used to calculate the motor speed and reconstruct the motor position. The speed and position information are then transmitted to the MCU for motor algorithm control. The advantages of this invention are: the system and method use a parallel real-time processing FPGA chip to acquire and calculate the encoder ABZ signal, realizing the absolute position calculation of the motor. This eliminates the need for an absolute position encoder, solving many drawbacks of the traditional two-encoder configuration used in engineering applications. By using a single incremental encoder signal acquisition to calculate the motor speed and absolute position, the lag response time in data acquisition and transmission is eliminated, which is beneficial for improving the real-time response capability and control accuracy of the system.

[0005] The journal or book title is "Instrumentation Technology and Sensors," and the document title is "Design of a Signal Acquisition System for an Incremental Grating Ruler Based on Domestic FPGA," published in issue 8, 2023. This document discloses a design based on the domestically produced FPGA chip AG10K for an incremental grating ruler signal acquisition system for an optical focusing platform. The system implements functions such as frequency multiplication direction detection, pulse counting, and serial data transmission for the incremental grating ruler. Communication with a host computer is achieved through serial communication, enabling precise position acquisition and display of the optical focusing platform. A filtering algorithm is designed to filter false zero-position signals, and positive and negative double-pulse processing is applied to the frequency division counting logic, effectively reducing noise interference to the zero-position and counting modules and ensuring the accuracy of the acquisition algorithm.

[0006] The prior art represented by the aforementioned documents has at least the following unresolved technical problems or defects:

[0007] None of the aforementioned existing technologies provide adaptive adjustment for the encoder. Due to different encoder manufacturers or different mechanical structures and installation conditions, the A and B phases of the incremental encoder may differ even when the device rotates in a fixed direction. This results in different resolutions for different devices, causing difficulties for subsequent information processing systems and poor versatility. Summary of the Invention

[0008] The purpose of this invention is to provide:

[0009] An incremental circular grating encoder adaptive acquisition and simulation device and method, and related technologies, are provided to solve technical problems such as difficulties in subsequent information processing systems and poor versatility, or combinations thereof.

[0010] Terminology Explanation:

[0011] Unless otherwise defined, all technical terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the subject matter pertains. Unless otherwise stated, all patents, patent inventions, and publications cited throughout this document are incorporated herein by reference in their entirety. Where multiple definitions exist for terms in this document, the definitions provided in this chapter shall prevail.

[0012] It should be understood that the above brief description and the following detailed description are exemplary and for illustrative purposes only, and do not limit the subject matter of the invention in any way. In this invention, the singular is used in conjunction with the plural unless otherwise specifically stated. It should also be noted that, unless otherwise stated, the use of “or” or “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms such as “including,” “containing,” and “contains” are not limiting.

[0013] Unless otherwise stated, conventional methods within the scope of the art, such as "speed-based gain scheduling", shall be used.

[0014] Unless otherwise defined, the use of various commercially available products as described herein employs standard techniques. These techniques and methods can generally be implemented according to conventional methods well-known in the art, based on the descriptions in the numerous general and more specific documents cited and discussed in this specification.

[0015] The terms “optional / arbitrary” or “optionally / arbitrarily” mean that the event or situation described below may or may not occur, including both the occurrence and non-occurrence of the event or situation.

[0016] As used in this article, the term "encoder" refers to a sensor that converts mechanical motion (such as rotation or linear displacement) into electrical signals.

[0017] The term "circular grating" as used in this article refers to an optical element used for high-precision angle measurement, primarily for converting rotation angles or angular displacements into electrical signals.

[0018] The term "chip" as used in this article refers to: a chip is a core component of modern electronic devices, also known as an integrated circuit (IC) or microchip.

[0019] In a first aspect, the present invention provides: an incremental circular grating encoder adaptive acquisition and simulation device, comprising an incremental encoder, an encoder acquisition and simulation device, a motor controller and a host computer, wherein the incremental encoder is used to generate A signal, B signal and Z signal and input them into the encoder acquisition and simulation device, and the encoder acquisition and simulation device is connected to the motor controller and the host computer respectively;

[0020] The encoder acquisition and simulation device includes an analog incremental encoder, which is connected in parallel with the incremental encoder, and one of the analog incremental encoder and the incremental encoder can be used.

[0021] The encoder acquisition and simulation device further includes a channel selector, a code value addition / subtraction counting / clearing module, an output module, and a communication interface. Both the analog incremental encoder and the incremental encoder are connected to the channel selector. The channel selector is connected to the output module and the code value addition / subtraction counting / clearing module, respectively. The code value addition / subtraction counting / clearing module is connected to the communication interface, which is connected to the host computer or a downstream device. The signal received by the output module is the original signal input by the channel selector.

[0022] The incremental encoder includes a phase detector, which determines whether to invert the A and B signals. After the phase detector determines the signals, A', B', and Z signals are obtained. The incremental encoder then filters the A', B', and Z signals obtained by the phase detector.

[0023] Secondly, this invention provides: an adaptive acquisition and simulation method for an incremental circular grating encoder, comprising the following steps:

[0024] S1. Execute adaptive mode on the incremental encoder to adaptively adjust the encoder;

[0025] S2. The host computer determines the working mode of the incremental encoder through commands. The working modes include normal mode, adaptive mode and analog mode. The host computer determines the specific working mode to enter based on the parameters of the incremental encoder. When the host computer determines to execute the normal mode, proceed to step S3. When the host computer determines to execute the adaptive mode, proceed to step S4. When the host computer determines to execute the analog mode, proceed to step S5.

[0026] S3. The host computer executes the normal mode for the incremental encoder;

[0027] S4. The host computer executes the adaptive mode for the incremental encoder. First, it executes the same content as the adaptive mode in step S1, and then switches to normal mode to execute the content in step S3.

[0028] S5. The host computer executes the simulation mode, stops the incremental encoder from acquiring signals, and uses the analog incremental encoder to acquire signals A, B, and Z, and executes the simulation mode.

[0029] S1 includes the following steps:

[0030] S11. Use a phase detector to acquire the phases of signals A and B, and then calculate the filtering parameters based on the periods of signals A, B, and Z.

[0031] S12. The phase detector determines whether the phases of signal A and signal B are inverted, outputs signal A', signal B' and signal Z that meet the phase requirements, and uses filtering parameters to filter signal A', signal B' and signal Z.

[0032] S13. According to the encoder code value counting rules, perform code value addition and subtraction to obtain the cumulative code value;

[0033] S14. Output the code value to the host computer or subsequent devices;

[0034] S15. Clear the Z signal to zero according to the encoder code value counting rules;

[0035] S16. Iterate through steps S11-S15 until the iteration termination condition is met. The iteration termination condition is: continuously collect the maximum value of the encoder disk N times; by re-collecting the encoder at the current speed using the appropriate filtering parameters, the maximum value of the encoder disk per revolution can be obtained.

[0036] S17, Store the phase of signal A and the phase of signal B, and the resolution of the incremental encoder.

[0037] In step S12, the specific method for the phase detector to determine whether the phases of signal A and signal B are inverted is as follows: when the phase of signal B leads the phase of signal A, it indicates that the phases are inverted. At this time, the phases of signal A and signal B are inverted to obtain signal A' and signal B'. Otherwise, it indicates that the phases are not inverted, and the acquired signal A and signal B are directly output as signal A' and signal B'.

[0038] The method for obtaining the filter parameters in step S12 is as follows:

[0039] (1) Collect n cycles for each of the A' and B' signals, calculate the corresponding average period and standard deviation, and collect n cycles for each of the A' and B' signals again. Calculate the corresponding period error by subtracting the two sets of n cycles from the corresponding average period, and determine whether they meet the standard deviation. Count the total number of signals that meet the standard deviation. If the total number is greater than n / 2 and the difference between the average periods of the A and B signals is less than 5%, then use one-eighth of the average period as the filtering parameter. Otherwise, recount until the total number is greater than n / 2.

[0040] (2) For the zero-position Z signal, its pulse width time is collected h times, and then the average value is taken and compared with the average period of the A' signal and the average period of the B' signal in (1). If the pulse width time of the encoder Z signal meets the requirement of one-quarter of the average period of the A' signal and the average period of the B' signal, the error is set to be less than 5%, and one-quarter of the average pulse width time of the Z signal h times is used as the filtering parameter.

[0041] In step S2, when the data in the FLASH is an invalid value, the adaptive mode is executed; when the data in the FLASH is the maximum value of the encoder, the normal mode is executed; and when fault detection is required, the simulation mode is executed.

[0042] Specifically, S3 includes the following steps:

[0043] S31. Read the resolution and filtering parameters of the incremental encoder before and after the A and B phases in the corresponding FLASH storage space. The stored encoder phase is the ASCII code of "A" or "B" and the low bit is not 1.

[0044] S32. Determine whether the phases of A and B are inverted, and filter the A, B, and Z signals according to the filtering parameters;

[0045] S33. Perform code value addition and subtraction counting according to the encoder code value counting rules;

[0046] S34, the code value is output to the host computer and subsequent devices;

[0047] S35. According to the encoder code value counting rules, clear the Z signal to zero, and then end the task.

[0048] Specifically, S5 includes the following steps:

[0049] S51. Calculate the periods of signals A, B, and Z based on the rotation speed and resolution sent by the host computer.

[0050] S52. Perform code value addition and subtraction counting according to the encoder code value counting rules;

[0051] S53, the code value is output to the host computer or subsequent devices;

[0052] S54. According to the encoder code value counting rules, clear the Z signal to zero, and then end the task.

[0053] The present invention has at least the following beneficial effects:

[0054] (1) This invention determines the A and B phases before and after the current encoder speed by using a phase detector, designs a specific algorithm to calculate the filtering parameters of the acquired signal, and re-outputs the A, B and Z signals after filtering so that their phases meet the requirements of subsequent code value counting, thereby completing the encoder resolution recognition. After the adaptive process is completed, the output signal parameters of the acquired encoder are automatically stored, thereby realizing adaptive adjustment of different A and B phases and different resolutions under different manufacturers or different mechanical structure installation conditions, and improving compatibility.

[0055] (2) By setting up an analog incremental encoder, the present invention enables effective replacement under fault conditions, which helps to quickly locate the fault location in complex encoder application scenarios. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the overall structure of the device of the present invention.

[0057] Figure 2 This is a schematic diagram of the encoder acquisition and simulation device of the present invention. Detailed Implementation

[0058] The following non-limiting embodiments are intended to enable those skilled in the art to gain a more comprehensive understanding of the present invention, but do not limit the invention in any way. The following content is merely an exemplary description of the scope of protection claimed by the present invention, and those skilled in the art can make various changes and modifications to the present invention based on the disclosed content, and such changes should also fall within the scope of protection claimed by the present invention.

[0059] The present invention will be further described below by way of specific embodiments. Unless otherwise specified, all instruments, devices, equipment, reagents, products, etc., used in the embodiments of the present invention are obtained through conventional commercial means.

[0060] Example 1

[0061] like Figure 1 As shown, this embodiment provides an incremental circular grating encoder adaptive acquisition and simulation device, including an incremental encoder, an encoder acquisition and simulation device, a motor controller, and a host computer, with the main chip being an FPGA. The incremental encoder generates A, B, and Z signals, which are input into the encoder acquisition and simulation device. The encoder acquisition and simulation device receives the A signal at a TTL level, the B signal at a TTL level, and the Z signal at a TTL level. The device also outputs a processed A signal at a TTL level, a processed B signal at a TTL level, and a processed Z signal at a TTL level. The encoder acquisition and simulation device outputs the processed Z signal. It includes a motor control serial port, a communication serial port, and a fiber optic communication serial port. The motor control serial port connects to the motor controller. The host computer also has a communication serial port and a fiber optic communication serial port. Data is transmitted between the communication serial port in the encoder acquisition and simulation device and the communication serial port in the host computer. Data is also transmitted between the fiber optic communication serial port in the encoder acquisition and simulation device and the fiber optic communication serial port in the host computer. The preferred fiber optic communication rate is 4 Gbit / s, and the preferred serial port baud rate is 921600. The encoder acquisition and simulation device also includes a clock DCM module and a parameter storage module. The clock DCM module synchronizes the output signal of the encoder acquisition and simulation device and stores the synchronized output signal in the parameter storage module.

[0062] like Figure 2 As shown, the encoder acquisition and simulation device includes an analog incremental encoder, a channel selector, a code value increment / decrement / reset module, an output module, and a communication interface. The analog incremental encoder and the incremental encoder are connected in parallel. Only one of the analog incremental encoder and the incremental encoder can be used, and the analog incremental encoder is only used in analog mode to detect the location of faults in the circuit. The analog incremental encoder is used to output A, B, and Z signals. Both the analog incremental encoder and the incremental encoder are connected to the channel selector. The channel selector is connected to the output module and the code value increment / decrement / reset module, respectively. The code value increment / decrement / reset module is connected to the communication interface, which is connected to a host computer or subsequent equipment. The signal received by the output module is the original signal input by the channel selector.

[0063] An incremental encoder is equipped with a phase detector, which is used to determine whether to invert the A signal and the B signal. After the phase detector determines the signal, the A' signal, the B' signal and the Z signal are obtained. The incremental encoder then filters the A' signal, the B' signal and the Z signal after the phase detector determines the signal.

[0064] Example 2

[0065] This embodiment provides an adaptive acquisition and simulation method for an incremental circular grating encoder, including the following steps:

[0066] S1. Implement adaptive mode for the incremental encoder, and adaptively adjust the encoder to ensure that the adaptively adjusted incremental encoder is suitable for the current working conditions. The specific method is as follows:

[0067] S11. Use a phase detector to acquire the phases of signals A and B, and then calculate the filtering parameters based on the periods of signals A, B, and Z.

[0068] S12. The phase detector determines whether the phases of signal A and signal B are inverted, outputs signals A', B', and Z that meet the phase requirements, and performs filtering operations on signals A', B', and Z using filtering parameters.

[0069] The specific method for the phase detector to determine whether the phases of signal A and signal B are inverted is as follows: when the phase of signal B leads the phase of signal A, it indicates that the phases are inverted. In this case, the phases of signal A and signal B are inverted to obtain signal A' and signal B'. Otherwise, it indicates that the phases are not inverted, and the acquired signal A and signal B are directly output as signal A' and signal B'.

[0070] The method for obtaining the filter parameters is as follows:

[0071] (1) Collect n cycles for each of the A' and B' signals, calculate the corresponding average period and standard deviation, and collect n cycles for each of the A' and B' signals again. Calculate the corresponding period error by subtracting the two sets of n cycles from the corresponding average period, and determine whether they meet the standard deviation. Count the total number of signals that meet the standard deviation. If the total number is greater than n / 2 and the difference between the average periods of the A and B signals is less than 5%, then one-eighth of the average period is used as the filtering parameter. Otherwise, recount until the total number is greater than n / 2. n is preferably 2000.

[0072] (2) In order to prevent interference from false zero signals, the pulse width time of the zero-position Z signal is collected h times, and then the average value is taken and compared with the average period of the A' signal and the average period of the B' signal in (1). If the pulse width time of the encoder Z signal meets the requirement of one-quarter of the average period of the A' signal and the average period of the B' signal (error less than 5%), one-quarter of the average pulse width time of the Z signal h times is used as the filtering parameter, and h is preferably 10.

[0073] S13. According to the encoder code value counting rules, perform code value addition and subtraction to obtain the cumulative code value.

[0074] S14, output the code value to the host computer or subsequent devices.

[0075] S15. Clear the Z signal to zero according to the encoder code value counting rules.

[0076] S16. Iterate through steps S11-S15 until the iteration termination condition is met. The iteration termination condition is: continuously collect the maximum value of the encoder disk N times, where N is preferably 10; re-collect the encoder at the current speed using the appropriate filtering parameters to obtain the maximum value of the encoder disk per revolution.

[0077] S17, Store the phase of signal A and the phase of signal B, and the resolution of the incremental encoder.

[0078] S2. The host computer determines the operating mode of the incremental encoder via commands. The operating modes include normal mode, adaptive mode, and analog mode. The host computer determines the specific operating mode to enter based on the parameters of the incremental encoder. When the host computer determines to execute the normal mode, proceed to step S3; when the host computer determines to execute the adaptive mode, proceed to step S4; and when the host computer determines to execute the analog mode, proceed to step S5.

[0079] When the data in the FLASH is an invalid value, the adaptive mode is executed; when the data in the FLASH is the maximum value of the encoder, the normal mode is executed, and the minimum value of the stored encoder is preferably 213 and the maximum value is preferably 230; when fault detection is required, the simulation mode is executed.

[0080] S3. The host computer executes the normal mode for the incremental encoder, which includes the following steps:

[0081] S31. Read the resolution and filtering parameters of the incremental encoder before and after the A and B phases in the corresponding FLASH storage space. The stored encoder phase is the ASCII code of "A" or "B", and the low bit is not 1.

[0082] S32. Determine whether the phases of A and B are inverted, and filter the A, B and Z signals according to the filtering parameters.

[0083] S33. Perform code value addition and subtraction counting according to the encoder code value counting rules.

[0084] S34, the code value is output to the host computer and subsequent devices.

[0085] S35. According to the encoder code value counting rules, clear the Z signal to zero, and then end the task.

[0086] S4. The host computer executes the adaptive mode for the incremental encoder. First, it executes the same content as the adaptive mode in step S1, and then switches to normal mode to execute the content in step S3.

[0087] S5. The host computer executes the simulation mode, stops the incremental encoder from acquiring signals, and uses the analog incremental encoder to acquire signals A, B, and Z. The specific steps of executing the simulation mode are as follows:

[0088] S51. Calculate the periods of signals A, B, and Z based on the rotational speed and resolution generated by the host computer.

[0089] S52. Perform code value addition and subtraction counting according to the encoder code value counting rules.

[0090] S53, the code value is output to the host computer or subsequent devices.

[0091] S54. According to the encoder code value counting rules, clear the Z signal to zero, and then end the task.

[0092] Verification of technical effectiveness and / or analysis of solutions to technical problems:

[0093] This invention uses a phase detector to determine the A and B phases at the current encoder speed, designs a specific algorithm to calculate the filtering parameters of the acquired signal, and re-outputs the A, B, and Z signals after filtering to ensure that their phases meet the requirements for subsequent code value counting, thereby completing encoder resolution recognition. After adaptive adjustment, it automatically stores the acquired encoder output signal parameters, thus achieving adaptive adjustment for different A and B phases and different resolutions under different manufacturers or different mechanical structure installation conditions, improving compatibility.

[0094] This invention enables effective replacement under fault conditions by setting up an analog incremental encoder, which helps to quickly locate the fault location in complex encoder application scenarios.

[0095] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention do not depart from the essence and scope of the technical solution of the present invention.

Claims

1. An adaptive acquisition and simulation method for an incremental circular grating encoder, characterized in that, Includes the following steps: S1. Execute adaptive mode on the incremental encoder to adaptively adjust the encoder; During the adaptive adjustment process, the phase of signal A and signal B are acquired by a phase detector, the filtering parameters of the acquired signals are calculated, and the signals A, B and Z are output after filtering according to the filtering parameters so that their phases meet the code value counting requirements, thereby completing the adaptive adjustment of encoder resolution. The method for obtaining the filter parameters is as follows: (1) Collect n cycles for each of the A' and B' signals, calculate the corresponding average period and standard deviation, and collect n cycles for each of the A' and B' signals again. Calculate the corresponding period error by subtracting the two sets of n cycles from the corresponding average period, and determine whether they meet the standard deviation. Count the total number of signals that meet the standard deviation. If the total number is greater than n / 2 and the difference between the average periods of the A and B signals is less than 5%, then use one-eighth of the average period as the filtering parameter. Otherwise, recount until the total number is greater than n / 2. (2) For the zero-position Z signal, its pulse width time is collected, collected h times, and then the average value is taken and compared with the average period of the A' signal and the average period of the B' signal in (1). If the pulse width time of the encoder Z signal meets the requirement of one-quarter of the average period of the A' signal and the average period of the B' signal, the error is set to be less than 5%, and one-quarter of the average pulse width time of the Z signal h times is used as the filtering parameter. S2. The host computer determines the working mode of the incremental encoder through commands. The working modes include normal mode, adaptive mode and analog mode. The host computer determines the specific working mode to enter based on the parameters of the incremental encoder. When the host computer determines to execute the normal mode, proceed to step S3. When the host computer determines to execute the adaptive mode, proceed to step S4. When the host computer determines to execute the analog mode, proceed to step S5. S3. The host computer executes the normal mode for the incremental encoder; S4. The host computer executes the adaptive mode for the incremental encoder. First, it executes the same content as the adaptive mode in step S1, and then switches to normal mode to execute the content in step S3. S5. The host computer executes the simulation mode, stops the incremental encoder from acquiring signals, and uses the analog incremental encoder to acquire signals A, B, and Z, and executes the simulation mode.

2. The adaptive acquisition and simulation method for an incremental circular grating encoder according to claim 1, characterized in that, S1 includes the following steps: S11. Use a phase detector to acquire the phases of signals A and B, and then calculate the filtering parameters based on the periods of signals A, B, and Z. S12. The phase detector determines whether the phases of signal A and signal B are inverted, outputs signal A', signal B' and signal Z that meet the phase requirements, and uses filtering parameters to filter signal A', signal B' and signal Z. S13. According to the encoder code value counting rules, perform code value addition and subtraction to obtain the cumulative code value; S14. Output the code value to the host computer or subsequent devices; S15. Clear the Z signal to zero according to the encoder code value counting rules; S16. Iterate through steps S11-S15 until the iteration termination condition is met. The iteration termination condition is: continuously collect the maximum value of the encoder disk N times; by re-collecting the encoder at the current speed using the appropriate filtering parameters, the maximum value of the encoder disk per revolution can be obtained. S17, Store the phase of signal A and the phase of signal B, and the resolution of the incremental encoder.

3. The adaptive acquisition and simulation method for an incremental circular grating encoder according to claim 2, characterized in that, In step S12, the specific method for the phase detector to determine whether the phases of signal A and signal B are inverted is as follows: when the phase of signal B leads the phase of signal A, it indicates that the phases are inverted. At this time, the phases of signal A and signal B are inverted to obtain signal A' and signal B'. Otherwise, it indicates that the phases are not inverted, and the acquired signal A and signal B are directly output as signal A' and signal B'.

4. The adaptive acquisition and simulation method for an incremental circular grating encoder according to claim 1, characterized in that, In step S2, when the data in the FLASH is an invalid value, the adaptive mode is executed; when the data in the FLASH is the maximum value of the encoder, the normal mode is executed. When fault detection is required, execute the simulation mode.

5. The adaptive acquisition and simulation method for an incremental circular grating encoder according to claim 1, characterized in that, S3 specifically includes the following steps: S31. Read the resolution and filtering parameters of the incremental encoder before and after the A and B phases in the corresponding FLASH storage space. The stored encoder phase is the ASCII code of "A" or "B" and the low bit is not 1. S32. Determine whether the phases of A and B are inverted, and filter the A, B, and Z signals according to the filtering parameters; S33. Perform code value addition and subtraction counting according to the encoder code value counting rules; S34, the code value is output to the host computer and subsequent devices; S35. According to the encoder code value counting rules, clear the Z signal to zero, and then end the task.

6. The adaptive acquisition and simulation method for an incremental circular grating encoder according to claim 1, characterized in that, S5 specifically includes the following steps: S51. Calculate the periods of signals A, B, and Z based on the rotation speed and resolution sent by the host computer. S52. Perform code value addition and subtraction counting according to the encoder code value counting rules; S53, the code value is output to the host computer or subsequent devices; S54. According to the encoder code value counting rules, clear the Z signal to zero, and then end the task.

7. An incremental circular grating encoder adaptive acquisition and simulation device, characterized in that, An adaptive acquisition and simulation method for an incremental circular grating encoder according to any one of claims 1-6 includes an incremental encoder, an encoder acquisition and simulation device, a motor controller, and a host computer. The incremental encoder is used to generate A signal, B signal, and Z signal and input them into the encoder acquisition and simulation device. The encoder acquisition and simulation device is connected to the motor controller and the host computer, respectively. The encoder acquisition and simulation device includes an analog incremental encoder, which is connected in parallel with the incremental encoder, and one of the analog incremental encoder and the incremental encoder can be used.

8. The incremental circular grating encoder adaptive acquisition and simulation device according to claim 7, characterized in that, The encoder acquisition and simulation device further includes a channel selector, a code value addition / subtraction counting / clearing module, an output module, and a communication interface. Both the analog incremental encoder and the incremental encoder are connected to the channel selector. The channel selector is connected to the output module and the code value addition / subtraction counting / clearing module, respectively. The code value addition / subtraction counting / clearing module is connected to the communication interface, which is connected to the host computer or a downstream device. The signal received by the output module is the original signal input by the channel selector.

9. The incremental circular grating encoder adaptive acquisition and simulation device according to claim 8, characterized in that, The incremental encoder is equipped with a phase detector, which is used to determine whether to invert the A signal and the B signal. After the phase detector determines the signal, the A' signal, the B' signal and the Z signal are obtained. The incremental encoder performs filtering processing on the A' signal, the B' signal and the Z signal after the phase detector.

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