High-side drive idle detection circuit

Abstract

The application discloses a kind of high side drive no-load detection circuits, belong to electronic technical field, the high side drive no-load detection circuit, including current sampling module, including current mirror, current mirror includes first MOS tube and second MOS tube, the source of first MOS tube and second MOS tube is connected power supply voltage, gate is interconnected and is connected on voltage, and the current that the drain of first MOS tube and second MOS tube exports has predetermined proportion, the drain of second MOS tube is also connected to pull load current input port;Comparison module, the first input and second input of comparison module are connected with the drain of first MOS tube and the drain of second MOS tube respectively, for different level signals are exported according to the difference between two-way input voltage, judges no-load state by level signal.New high side drive in the no-load detection circuit it has is proposed, with the characteristics of low power consumption, simple circuit and high reliability.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a high-side drive no-load detection circuit. Background Technology

[0002] High-side driving is an electronic circuit design technique used to control the power supply side (high side) of a load, rather than the ground side (low side). It is crucial in many applications, especially in scenarios requiring precise power control or circuit protection. High-side driving offers better detection and handling of load short circuits and simplifies wiring and reduces noise by allowing one end of the load to be directly grounded. Based on these characteristics, high-side driving is widely used in automotive electronics, such as in headlight control, fuel pump control, seat heating, wiper motors, and power windows—all vehicle-related functions.

[0003] High-side driven electronic devices are mostly in an idle standby state. Therefore, how to detect the idle state when the high-side output is turned on, shut down unnecessary circuits, and reduce power consumption has become an urgent problem to be solved.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a high-side drive no-load detection circuit to solve the problem of how to detect the no-load state when the high-side output is turned on.

[0006] To solve the above technical problems, the present invention provides a high-side drive no-load detection circuit, comprising:

[0007] A current sampling module includes a current mirror, which includes a first MOSFET and a second MOSFET. The sources of the first MOSFET and the second MOSFET are connected to a power supply voltage, and their gates are interconnected and connected to a turn-on voltage. The current output from the drains of the first MOSFET and the second MOSFET has a predetermined ratio. The drain of the second MOSFET is also connected to a load current input port.

[0008] The comparison module has its first and second input terminals connected to the drains of the first and second MOSFETs, respectively, and is used to output different level signals based on the difference between the two input currents, thereby determining the no-load state through the level signals.

[0009] Preferably, the predetermined ratio is less than 1.

[0010] Preferably, the current sampling module further includes a third MOS transistor and a fourth MOS transistor. The source of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the third MOS transistor is connected to the first input terminal of the comparison module. The source of the fourth MOS transistor is connected to the drain of the second MOS transistor, and the drain of the fourth MOS transistor is connected to the second input terminal of the comparison module. The gates of the third MOS transistor and the fourth MOS transistor are interconnected and connected to the gate of the first MOS transistor.

[0011] Preferably, the width-to-length ratio of the third MOS transistor and the fourth MOS transistor is 1.

[0012] Preferably, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all PMOS transistors.

[0013] Preferably, the gates of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all connected to the anode of the Zener diode, and the cathode of the Zener diode is connected to the power supply voltage.

[0014] Preferably, the comparison module includes a fifth MOS transistor and a sixth MOS transistor. The source of the fifth MOS transistor is connected to the drain of the third MOS transistor, and the drain is used to output the level signal. The source of the sixth MOS transistor is connected to the drain of the fourth MOS transistor. The gate and drain of the sixth MOS transistor are interconnected and connected to the gate of the fifth MOS transistor.

[0015] Preferably, the drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor, the drain of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, the gates of the seventh and eighth MOS transistors are both connected to a bias voltage, and the sources of the seventh and eighth MOS transistors are both grounded.

[0016] Preferably, the fifth and sixth MOS transistors are both PMOS transistors, and the seventh and eighth MOS transistors are both NMOS transistors.

[0017] Preferably, when the voltage at the second input terminal of the comparison module is greater than the voltage at the first input terminal, a first level signal is output, and the circuit under test is in an unloaded state; when the voltage at the second input terminal of the comparison module is less than the voltage at the first input terminal, a second level signal is output, and the first level signal is less than the second level signal, and the circuit under test is in a non-unloaded state.

[0018] In the high-side drive no-load detection circuit provided by the present invention, a current sampling module is used to sample the high-side output current, a current mirror provides two currents with a predetermined ratio, and a load current is introduced into one of them. Then, a comparison module is used to detect the two voltages and output a corresponding level signal based on the difference between the two voltages. The implementation method is simple and reliable, has low power consumption, and can accurately determine whether the HS high-side output is in a no-load state. Attached Figure Description

[0019] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0020] Figure 1 This is a circuit diagram of a high-side drive output no-load detection circuit according to an embodiment of the present invention.

[0021] In the attached image:

[0022] 100. Current sampling module; 200. Comparison module. Detailed Implementation

[0023] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0024] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] Research has found that conventional no-load detection circuits are often designed for high-current electronic devices, such as those using switching power supplies. Such detection circuits are often complex in design and have high power consumption.

[0026] Based on this, the core idea of ​​the present invention is to propose a new no-load detection circuit in high-side driving, which has the characteristics of low power consumption, simple circuit and high reliability.

[0027] For details, please refer to Figure 1 This is a schematic diagram of an embodiment of the present invention. Figure 1 As shown, a high-side drive no-load detection circuit includes:

[0028] The current sampling module 100 includes a current mirror, which includes a first MOSFET PM1 and a second MOSFET PM2. The sources of the first MOSFET PM1 and the second MOSFET PM2 are connected to the power supply voltage VCC, and their gates are interconnected and connected to the on-state voltage. The current output from the drains of the first MOSFET PM1 and the second MOSFET PM2 has a predetermined ratio. The drain of the second MOSFET PM2 is also connected to the load current input port HS.

[0029] The comparison module 200 has its first input terminal and second input terminal connected to the drain of the first MOS transistor PM1 and the drain of the second MOS transistor PM2, respectively. It is used to output different level signals according to the difference between the two input voltages and to determine the no-load state through the level signals.

[0030] In one implementation, the current sampling module 100 samples the high-side output current, uses a current mirror to provide two currents with a predetermined ratio, and introduces a load current I into one of them. H Then, the comparison module 200 is used to detect the two voltages and output the corresponding level signal according to the difference between the two voltages. The method is simple and reliable, has low power consumption, and can accurately determine whether the HS high-side output is in an unloaded state.

[0031] Specifically, when the voltage at the second input terminal of the comparison module 200 is greater than the voltage at the first input terminal, a first level signal is output, indicating that the circuit under test is in an unloaded state. When the voltage at the second input terminal of the comparison module 200 is less than the voltage at the first input terminal, a second level signal is output, and the first level signal is less than the second level signal, indicating that the circuit under test is in a non-unloaded state. For example, the first level signal is low, and the second level signal is high.

[0032] In this method, a current mirror is used to provide two currents with a predetermined ratio, and a load current I is added to one of them. H Let R1 be the linear region impedance of the first MOSFET PM1, and R2 be the linear region impedance of the second MOSFET PM2. Let I1 be the current flowing through the comparator module 200. When the voltage drops of the first MOSFET PM1 and the second MOSFET PM2 are equal, the no-load current switching threshold is obtained. Then:

[0033]

[0034] This leads to the load current I. H No-load current reversal threshold:

[0035]

[0036] when:

[0037]

[0038] The voltage drop across the second MOSFET PM2 is greater than the voltage drop across the first MOSFET PM1, causing the load current I to be drawn. H If the current exceeds the no-load current switching threshold, the output is at a high level, and the high-side output is determined to be in a non-no-load state.

[0039] when:

[0040]

[0041] The voltage drop of the second MOSFET PM2 is less than that of the first MOSFET PM1, resulting in a lower load current I. H When the current is less than the no-load current switching threshold, the output is at a low level, and the high-side output is determined to be in a no-load state.

[0042] In one embodiment, the predetermined ratio is less than 1. The first MOSFET PM1 and the second MOSFET PM2 form an HS output sampling current mirror. By adjusting the width-to-length ratio of the first MOSFET PM1 and the second MOSFET PM2, the magnitude of the current output at their drain terminals is adjusted. Let the current mirror ratio be 1:N, typically N>>1. More preferably, N is 100 or 1000.

[0043] Specifically, the current sampling module 100 further includes a third MOSFET PM3 and a fourth MOSFET PM4. The source of the third MOSFET PM3 is connected to the drain of the first MOSFET PM1, and the drain of the third MOSFET PM3 is connected to the first input terminal of the comparison module 200. The source of the fourth MOSFET PM4 is connected to the drain of the second MOSFET PM2, and the drain of the fourth MOSFET PM4 is connected to the second input terminal of the comparison module 200. The gates of the third MOSFET PM3 and the fourth MOSFET PM4 are interconnected and connected to the gate of the first MOSFET PM1.

[0044] The gates of the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, and the fourth MOSFET PM4 are all connected to a turn-on voltage that allows them to conduct stably. In one embodiment, a Zener diode Z1 provides a stable turn-on voltage to the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, and the fourth MOSFET PM4. The gates of the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, and the fourth MOSFET PM4 are all connected to the anode of the Zener diode Z1, and the cathode of the Zener diode Z1 is connected to the power supply voltage VCC. Obviously, the gates of the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, and the fourth MOSFET PM4 can also be connected to a voltage regulator circuit containing the Zener diode Z1 or other voltage regulator circuits that can provide a stable turn-on voltage.

[0045] In one embodiment, the first MOS transistor PM1, the second MOS transistor PM2, the third MOS transistor PM3, and the fourth MOS transistor PM4 are all PMOS transistors.

[0046] The first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, the fourth MOSFET PM4, and the Zener diode Z1 constitute the high-side output current sampling module. The third MOSFET PM3 and the fourth MOSFET PM4 form a high-voltage current protection mirror, and their current ratio is typically set to 1:1. Understandably, the width-to-length ratio of the third MOSFET PM3 and the fourth MOSFET PM4 is 1. The function of the Zener diode Z1 is to clamp and protect the voltage difference between the power supply voltage VCC and the gate voltages of the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, and the fourth MOSFET PM4, while simultaneously providing a reasonable bias voltage to the four PMOS transistors.

[0047] Specifically, the comparison module 200 includes a fifth MOS transistor PM5 and a sixth MOS transistor PM6. The source of the fifth MOS transistor PM5 is connected to the drain of the third MOS transistor PM3, and the drain is used to output the level signal. The source of the sixth MOS transistor PM6 is connected to the drain of the fourth MOS transistor PM4. The gate and drain of the sixth MOS transistor PM6 are interconnected and connected to the gate of the fifth MOS transistor PM5.

[0048] The fifth MOSFET PM5 and the sixth MOSFET PM6 form the differential input of the common-gate comparator. PM5 and PM6 are the differential input pair of the comparator. The drain of PM5 is connected to the output port OC_OUT of the comparator module 200. When the source voltage of PM6 is greater than the source voltage of PM5, the output port OC_OUT outputs a low level, indicating that the high-side output is in an unloaded state. When the source voltage of PM6 is less than the source voltage of PM5, the output port OC_OUT outputs a high level, indicating that the high-side output is in a non-unloaded state.

[0049] In this configuration, the drain of the fifth MOSFET PM5 is connected to the drain of the seventh MOSFET NM7, and the drain of the sixth MOSFET PM6 is connected to the drain of the eighth MOSFET NM8. The gates of both the seventh MOSFET NM7 and the eighth MOSFET NM8 are connected to a bias voltage Vbias, and the sources of both the seventh MOSFET NM7 and the eighth MOSFET NM8 are grounded to GND. The fifth MOSFET PM5 and the sixth MOSFET PM6 are both PMOS transistors, and the seventh MOSFET NM7 and the eighth MOSFET NM8 are both NMOS transistors.

[0050] The seventh MOSFET NM7 and the eighth MOSFET NM8 form the load terminal of the common-gate comparator. The gates of both MOSFETs NM7 and NM8 are connected to a bias voltage Vbias. The magnitude of Vbias is sufficient to turn on both MOSFETs NM7 and NM8, and the current flowing through both MOSFETs NM7 and NM8 under the bias voltage Vbias is I1. When the drain voltage drops of the first MOSFET PM1 and the second MOSFET PM2 are equal, the following relationship exists:

[0051]

[0052] Therefore, when the source voltage of the sixth MOSFET PM6 is greater than or less than the source voltage of the fifth MOSFET PM5, the output port OC_OUT outputs different level signals to perform no-load detection.

[0053] In the high-side drive no-load detection circuit provided by this invention, the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, the fourth MOSFET PM4, and the Zener diode Z1 form the HS high-side output current sampling circuit. The Zener diode Z1 clamps and protects the voltage difference between the power supply voltage VCC and the gate voltages of the first MOSFET PM1, the second MOSFET PM2, the third MOSFET PM3, and the fourth MOSFET PM4, while simultaneously providing a reasonable bias voltage to the four PMOS transistors. The first MOSFET PM1 and the second MOSFET PM2 form the output sampling current mirror, with a current mirror ratio much less than 1. The third MOSFET PM3 and the fourth MOSFET PM4 form the high-voltage protection current mirror, with a ratio of 1:1. The fifth MOSFET PM5 and the sixth MOSFET PM6 form the differential input terminal of the common-gate comparator, and the seventh MOSFET NM7 and the eighth MOSFET NM8 form the load terminal of the common-gate comparator. Based on the relationship between the source voltages of the fifth MOSFET PM5 and the sixth MOSFET PM6, different level signals are output at the output port OC_OUT. Therefore, it is possible to accurately determine whether the high-side output is in an unloaded state when the high-side output is turned on. The entire circuit has the characteristics of simple structure, high integration, high reliability and low power consumption. Furthermore, by adjusting the structure of the MOSFETs, it can be widely used in automotive body electronic equipment.

[0054] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A high-side drive no-load detection circuit, characterized in that, include: A current sampling module includes a current mirror, which includes a first MOSFET and a second MOSFET. The sources of the first MOSFET and the second MOSFET are connected to a power supply voltage, and their gates are interconnected and connected to a turn-on voltage. The current output from the drains of the first MOSFET and the second MOSFET has a predetermined ratio. The drain of the second MOSFET is also connected to a load current input port. The comparison module has its first and second input terminals connected to the drains of the first and second MOSFETs, respectively, and is used to output different level signals based on the difference between the two input voltages, thereby determining the no-load state through the level signals.

2. The high-side drive no-load detection circuit according to claim 1, characterized in that, The predetermined ratio is less than 1.

3. The high-side drive no-load detection circuit according to claim 1, characterized in that, The current sampling module further includes a third MOS transistor and a fourth MOS transistor. The source of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the third MOS transistor is connected to the first input terminal of the comparison module. The source of the fourth MOS transistor is connected to the drain of the second MOS transistor, and the drain of the fourth MOS transistor is connected to the second input terminal of the comparison module. The gates of the third MOS transistor and the fourth MOS transistor are interconnected and connected to the gate of the first MOS transistor.

4. The high-side drive no-load detection circuit according to claim 3, characterized in that, The width-to-length ratio of the third MOS transistor and the fourth MOS transistor is 1.

5. The high-side drive no-load detection circuit according to claim 3, characterized in that, The first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all PMOS transistors.

6. The high-side drive no-load detection circuit according to claim 3, characterized in that, The gates of the first, second, third, and fourth MOSFETs are all connected to the anode of the Zener diode, while the cathode of the Zener diode is connected to the power supply voltage.

7. The high-side drive no-load detection circuit according to claim 3, characterized in that, The comparison module includes a fifth MOS transistor and a sixth MOS transistor. The source of the fifth MOS transistor is connected to the drain of the third MOS transistor, and the drain is used to output the level signal. The source of the sixth MOS transistor is connected to the drain of the fourth MOS transistor. The gate and drain of the sixth MOS transistor are interconnected and connected to the gate of the fifth MOS transistor.

8. The high-side drive no-load detection circuit according to claim 7, characterized in that, The drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor, the drain of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, the gates of the seventh and eighth MOS transistors are both connected to a bias voltage, and the sources of the seventh and eighth MOS transistors are both grounded.

9. The high-side drive no-load detection circuit according to claim 8, characterized in that, The fifth and sixth MOS transistors are both PMOS transistors, and the seventh and eighth MOS transistors are both NMOS transistors.

10. The high-side drive no-load detection circuit according to claim 1, characterized in that, When the voltage at the second input terminal of the comparison module is greater than the voltage at the first input terminal, a first level signal is output, indicating that the circuit under test is in an unloaded state. When the voltage at the second input terminal of the comparison module is less than the voltage at the first input terminal, a second level signal is output, and the first level signal is less than the second level signal, indicating that the circuit under test is in a non-unloaded state.

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