Wafer testing method and system with multi-dimensional performance

Abstract

The invention relates to the technical field of wafer testing, and discloses a multi-dimensional performance wafer testing method and system. The method comprises the following steps: defining N key performance dimensions of a wafer to be tested, wherein each dimension has quantifiable performance indexes and adjustable stress parameters; for each dimension, obtaining a condition mapping relation and determining a candidate optimal screening condition corresponding to the condition mapping relation; based on the candidate optimal screening condition of each dimension, determining the optimal screening condition of each dimension, and integrating to generate a multi-dimensional test vector set covering all the dimensions; a multi-dimensional test vector set is applied to each chip on a wafer to be tested for first-level screening, and a second test vector different from the multi-dimensional test vector set is applied to the screened chips for verification. According to the invention, the wafer test efficiency and reliability can be improved.

Description

Technical Field

[0001] This application relates to the field of wafer testing technology, and in particular to a wafer testing method and system for multi-dimensional performance. Background Technology

[0002] In semiconductor manufacturing, wafer testing is a critical step in ensuring chip performance and reliability. Traditional wafer testing methods typically focus on a single or a few performance dimensions (such as functionality, speed, power consumption, etc.) and use fixed test conditions based on experience or product specifications for screening. This testing approach has the following shortcomings: Limited testing dimensions: It is difficult to comprehensively evaluate the overall performance and reliability of chips under multi-stress environments, leading to an increased risk of potential defect escape. Non-optimized test conditions: The test stress parameters used are often not scientifically optimized and may not be the most effective defect induction conditions, resulting in low screening efficiency. Alternatively, excessively stringent test conditions may be used in pursuit of high reliability, increasing unnecessary testing costs and the risk of damage to good products. Lack of differentiated testing strategies: Using similar intensity testing strategies for chips at different value stages (such as the wafer stage and the post-packaging stage) throughout the manufacturing process fails to balance the need for efficient early defect removal with the need to protect high-value products later, resulting in low overall testing cost-effectiveness.

[0003] Therefore, there is an urgent need for a wafer testing method and system that can systematically define multiple key performance dimensions, scientifically determine the optimal test conditions for each dimension, and implement differentiated testing strategies according to the manufacturing process stages, so as to optimize testing efficiency and cost while ensuring the high reliability of the final product.

[0004] Therefore, the present invention provides a wafer testing method and system for multi-dimensional performance. Summary of the Invention

[0005] The embodiments in this specification provide the following technical solutions: Step S1: Define N key performance dimensions of the wafer under test. Each key performance dimension has a corresponding quantifiable performance index and an adjustable stress parameter. Step S2: For each key performance dimension, obtain the condition mapping relationship corresponding to that dimension, and obtain the candidate optimal screening conditions based on the condition mapping relationship; Step S3: Based on the candidate optimal screening conditions, determine the optimal screening conditions for each dimension, and generate a multi-dimensional test vector set based on the N optimal screening conditions. The multi-dimensional test vector set refers to the comprehensive test stress conditions that need to be applied in the wafer testing stage, covering N dimensions. Step S4: Apply a multi-dimensional test vector set to each chip on the wafer to be tested for the first level of screening. Apply a second test vector to the chips that pass the first level of screening test. The second test vector is different from the test vector in the multi-dimensional test vector set.

[0006] Compared with the prior art, the beneficial effects of the present invention are at least as follows: The technical solution provided in this application, by clearly defining multiple key performance dimensions and establishing their conditional mapping relationships, can scientifically and data-drivenly determine the optimal screening conditions for each dimension, and integrate and generate a coordinated multi-dimensional test vector set. This ensures that the testing scheme can efficiently and synchronously stimulate and detect multiple types of potential defects, significantly improving the completeness and screening efficiency of the test, and reducing the defect escape rate. A two-stage testing strategy of "strict screening at the front end and precise testing at the back end" is adopted. An optimized high-intensity multi-dimensional test vector set is applied at the first level of the wafer testing stage, efficiently eliminating defective products in the early, low-cost manufacturing stage. In the post-packaging testing stage, relatively mild and comprehensive testing conditions (such as standard operating conditions or the safest conditions) are used to verify product compliance with specifications while minimizing the potential damage risk to high-value packaged chips. By continuously collecting data and training predictive models during the testing process, the influence of each test parameter on the final result is quantitatively analyzed, and the test vector set is dynamically optimized (such as strengthening key parameters and eliminating redundant parameters). This allows the testing scheme to adapt to process fluctuations and product evolution, possessing self-learning and continuous improvement capabilities, and maintaining long-term testing efficiency and economy. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of one embodiment of a wafer testing method for multi-dimensional performance in this application. Figure 2 This is a schematic diagram of one embodiment of a wafer testing system for multi-dimensional performance in this application. Detailed Implementation

[0009] This application provides a wafer testing method and system for multi-dimensional performance. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0010] For ease of understanding, the specific process of the embodiments of this application is described below. Please refer to [link / reference]. Figure 1 One embodiment of a wafer testing method for multi-dimensional performance in this application includes: Step S1: Define N key performance dimensions of the wafer under test. Each key performance dimension has a corresponding quantifiable performance index and an adjustable stress parameter. Specifically, existing wafer testing methods suffer from problems such as limited evaluation dimensions, non-optimized testing conditions, and a failure to differentiate between cost and risk in the overall testing strategy, resulting in low screening efficiency, significant product reliability risks, and high overall testing costs. Therefore, this application aims to fundamentally improve wafer reliability and optimize the total cost of the entire testing process by optimizing across multiple dimensions and implementing differentiated testing strategies in stages.

[0011] To achieve structured and explicit testing objectives, based on product specifications, typical stress conditions of the target application scenario, and known failure mode analysis, the dimensions to be tested are determined. For example, for wafers used to manufacture high-performance processors, four key dimensions can be defined: dynamic timing performance, power consumption-performance efficiency, thermal stability, and power supply noise margin. For each dimension, the timing margin at the highest operating frequency, the operating power consumption under a specific load, the junction temperature rise rate, and the lowest operating voltage are selected as performance indicators. The test clock frequency, dynamic load current, power density, and voltage ripple amplitude are selected as corresponding adjustable stress parameters. This transforms vague quality requirements into specific, measurable, and controllable technical tasks, ensuring the completeness and purposefulness of the testing scheme and avoiding testing blind spots. Here, N is an integer greater than or equal to 2.

[0012] Step S2: For each key performance dimension, obtain the condition mapping relationship corresponding to that dimension, and obtain the candidate optimal screening conditions based on the condition mapping relationship; Specifically, even with multiple key performance dimensions defined, it remains unclear what testing intensity is most effective for each dimension. Blindly using fixed or empirical values ​​may lead to inefficient screening (defect escape) or increased testing costs (overtesting). To avoid these problems, optimal testing conditions need to be found. This requires establishing a conditional mapping relationship for each key performance dimension through controlled experiments—that is, a correlation model between stress parameters and evaluation parameters. This conditional mapping relationship is obtained through testing and refers to the correspondence between stress parameters and evaluation parameters obtained by testing the same batch of wafers under multiple different stress parameters. A batch of statistically significant reference wafers (usually from early production batches) can be used for parameter scanning testing in a controlled laboratory setting. For each key performance dimension, the reference wafers are tested under a series of values ​​for their corresponding stress parameters. Performance index data is collected, and evaluation parameters reflecting quality, such as failure rate, parameter exceedance rate, and performance degradation slope, are calculated. This step transforms the selection of test conditions from experience-driven to data-driven, obtaining the condition mapping relationship for each key performance dimension. Subsequently, based on the condition mapping relationship, it can be determined under what test conditions the corresponding dimension's defects are most easily triggered and detected, providing a key basis for subsequent optimization of the test plan.

[0013] Step S3: Based on the candidate optimal screening conditions, determine the optimal screening conditions for each dimension, and generate a multi-dimensional test vector set based on the N optimal screening conditions. The multi-dimensional test vector set refers to the comprehensive test stress conditions that need to be applied in the wafer testing stage, covering N dimensions. Specifically, to generate a high-performance test plan and ensure that every test vector applied in wafer testing is scientifically validated to maximize overall screening efficiency, extreme points of stress parameters are identified based on the conditional mapping relationship of each key performance dimension. The stress parameters corresponding to these extreme points are determined as the optimal screening conditions for that dimension. Then, the optimal screening conditions for all dimensions are encoded to generate a multi-dimensional test vector set, which serves as the standard operating procedure for subsequent mass production testing. This step obtains the optimal test points independently for each dimension and integrates them to generate a coordinated, efficient, and unified test plan that can be executed in large-scale testing.

[0014] Step S4: Apply a multi-dimensional test vector set to each chip on the wafer to be tested for the first level of screening. Apply a second test vector to the chips that pass the first level of screening test. The second test vector is different from the test vector in the multi-dimensional test vector set.

[0015] Specifically, in order to proactively and efficiently identify potentially defective products at the early, lowest-cost stage of the manufacturing process during high-speed, large-scale wafer testing, and prevent them from flowing into subsequent high-cost stages, automated testing equipment is used. Each test vector in a multi-dimensional test vector set is configured into a runnable test program. After the probe station contacts the wafer, for each chip on the wafer under test, a predefined combination of stress waveforms is generated and applied according to the generated test program. At the same time, the response signal of the chip is acquired at high speed. The automated testing equipment performs the first level of screening according to preset screening criteria (such as all functional tests are correct, peak current is less than a preset current threshold, and temperature rise is less than a preset temperature threshold). If any criterion is not met, the chip is marked as defective on the wafer coating. Through the first level of screening, early detection and early rejection are achieved, significantly reducing the subsequent processing cost of defective chips and improving the reliability and yield of the final product.

[0016] Chips that pass the first-level screening test will proceed to the subsequent packaging stage. After packaging, the value of each chip increases significantly. Continuing with high-intensity testing at this stage would greatly increase the risk of damaging good products, leading to unnecessary economic losses. To protect high-value wafers and ensure that the quality of the wafers leaving the factory meets standards while minimizing the potential risks of testing, a gentle and comprehensive testing approach is adopted. Through precise functional verification and performance parameter measurement, the chips are ensured to meet factory specifications, while avoiding damage introduced by the testing process itself. Therefore, in the post-packaging testing stage, the chips are placed in test sockets, and a second test vector is applied using automated testing equipment. The second test vector differs in intensity from the first test vector; its stress parameters typically use the safest conditions corresponding to the lowest damage rate shown in standard test conditions or mapping relationships. By applying the second test vector to test the wafer chips, the potential risks of testing are minimized while ensuring the quality of the wafers leaving the factory meets standards, forming a collaborative, efficient, and cost-effective complete testing process that combines rigorous screening at the front end with precise testing at the back end.

[0017] In one specific embodiment, obtaining the conditional mapping relationship corresponding to this dimension includes the following steps: Within a predetermined temperature range, several different temperature points are selected. At each temperature point, a stress parameter is selected as the target stress parameter. Other stress parameters are fixed except for the target stress parameter. The target stress parameter is systematically modified. For each stress parameter value, a set of sample wafers is tested, and the corresponding evaluation parameters are calculated to obtain the correspondence data between the stress parameters and the evaluation parameters. Data analysis software is used to process the corresponding data to obtain the trend line of the evaluation parameter changing with the stress parameter. Based on the trend line, all maximum points are identified, and the stress parameter values ​​corresponding to the maximum points are determined as the candidate optimal screening conditions at the corresponding temperature points. The optimal screening conditions are obtained based on the candidate optimal screening conditions.

[0018] Specifically, to obtain a high-quality, multi-dimensional basic dataset, sample wafers are placed in a variable temperature-controlled probe station. A first temperature point is set, and other conditions are fixed. Assuming the target stress parameter is the pulse width, the pulse width is systematically modified, for example, from 1 μs to 100 μs. Ten points are taken, and a group of sample wafers are tested at each pulse width. The junction temperature rise of each chip on the sample wafer or the transient drift of a certain temperature-sensitive parameter is measured. A safety threshold is set, and the number of chips with a junction temperature rise greater than the safety threshold at each pulse width is counted. The failure rate (evaluation parameter) is calculated, and finally a set of data points is obtained: {(pulse width 1, failure rate 1), (pulse width 2, failure rate 2), ...}, which is used to represent the correspondence between pulse width and evaluation parameter.

[0019] To objectively and accurately identify the most discriminative stress parameter values ​​from a large amount of basic data, based on the principles of data analysis and feature extraction, the corresponding relationship data at each temperature point is automatically analyzed to identify the trend and characteristic points of the evaluation parameter's variation with the target stress parameter. The peak point is then used as the most effective candidate value for screening at that temperature point. First, multiple sets of corresponding relationship data for each temperature point are imported using data analysis software. Each set of corresponding relationship data represents the relationship between a certain stress parameter and its corresponding evaluation parameter. Since there may be multiple stress parameters in each dimension, there are multiple sets of corresponding relationship data. A second-order polynomial analysis is performed on each set of corresponding relationship data. The formula is fitted to obtain a smooth relationship curve. The derivative of each curve is calculated, and the point where the derivative is zero and the second derivative is negative is found. This is the local maximum point, which is the peak point. The stress parameter value corresponding to the local maximum point, such as the point with a pulse width of 50μs, is used as the candidate optimal screening condition. The meaning of the optimal screening condition is that the specific and quantifiable stress parameter value for a certain key performance dimension, when the chip is tested in the corresponding dimension using this stress parameter value, can make the evaluation parameter of the corresponding dimension reach an extreme value. So that when the chip is tested under the optimal screening condition, the problematic chip is most easily excited and thus quickly detected.

[0020] In one specific embodiment, the optimal screening criteria for each dimension are determined based on the candidate optimal screening criteria, specifically including the following steps: For multiple different candidate optimal screening conditions obtained at different temperatures, the peak characteristic value of each candidate optimal screening condition is calculated, and the stress parameter value corresponding to the candidate optimal screening condition with the largest peak characteristic value is taken as the optimal screening condition for the corresponding dimension.

[0021] Specifically, multiple different candidate optimal screening conditions may be obtained at different temperatures, and one needs to be selected as the final optimal screening condition. Therefore, for multiple different candidate optimal screening conditions obtained at different temperatures, the peak characteristic value corresponding to each candidate optimal screening condition is calculated. The peak characteristic value refers to the peak height or the contrast with the adjacent valley value. The higher the peak height or the greater the contrast with the adjacent valley value, the more significant the peak characteristic of the candidate optimal screening condition corresponding to the corresponding temperature point is. Therefore, the stress parameter value corresponding to the candidate optimal screening condition with the largest peak characteristic value is taken as the optimal screening condition for the corresponding dimension, which means that the test defect has the strongest discrimination ability under this dimension.

[0022] It should be noted that if the relationship curves at all temperature points are found to be very flat, for example, the peak feature is less than the preset peak threshold, the test temperature range is expanded to obtain new corresponding relationship data after the expansion of the temperature range, and new candidate optimal screening conditions are obtained based on the new corresponding relationship data, and then the optimal screening condition is selected based on the new candidate optimal screening conditions.

[0023] Furthermore, a multidimensional test vector set is generated based on N optimal selection criteria, specifically including the following steps: The multidimensional test vector set includes an N-dimensional stress parameter set, a target value set, and test sequences and conditions. Each element in the stress parameter set corresponds to a stress parameter, and each element in the target value set is the parameter value of the stress parameter determined by the optimal screening conditions of the corresponding dimension. The test sequences and conditions refer to the order, time interval, duration of each stress parameter, and environmental configuration when multiple stress parameters are applied during actual testing.

[0024] Specifically, assuming a total of N = 2, there are two key performance dimensions, each with a stress parameter. Dimension A is dynamic switching performance and gate oxide integrity, focusing on the chip's ability to withstand high-frequency voltages during rapid switching. The corresponding stress parameter is assumed to be the rise slope of the gate-source voltage. The optimal screening condition is that at 125°C, when the rise slope of the gate-source voltage is 5V / ns, the proportion of chips with excessive gate leakage (damage) reaches its peak (e.g., 30%). Let Pa represent the rise slope; therefore, the optimal screening condition is Pa = 5V / ns (at 125°C). Dimension B is power supply voltage fluctuation tolerance, focusing on the impact of internal logic circuitry on power bus noise. The immunity to sound is assumed to be based on the amplitude of the triangular wave noise superimposed on the power supply voltage. The optimal screening condition is: at room temperature of 25℃, with noise injected at a frequency of 10MHz, the chip reaches its peak rate of functional error or reset failure when the amplitude of the triangular wave noise superimposed on the power supply voltage is equal to 300mV. Let Vp represent the amplitude of the triangular wave noise superimposed on the power supply voltage. Therefore, the optimal screening condition is Vp=300mV (at 25℃ and a noise frequency of 10MHz). Then, the N-dimensional stress parameter set of the multidimensional test vector set is the rising slope and the amplitude of the triangular wave noise superimposed on the power supply voltage. The target value set is 5V / ns and 300mV.

[0025] Multiple stress conditions cannot always be applied simultaneously. They may conflict with each other, be dependent on each other, or be limited by hardware resources. Improper or simplistic simultaneous application may lead to test failure, equipment damage, or even chip damage. Therefore, it is necessary to coordinate the application of stress parameters in terms of time, hardware resources, and logic to ensure that the test is safe, effective, and efficient. This involves defining the test sequence and conditions, clearly specifying the application method, application duration, and environmental configuration. The application method refers to which parameters are applied simultaneously and which parameters are applied sequentially. The time interval refers to the time interval between parameter applications. The duration refers to the length of time each stress parameter is applied. The environmental configuration refers to whether and how the environmental conditions need to be changed (such as switching temperatures) when applying stress parameters.

[0026] The above method systematically and without conflict integrates multiple independent optimal screening conditions targeting different performance dimensions into a single, coordinated overall test plan that can be executed safely and efficiently on automated test equipment, preventing test failures, inefficiencies, or equipment risks caused by improper integration.

[0027] In one specific embodiment, applying a multi-dimensional test vector set for the first level of screening includes the following steps: The wafer under test is configured into a test state. For each chip on the wafer, based on a multi-dimensional test vector set, each stress parameter in the stress parameter set is adjusted to the corresponding target value according to the test sequence. During the test duration in which the parameter values ​​are maintained, the evaluation parameters corresponding to N key performance dimensions are monitored and recorded. Based on the monitoring results, it is determined whether all evaluation parameters meet the corresponding preset screening criteria. If any evaluation parameter of any dimension does not meet the corresponding screening criteria, it is determined that the corresponding chip does not pass the first level of screening.

[0028] Specifically, before testing, the chip may be in any unknown state (such as the residual state of the previous test). Directly applying high pressure or high frequency stress may damage the chip. To ensure that the starting point of each test is consistent and safe, the wafer under test is configured in a test state. For example, all chip pins are placed at known locations, and the chip's internal controller is configured to standby mode. Then, the test environment is adjusted to the environmental configuration corresponding to each stress parameter in the multi-dimensional test vector set (such as ambient temperature or noise frequency). Then, according to the test sequence in the multi-dimensional test vector set, each stress parameter is adjusted to its corresponding value. For parameters that need to be applied concurrently, automatic test equipment is used to trigger them synchronously at the same time. For parameters that need to be applied sequentially... The added parameters are based on the corresponding order, time interval, and application duration. After the previous stress parameter is applied, the next one is applied in sequence. While applying the stress parameters, the corresponding performance indicators are monitored using automatic testing equipment, and evaluation parameters are calculated based on the performance indicators. After the test, it is checked whether the evaluation parameters for each dimension meet the corresponding screening criteria. For example, for dimension A, is the damage rate less than 5%? If so, it means that the screening criteria are met. If any evaluation parameter for any dimension does not meet the corresponding screening criteria, the corresponding chip is judged not to pass the first level of screening. If the evaluation parameters for all dimensions meet the corresponding screening criteria, the corresponding chip is judged to pass the first level of screening.

[0029] In one specific embodiment, applying the second test vector specifically includes the following steps: Based on the wafer product specification sheet, recommended operating conditions are extracted, and standard test vectors are generated based on the standard stress parameter values ​​of the recommended operating conditions in each dimension. Obtain the trend line of the evaluation parameters obtained when calculating the optimal screening conditions as a function of each stress parameter, identify the stress parameter value corresponding to the minimum point of the trend line as the safety test condition of the corresponding dimension, and generate a safety test vector based on all safety test conditions. The standard test vector and the security test vector are combined to generate the second test vector.

[0030] Specifically, to ensure testing compliance, recommended operating conditions are extracted from the wafer's specifications. Standard test vectors are generated based on the standard stress parameter values ​​for each dimension provided in the specifications. For example, if the specifications specify a minimum input voltage of 2V, then 2V is used as the final tolerance when considering input level tolerance. By generating standard test vectors, the product is ensured to be qualified for shipment.

[0031] Ensuring wafer compliance with specifications is fundamental. Further verification of chip robustness is required. This involves obtaining a trend line of evaluation parameters changing with stress parameters when calculating optimal screening conditions, identifying the stress parameter values ​​corresponding to the minimum points of the trend lines, and recognizing that the stress parameter values ​​corresponding to the minimum points represent the minimum potential damage to the chip from the applied stress parameter values. By generating a safety test vector from the set of safety test conditions corresponding to each dimension, the theoretically safest test based on scientific data can be achieved.

[0032] The standard test vector and the safety test vector are combined to generate the second test vector. The combination process is the same as the method of generating a multi-dimensional test vector set based on the optimal screening conditions. The generated second test vector ensures that the chip meets the basic product specifications through the standard test vector, and further ensures that the chip is not damaged and ensures the stability of the chip based on the safety test vector.

[0033] In one specific embodiment, after step S4, the following steps are also performed: During the first-level screening test, test data is continuously collected and used as a training dataset to train a prediction model. The prediction model is used to establish the correlation between stress parameters and the final test results, and can also obtain the degree of influence of stress parameters on the test results. Based on the prediction model, the multi-dimensional test vector set is optimized.

[0034] Specifically, a key performance indicator typically corresponds to multiple stress parameters, and multiple key performance indicators correspond to a large number of stress parameters. Faced with a large number of stress parameters, it is difficult for humans to discover the hidden nonlinear and complex correlations. Therefore, during the first-level screening test, test data is continuously collected. The test data includes stress parameters of various dimensions and test results. The test results refer to whether the chip passes the test. A prediction model is trained. The prediction model takes stress parameters as input and the final test result as the output target. By training the prediction model with the training dataset, the prediction model can not only predict, but also reveal which stress parameters of which dimensions are truly effective parameters for quality evaluation, and which may be redundant parameters or noise. In other words, it can obtain the degree of influence of each stress parameter on the final test result based on the prediction model. Based on the degree of influence, the multi-dimensional test vector set is optimized, providing a scientific and quantitative basis for optimizing the test plan.

[0035] In one specific embodiment, the optimization of the multidimensional test vector set based on the prediction model includes the following steps: Based on the prediction model, the influence of each stress parameter on the prediction result is obtained. Several stress parameters with the greatest influence are selected as the first stress parameters, and several stress parameters with the least influence are selected as the second stress parameters. When generating the multidimensional test vector set, the application time is increased for the parameter value corresponding to the first stress parameter, and the second stress parameter is deleted from the multidimensional test vector set.

[0036] Specifically, the multidimensional test vector set is generated based on all stress parameters. However, not all stress parameters may contribute significantly to the final quality evaluation; some may contribute very little to the screening. Therefore, the influence of corresponding stress parameters on the test results is obtained based on the prediction model. The greater the influence, the greater the contribution of the corresponding stress parameter to the test results, and the more important it is to the final test results. Thus, the influence of each stress parameter on the prediction results is obtained based on the prediction model, and the 10 stress parameters with the greatest influence are selected as the first stress parameters (e.g., the 10 most influential stress parameters). The 10 stress parameters with the least influence are selected as the second stress parameters (e.g., the 10 least influential stress parameters). In subsequent testing, when generating the multidimensional test vector set, the application time of the parameter values ​​corresponding to the first stress parameters is increased to more thoroughly stimulate the relevant defects, thereby achieving the same screening effect with fewer other tests and even improving the overall accuracy. For the second stress parameters, since their influence on the final test results is particularly small, the corresponding stress parameters and parameter values ​​are deleted from the multidimensional test vector, thereby reducing the number of test points and thus reducing the test time.

[0037] The above describes a wafer testing method for multi-dimensional performance in embodiments of this application. The following describes a wafer testing system for multi-dimensional performance in embodiments of this application. Please refer to [link to relevant documentation]. Figure 2 One embodiment of a multi-dimensional performance wafer testing system in this application includes: The dimension definition unit defines N key performance dimensions of the wafer under test. Each key performance dimension has a corresponding quantifiable performance index and an adjustable stress parameter. The first screening unit obtains the condition mapping relationship corresponding to each key performance dimension, and obtains the candidate optimal screening conditions based on the condition mapping relationship; The second screening unit determines the optimal screening condition for each dimension based on the candidate optimal screening conditions, and generates a multi-dimensional test vector set based on the N optimal screening conditions. The multi-dimensional test vector set refers to the comprehensive test stress conditions covering N dimensions that need to be applied during the wafer testing stage. The wafer testing unit applies a multi-dimensional test vector set to each chip on the wafer under test for the first level of screening. For chips that pass the first level of screening, a second test vector is applied, which is different from the test vectors in the multi-dimensional test vector set.

[0038] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0039] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0040] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A wafer testing method for multi-dimensional performance, characterized in that, The method includes: Step S1: Define N key performance dimensions of the wafer under test. Each key performance dimension has a corresponding quantifiable performance index and an adjustable stress parameter. Step S2: For each key performance dimension, obtain the condition mapping relationship corresponding to that dimension, and obtain the candidate optimal screening conditions based on the condition mapping relationship; Step S3: Based on the candidate optimal screening conditions, determine the optimal screening conditions for each dimension, and generate a multi-dimensional test vector set based on the N optimal screening conditions. The multi-dimensional test vector set refers to the comprehensive test stress conditions that need to be applied in the wafer testing stage, covering N dimensions. Step S4: Apply a multi-dimensional test vector set to each chip on the wafer to be tested for the first level of screening. Apply a second test vector to the chips that pass the first level of screening test. The second test vector is different from the test vector in the multi-dimensional test vector set.

2. The method according to claim 1, characterized in that, Retrieve the conditional mapping relationship corresponding to this dimension, including: Within a predetermined temperature range, several different temperature points are selected. At each temperature point, a stress parameter is selected as the target stress parameter. Other stress parameters are fixed except for the target stress parameter. The target stress parameter is systematically modified. For each stress parameter value, a set of sample wafers is tested, and the corresponding evaluation parameters are calculated to obtain the correspondence data between the stress parameters and the evaluation parameters. Data analysis software is used to process the corresponding data to obtain the trend line of the evaluation parameter changing with the stress parameter. Based on the trend line, all maximum points are identified, and the stress parameter values ​​corresponding to the maximum points are determined as the candidate optimal screening conditions at the corresponding temperature points. The optimal screening conditions are obtained based on the candidate optimal screening conditions.

3. The method according to claim 1, characterized in that, Based on the candidate optimal screening criteria, the optimal screening criteria are determined for each dimension, including: For multiple different candidate optimal screening conditions obtained at different temperatures, the peak characteristic value of each candidate optimal screening condition is calculated, and the stress parameter value corresponding to the candidate optimal screening condition with the largest peak characteristic value is taken as the optimal screening condition for the corresponding dimension.

4. The method according to claim 1, characterized in that, A multidimensional test vector set is generated based on N optimal selection criteria, including: The multidimensional test vector set includes an N-dimensional stress parameter set, a target value set, and test sequences and conditions. Each element in the stress parameter set corresponds to a stress parameter, and each element in the target value set is the parameter value of the stress parameter determined by the optimal screening conditions of the corresponding dimension. The test sequences and conditions refer to the order, time interval, duration of each stress parameter, and environmental configuration when multiple stress parameters are applied during actual testing.

5. The method according to claim 1, applying a multi-dimensional test vector set for first-level screening, comprising: The wafer under test is configured into a test state. For each chip on the wafer, based on a multi-dimensional test vector set, each stress parameter in the stress parameter set is adjusted to the corresponding target value according to the test sequence. During the test duration in which the parameter values ​​are maintained, the evaluation parameters corresponding to N key performance dimensions are monitored and recorded. Based on the monitoring results, it is determined whether all evaluation parameters meet the corresponding preset screening criteria. If any evaluation parameter of any dimension does not meet the corresponding screening criteria, it is determined that the corresponding chip does not pass the first level of screening.

6. The method according to claim 1, characterized in that, Apply a second test vector, including: Based on the wafer product specification sheet, recommended operating conditions are extracted, and standard test vectors are generated based on the standard stress parameter values ​​of the recommended operating conditions in each dimension. Obtain the trend line of the evaluation parameters as stress parameters change when calculating the optimal screening conditions, identify the stress parameter values ​​corresponding to the minimum points of the trend line as the safety test conditions of the corresponding dimensions, and generate a safety test vector based on all safety test conditions. The standard test vector and the security test vector are combined to generate the second test vector.

7. The method according to claim 1, characterized in that, Following step S4, the following is also included: During the first-level screening test, test data is continuously collected and used as a training dataset to train a prediction model. The prediction model is used to establish the correlation between stress parameters and the final test results, and can also obtain the degree of influence of stress parameters on the test results. Based on the prediction model, the multi-dimensional test vector set is optimized.

8. The method according to claim 7, characterized in that, Optimization of the multidimensional test vector set based on the prediction model includes: Based on the prediction model, the influence of each stress parameter on the prediction result is obtained. Several stress parameters with the greatest influence are selected as the first stress parameters, and several stress parameters with the least influence are selected as the second stress parameters. When generating the multidimensional test vector set, the application time is increased for the parameter value corresponding to the first stress parameter, and the second stress parameter is deleted from the multidimensional test vector set.

9. A wafer testing system for multi-dimensional performance, used to implement the wafer testing method for multi-dimensional performance as described in any one of claims 1-8, characterized in that, The system includes: The dimension definition unit defines N key performance dimensions of the wafer under test. Each key performance dimension has a corresponding quantifiable performance index and an adjustable stress parameter. The first screening unit obtains the condition mapping relationship corresponding to each key performance dimension, and obtains the candidate optimal screening conditions based on the condition mapping relationship; The second screening unit determines the optimal screening condition for each dimension based on the candidate optimal screening conditions, and generates a multi-dimensional test vector set based on the N optimal screening conditions. The multi-dimensional test vector set refers to the comprehensive test stress conditions covering N dimensions that need to be applied during the wafer testing stage. The wafer testing unit applies a multi-dimensional test vector set to each chip on the wafer under test for the first level of screening. For chips that pass the first level of screening, a second test vector is applied, which is different from the test vectors in the multi-dimensional test vector set.

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