Chip packaging module structure

Abstract

The invention discloses a chip packaging module structure, and relates to the technical field of optical communication and photoelectric co-packaging, and the chip packaging module structure comprises a circuit board, an insulating substrate, a photonic integrated chip and an optical array assembly. Wherein the insulating substrate is arranged on one side of the circuit board; the photonic integrated chip is arranged on the insulating substrate, and the photonic integrated chip is provided with an optical waveguide; the optical fiber array assembly is supported on the substrate or the circuit board, and the optical fiber array assembly can move relative to the insulating substrate so as to be in butt joint with the connecting port of the optical waveguide for optical coupling; wherein a connecting port of the optical waveguide is directly or indirectly laterally exposed out of the periphery of the insulating substrate; according to the invention, by optimizing the layout and integration mode of the photonic integrated chip and the electronic integrated chip on the glass insulation substrate, the problem that the output end of the photonic integrated chip is polluted is avoided, and meanwhile, the convenience and coupling efficiency of optical interconnection are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optical communication and optoelectronic co-packaging technology, and particularly relates to a chip packaging module structure. BACKGROUND

[0002] With the rapid development of artificial intelligence, big data and high-performance computing technologies, the global data volume is growing exponentially, which puts forward higher requirements for data transmission bandwidth, energy efficiency and delay. Traditional pluggable optical modules use electrical interconnection, and the communication rate is limited. Moreover, the power consumption of the integrated digital signal processing chip (DSP) in the pluggable optical module accounts for 40%-50%, which becomes the bottleneck of energy efficiency. In addition, the transmission distance of the serializer (SerDes) of the pluggable optical module is limited, which is difficult to meet the growing demand for data traffic.

[0003] In order to improve the integration and reduce the power consumption, the optoelectronic co-packaging technology (CPO) emerges as the times require. The CPO integrates the optical engine and the application-specific integrated circuit chip on the same packaging insulating substrate, and significantly reduces the power consumption and signal loss by shortening the interconnection distance and eliminating the DSP. Research shows that the CPO can reduce the optical interconnection power consumption by about 70%, reduce the overall system power consumption by 30%, and improve the bandwidth and transmission efficiency.

[0004] In the traditional chip packaging module structure, the optical waveguide of the photonic integrated chip is usually arranged in the end face structure of the substrate. In this structure, the light-emitting structure of the photonic chip is easily contaminated during the process of installing the bottom filling glue, thereby affecting the transmission of the signal. Moreover, when the optical waveguide is arranged in the end face of the substrate, the coupling connection between the optical fiber array (hundred microns in diameter) and the optical waveguide (hundred nanometers in width) has low alignment efficiency and is prone to mechanical interference, which is not conducive to efficient alignment and coupling using the optical fiber coupling platform and expanding the optical communication capacity. SUMMARY

[0005] The main purpose of the present application is to provide a chip packaging module structure, which aims to solve the problem that the integrated position layout of the chip structure in the traditional chip packaging module structure is difficult to realize efficient coupling of optical fibers and expand the optical communication capacity.

[0006] To achieve the above purpose, the chip packaging module structure provided by the present application comprises: a circuit board; an insulating substrate arranged on one side of the circuit board; a photonic integrated chip arranged on the insulating substrate, the photonic integrated chip having an optical waveguide; and an optical fiber array assembly supported on the substrate or the circuit board, the optical fiber array assembly being movable relative to the insulating substrate to be optically coupled to the connection port of the optical waveguide; The connecting port of the optical waveguide directly or indirectly laterally exposes the periphery of the insulating substrate.

[0007] In an embodiment, the insulating substrate is entirely on the side of the photonic integrated chip facing the circuit board. The optical waveguide directly laterally exposes the periphery of the insulating substrate.

[0008] In an embodiment, the insulating substrate and the photonic integrated chip are arranged in a spaced manner. The optical waveguide laterally protrudes from the periphery of the insulating substrate. The optical fiber array assembly is supported on the circuit board by a support.

[0009] In an embodiment, the side of the insulating substrate facing away from the circuit board is provided with a first mounting groove, the photonic integrated chip is partially sunk in the first mounting groove, a first filling area is formed between the first mounting groove and the end of the photonic integrated chip for filling underfill adhesive, and the optical waveguide is at least partially attached to the insulating substrate. The optical fiber array assembly is supported on the insulating substrate. The position where the optical waveguide and the optical fiber array assembly are optically coupled is on the insulating substrate.

[0010] In an embodiment, the side of the insulating substrate facing away from the circuit board is provided with a second mounting groove, the bottom wall of the second mounting groove is further provided with a third mounting groove, the photonic integrated chip is partially sunk in the third mounting groove, a second filling area is formed between the third mounting groove and the end of the photonic integrated chip for filling underfill adhesive. The side wall of the second mounting groove laterally shields the optical waveguide, a photonic lead is arranged in the side wall of the second mounting groove, one end of the photonic lead is optically coupled to the optical waveguide, and the other end of the photonic lead is laterally led out of the insulating substrate, so that the optical waveguide indirectly laterally exposes the periphery of the insulating substrate through the photonic lead. The optical fiber array assembly is supported on the circuit board by a support.

[0011] In an embodiment, the chip package module structure further comprises an electronic integrated chip and a host-specific integrated circuit chip, the photonic integrated chip and the electronic integrated chip are arranged at the same end in the thickness direction of the insulating substrate or are arranged at two ends in the thickness direction of the insulating substrate, and the photonic integrated chip and the electronic integrated chip are connected, the host-specific integrated circuit chip is arranged on the insulating substrate and connected with the electronic integrated chip; and / or, The insulating substrate is configured as a glass insulating substrate.

[0012] In one embodiment, the insulating substrate is provided with a plurality of through holes for conducting through its two ends in the thickness direction; When the photonic integrated chip and the electronic integrated chip are disposed at opposite ends in the thickness direction of the insulating substrate, the photonic integrated chip and the electronic integrated chip are vertically interconnected through a plurality of vias.

[0013] In one embodiment, the circuit board is disposed on the side of the electronic integrated chip away from the insulating substrate; A gap is formed between the circuit board and the insulating substrate; The circuit board has a recessed section, and the electronic integrated chip is at least partially disposed in the recessed section, so that the other end of the electronic integrated chip is located in the gap space.

[0014] In one embodiment, both the photonic integrated chip and the electronic integrated chip are disposed at the end of the insulating substrate away from the circuit board; Multiple photonic integrated chips and multiple electronic integrated chips are provided, and one photonic integrated chip is connected to multiple electronic integrated chips to form multiple photonic engines on one end of the insulating substrate, and multiple waveguides in the multiple photonic engines are provided at the peripheral position of the insulating substrate.

[0015] In one embodiment, the host application-specific integrated circuit chip is disposed at the end of the insulating substrate away from the circuit board; and / or, One of the photonic integrated chip, the electronic integrated chip, and the host dedicated integrated circuit chip is set as the first chip. The chip packaging module structure also includes a heat sink assembly, which is at least connected to the first chip to cool the first chip.

[0016] This invention optimizes the layout and integration of photonic integrated chips and electronic integrated chips on a glass insulating substrate, avoiding the problem of contamination at the output end of the photonic integrated chip, while effectively improving the convenience and coupling efficiency of optical interconnection, and enhancing the mechanical strength and heat dissipation performance of the packaging structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the first embodiment of the chip packaging module structure provided by the present invention; Figure 2 This is a schematic diagram of the second embodiment of the chip packaging module structure provided by the present invention; Figure 3 This is a schematic diagram of the third embodiment of the chip packaging module structure provided by the present invention; Figure 4 This is a top view of the fourth embodiment of the chip packaging module structure provided by the present invention.

[0019] Explanation of icon numbers: 100. Chip packaging module structure; 1. Liquid cooling heat sink; 2. Thermal interface material; 3. Photonic integrated chip; 4. Wiring layer; 5. Optical waveguide; 6. Insulating substrate; 7. Fiber optic array assembly; 8. Optical fiber; 9. Through-hole section; 10. Electronic integrated chip; 11. Circuit board; 12. Solder ball; 13. Underfill adhesive; 14. Copper pillar solder joint; 15. Host dedicated integrated circuit chip; 16. Fiber optic array support; 17. Photonic lead; 18. Microcontroller chip.

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0024] With the rapid development of technologies such as artificial intelligence, big data, and high-performance computing, the global data volume is growing exponentially, placing higher demands on data transmission bandwidth, energy efficiency, and latency. Traditional pluggable optical modules use electrical interconnects, resulting in limited communication rates. Furthermore, the power consumption of their integrated digital signal processing chips (DSPs) accounts for as much as 40%-50%, becoming a bottleneck for energy efficiency. In addition, the serializer (SerDes) of pluggable optical modules has limited transmission distance, making it difficult to meet the ever-increasing data traffic demands.

[0025] To improve integration and reduce power consumption, co-packaged optoelectronics (CPO) technology has emerged. CPO integrates the optical engine and application-specific integrated circuit (ASIC) chip onto the same insulated substrate, significantly reducing power consumption and signal loss by shortening interconnect distances and eliminating DSPs. Studies have shown that CPO can reduce optical interconnect power consumption by approximately 70% and overall system power consumption by 30%, while simultaneously improving bandwidth and transmission efficiency.

[0026] In traditional chip packaging module structures, the optical waveguide of a photonic integrated chip is usually placed within the end face structure of its substrate. This arrangement can easily contaminate the light-emitting structure of the photonic chip during the installation of the bottom filler adhesive, thus affecting signal transmission. Furthermore, placing the optical waveguide within the end plane of the substrate can easily cause mechanical interference when the fiber array and the optical waveguide are coupled, which is not conducive to efficient alignment and coupling using a fiber optic coupling platform.

[0027] This invention proposes a chip packaging module structure.

[0028] Please see Figure 1In one embodiment of the present invention, the chip packaging module structure 100 includes a circuit board 11, an insulating substrate 6, a photonic integrated chip 3, and a fiber array assembly 7. The insulating substrate 6 is disposed on one side of the circuit board 11; the photonic integrated chip 3 is disposed on the insulating substrate 6 and has an optical waveguide 5; the fiber array assembly 7 is supported on the substrate or the circuit board 11, and the fiber array assembly 7 is movable relative to the insulating substrate 6 to optically couple with the connection port of the optical waveguide 5; wherein the connection port of the optical waveguide 5 is directly or indirectly exposed laterally to the periphery of the insulating substrate 6.

[0029] Co-packaged optical (CPO) is an advanced packaging technology that integrates optical modules and electrical chips onto the same package board. It is mainly used in hyperscale data centers, AI computing clusters, high-performance switches, and optical communication equipment.

[0030] In the entire packaging structure, the fiber array assembly 7 and the optical waveguide 5 structure on the photonic integrated chip 3 need to be coupled to conduct optical signals. In conventional structures, the optical waveguide 5 of the photonic integrated chip 3 is usually disposed within the end face structure of its substrate. In this arrangement, during the end-to-end mounting of the photonic chip, the bottom filler 13 used for mounting is prone to contaminating the port of the optical waveguide 5, thereby affecting signal transmission.

[0031] The above-described embodiments effectively solve the aforementioned problems. Specifically, the optical waveguide 5 is positioned close to the outer periphery of the insulating substrate 6, directly or indirectly exposing the periphery of the insulating substrate 6. This effectively prevents the bottom filler adhesive 13 from flowing onto the optical waveguide 5 and contaminating the optical port. Furthermore, an optical coupling portion or a coupling structure protruding from the outer periphery of the insulating substrate 6 is formed on the outer peripheral wall of the insulating substrate 6. During actual optical coupling, the fiber array assembly 7 does not need to move to the end plane of the insulating substrate 6 for optical coupling; the coupling connection between the fiber 8 on the fiber array assembly 7 and the optical waveguide 5 can be achieved at the peripheral position of the insulating substrate 6. This coupling method greatly reduces the adaptation difficulty during the coupling process of the fiber 8 and the optical waveguide 5, facilitating active alignment using a fiber 8 coupling platform during fiber 8 coupling, and significantly improving the actual coupling efficiency.

[0032] Furthermore, since the optical waveguide 5 is laterally exposed around the periphery of the insulating substrate 6, the adhesives used during the installation of the photonic integrated chip 3 will not easily contaminate the optical waveguide 5. This is because adhesives are typically applied at the connection points between the chip and the substrate, while the optical waveguide 5 is located on the periphery, separated from the conventional bonding area. This avoids the problem of adhesive contamination affecting optical signal transmission, thus ensuring the stability and reliability of signal transmission.

[0033] Furthermore, this arrangement of the optical waveguide 5 allows for more flexible coupling between the fiber array assembly 7 and the optical waveguide 5. In practical applications, different devices and scenarios may have different requirements for the angle and position of optical coupling. Coupling around the insulating substrate 6 allows for adjustment of the position and angle of the fiber array assembly 7 according to specific needs, achieving optimal optical coupling. Simultaneously, this flexible coupling method reduces the precision requirements for the installation of the fiber array assembly 7, minimizing errors and difficulties during installation, and improving the overall production efficiency and yield of the packaging structure.

[0034] From a long-term usage perspective, the design of the optical waveguide 5 being laterally exposed on the periphery of the insulating substrate 6 facilitates the maintenance and upgrading of the packaging structure. When inspection, repair, or replacement of the optical waveguide 5 or the fiber array assembly 7 is required, the operation is much easier, eliminating the need for complex disassembly and installation of the entire substrate end plane as in traditional structures, thus reducing maintenance and time costs. Furthermore, with continuous technological advancements, if the packaging structure needs to be upgraded to meet higher-performance optical signal transmission requirements, this design is easier to improve and optimize, offering better scalability and adaptability. The insulating substrate 6 can be made of ceramic or silicon; in this embodiment, it is preferably made of glass. Glass substrates, as an emerging packaging material, have low dielectric constant and low loss tangent, resulting in low signal loss and superior RF performance in high-frequency applications. Glass has an adjustable coefficient of thermal expansion, high mechanical strength, and strong anti-warping ability; its surface flatness is superior to that of organic substrates. Through-glass via (TGV) technology is achieved through laser-induced and wet etching processes, which are simple and efficient to fabricate, and the via depth can reach 200μm to 400μm, allowing for thicker glass substrates and further enhancing dimensional stability and anti-warping ability.

[0035] Furthermore, the photonic integrated chip 3 can be made of various materials, such as silicon or lithium niobate, to achieve the performance goals of high bandwidth and low loss.

[0036] In the actual structure, the insulating substrate 6 can be entirely located on the side of the photonic integrated chip 3 facing the circuit board 11; the optical waveguide 5 directly exposes the periphery of the insulating substrate 6 laterally.

[0037] Since the insulating substrate 6 is entirely located on the side of the photonic integrated chip 3 facing the circuit board 11, the overall space occupied by the structure can be effectively reduced, making it more suitable for use in miniaturized devices. Furthermore, when the package structure is applied to complex system environments, the design of the optical waveguide 5 being directly exposed laterally on the periphery of the insulating substrate 6 allows for better integration with other optical components or systems. The transmission direction and angle of the optical signal can be adjusted more flexibly to meet the specific needs of different systems, improving the compatibility and adaptability of the entire system. Moreover, this layout enhances the reliability and stability of the package structure when facing different operating conditions and environmental changes, ensuring stable transmission of the optical signal. For example, in some embodiments, such as Figure 1 As shown, the insulating substrate 6 and the photonic integrated chip 3 are spaced apart; the optical waveguide 5 protrudes laterally from the periphery of the insulating substrate 6; the fiber array assembly 7 is supported on the circuit board 11 by a support member. Specifically, the support member is configured as a fiber array support 16.

[0038] like Figure 2 As shown, the portion of the photonic integrated chip 3 located inside the end of the insulating substrate 6 is a specific conductive mounting structure. Its end face and the end face of the insulating substrate 6 are fixed with a corresponding bottom filler 13, allowing the optical waveguide 5 of the photonic chip to be spaced apart from the insulating substrate 6. Furthermore, one end of the optical waveguide 5 protrudes from the outside of the insulating substrate 6. This structure not only allows for rapid alignment of the fiber array assembly 7 and the optical waveguide 5 using high-precision patch coupling equipment (alignment accuracy ≤ 0.5 micrometers), achieving efficient passive coupling and significantly improving coupling efficiency, but also ensures that, in complex working environments, the fiber array assembly 7 is firmly supported on the circuit board 11 by a support member, effectively resisting vibration and impact, and guaranteeing the stability and reliability of optical signal transmission.

[0039] In another embodiment, such as Figure 2As shown, the insulating substrate 6 has a first mounting groove on the side facing away from the circuit board 11. The photonic integrated chip 3 is partially recessed in the first mounting groove. A first filling area is formed between the first mounting groove and the end of the photonic integrated chip 3 to fill the bottom filler adhesive 13. The optical waveguide 5 is at least partially attached to the insulating substrate 6. The fiber array assembly 7 is supported on the insulating substrate 6. The optical waveguide 5 and the fiber array assembly 7 are located on the insulating substrate 6 for optical coupling.

[0040] This structural design further optimizes the spatial layout of the chip packaging module, making the overall structure more compact. Since the photonic integrated chip 3 is partially recessed within the first mounting groove, the optical waveguide 5 can fit tightly against the insulating substrate 6. For the other end of the photonic integrated chip 3, located in the first mounting groove, during installation, the bottom filler 13 can be contained within the first mounting groove, filling the space between the bottom of the groove and the photonic integrated chip 3. This prevents the bottom filler 13 from contaminating the optical waveguide 5, reduces interference from external factors on the optical waveguide 5, and improves the stability of optical signal transmission.

[0041] Meanwhile, the optical waveguide 5 and the optical fiber array assembly 7 are coupled and optically coupled at the location on the insulating substrate 6. The insulating substrate 6 supports the optical waveguide 5, making the optical coupling process more stable. The insulating substrate 6 can provide good physical support and electrical insulation for the optical coupling location, reducing optical signal distortion caused by external electric and magnetic field interference.

[0042] In practical applications, this compact and stable structural design makes it easier to integrate the chip packaging module into various devices, such as communication equipment and optical sensors. It not only improves the overall performance of the device but also reduces its size and power consumption, providing strong support for miniaturization and high performance. At the same time, this structure enhances the adaptability and reliability of the chip packaging module in complex environments, better meeting the application needs of different fields. In yet another embodiment, such as Figure 3As shown, the insulating substrate 6 has a second mounting groove on the side facing away from the circuit board 11, and the bottom wall of the second mounting groove also has a third mounting groove. The photonic integrated chip 3 is partially recessed in the third mounting groove. A second filling area is formed between the third mounting groove and the end of the photonic integrated chip 3 for filling the bottom filler 13. The sidewall of the second mounting groove laterally shields the optical waveguide 5. A photonic lead 17 is provided in the sidewall of the second mounting groove. One end of the photonic lead 17 is optically coupled to the optical waveguide 5, and the other end is laterally led out of the insulating substrate 6, so that the optical waveguide 5 is indirectly and laterally exposed to the periphery of the insulating substrate 6 through the photonic lead 17. The fiber array assembly 7 is supported on the circuit board 11 by a support member.

[0043] The photonic leads 17 are formed on the insulating substrate 6 by laser direct writing. The photonic leads 17, fabricated on the insulating substrate 6 by laser direct writing or other methods, enable extended coupling between the optical waveguide 5 of the photonic integrated chip 3 and the optical fiber 8 array, thereby converting the high-density optical interface into a standard-pitch optical fiber 8 interface.

[0044] This extended coupling method has significant advantages. First, it effectively solves the problem of mismatch between high-density optical interfaces and standard-pitch fiber optic interfaces in practical applications, enabling smoother connection and communication between optical components of different specifications. Second, the photonic integrated chip 3 and optical waveguide 5 can be extended and coupled to multi-row fiber arrays through photonic leads 17, achieving a doubling of optical communication capacity. Third, the photonic leads 17 are fabricated using advanced technologies such as laser direct writing, ensuring the high efficiency and stability of photonic transmission. Laser direct writing technology can precisely control the path and parameters of the photonic leads 17, reducing scattering and loss of optical signals during transmission and improving the transmission quality of optical signals.

[0045] During installation, the design of the photonic integrated chip 3 partially submerged within the third mounting slot not only secures the photonic integrated chip 3 within the third mounting slot using a filler material, namely the bottom filler adhesive 13, thus preventing contamination of the optical waveguide 5, but also utilizes the sidewalls of the second mounting slot to protect the optical waveguide 5 from damage caused by external physical impacts. Simultaneously, the photonic leads within the second mounting slot optically couple the optical waveguide 5 to the external optical fiber 8, enabling efficient transmission of optical signals between the chip and external devices.

[0046] Furthermore, this structural design offers excellent scalability and compatibility. As technology advances and application demands evolve, different optical performance requirements can be met by adjusting the parameters and layout of the photonic leads, or by replacing the fiber array components 7 with different specifications. Moreover, this structure can be well integrated with existing circuit boards 11 and other electronic components, providing greater flexibility for the design and optimization of the entire system.

[0047] In practical applications, the advantages of this chip packaging module structure 100 will be more fully realized. For example, in the field of high-speed communication, it can achieve high-speed and stable optical signal transmission, improving the bandwidth and reliability of the communication system; in the field of optical sensing, it can combine the high sensitivity of the photonic integrated chip 3 with the long-distance transmission advantage of the optical fiber 8 to achieve more accurate and wider sensing applications. The main structural features of the above embodiments focus on the specific location layout of the photonic integrated chip 3. In this layout, the optical waveguide 5 of the photonic integrated chip 3 is directly or indirectly disposed on the outer peripheral wall of the insulating substrate 6. This layout, on the one hand, mounts the photonic integrated chip 3 to the inner side of the insulating substrate 6, thereby isolating the bottom filler 13 from the optical waveguide 5, effectively preventing contamination of the optical waveguide 5 and thus avoiding interference with optical signal transmission. Furthermore, the insulating substrate 6 supports the optical waveguide 5, improving its stability during coupling. In practical applications, this layout also allows for better integration with other related components. For example, when connecting to an external optical fiber 8, the optical waveguide 5 on the outer peripheral wall can more easily dock with the optical fiber 8, reducing losses and errors during the connection process and further improving the efficiency of optical signal transmission. Simultaneously, this layout also provides more possibilities for integrating the chip with other optical or electronic devices, contributing to the construction of more complex and efficient optical systems. In some embodiments, such as Figure 3 As shown, the chip packaging module structure 100 further includes an electronic integrated chip 10 and a host dedicated integrated circuit chip 15. The photonic integrated chip 3 and the electronic integrated chip 10 are disposed at the same end in the thickness direction of the insulating substrate 6, or are disposed at opposite ends in the thickness direction of the insulating substrate 6, and the photonic integrated chip 3 and the electronic integrated chip 10 are connected to each other. The host dedicated integrated circuit chip 15 is disposed on the insulating substrate 6 and is connected to the electronic integrated chip 10.

[0048] In the chip packaging module structure 100, the photonic integrated chip 3 needs to be used in conjunction with the electronic integrated chip 10 and the host dedicated integrated circuit chip 15. In this structure, the host dedicated integrated circuit chip 15 performs core tasks, such as network data packet exchange, artificial intelligence calculations, or general computing. It generates the raw digital bit stream to be sent and processes the received data; it is the "brain" and "commander" of the system. The electronic integrated chip 10 provides the precise voltage / current required for the photonic integrated chip 3 to operate (e.g., driving lasers, modulators) and processes the weak electrical signals generated by the photonic integrated chip 3 (e.g., amplifying detector signals), while also performing initial analog-to-digital / digital-to-analog conversion; it is the "translator" and "signal officer" of photoelectric conversion. The photonic integrated chip 3 can convert electrical signals into optical signals (emission), or manipulate them in the optical domain (modulation, beam splitting), and then convert the optical signals back into electrical signals (reception); it is the operator of the optical world.

[0049] In terms of specific structural settings, the aforementioned chip structure will be mounted on the insulating substrate 6. Through the specific arrangement of the photonic chip and the electronic chip on the insulating substrate 6, the entire chip packaging module structure 100 can possess corresponding characteristics, thereby meeting different practical application requirements.

[0050] Specifically, in some embodiments, the insulating substrate 6 is provided with a plurality of through holes 9 for conducting through its two ends in the thickness direction; when the photonic integrated chip 3 and the electronic integrated chip 10 are respectively disposed at the two ends in the thickness direction of the insulating substrate 6, the photonic integrated chip 3 and the electronic integrated chip 10 are vertically interconnected through the plurality of through holes.

[0051] In the specific structure, the host-specific integrated circuit chip 15 is located at the end of the insulating substrate 6 away from the circuit board 11, and the photonic integrated chip 3 and the host-specific integrated circuit chip 15 are located on the same side of the insulating substrate 6 in the thickness direction. The electronic integrated chip 10 is located on the other side of the insulating substrate 6 in the thickness direction. The photonic integrated chip 3 and the electronic integrated chip 10 are vertically interconnected through the through-hole. Specifically, a corresponding conductive structure is provided in the through-hole to realize the communication connection between the two chip structures.

[0052] It should be noted that the dual-sided mounting method can further increase the mounting density of the photonic integrated chips 3 on the insulating substrate 6. By increasing the mounting density of the photonic integrated chips 3, the performance of the entire chip packaging module structure 100 can be effectively improved. More photonic integrated chips 3 mean that more complex optical signals can be processed, achieving higher data transmission rates and lower latency. At the same time, the dual-sided mounting method makes the layout between the chips more compact and reasonable, reducing the path length of signal transmission and further optimizing the quality of signal transmission. In addition, this mounting method can also improve the integration of the chip packaging module structure 100, reduce its overall size, and make it more suitable for applications with high space requirements, such as portable electronic devices. Moreover, with the increase in mounting density, costs can also be reduced to a certain extent, because more functions can be implemented in the same space, improving resource utilization efficiency. In addition, this mounting method is also beneficial for heat dissipation design. The dual-sided layout makes it easier to set up heat dissipation channels to dissipate the heat generated by the chips in a timely manner, ensuring that the chips operate in a stable temperature environment, thereby extending the lifespan of the chips and ensuring their operational stability.

[0053] In this embodiment, the circuit board 11 is disposed on one end of the insulating substrate 6 and mounted on the electronic integrated chip 10. In some embodiments, the circuit board 11 is disposed on the side of the electronic integrated chip 10 away from the insulating substrate 6; a gap space is formed between the circuit board 11 and the insulating substrate 6; the circuit board 11 has a recessed portion, and the electronic integrated chip 10 is at least partially disposed within the recessed portion, so that the other end of the electronic integrated chip 10 is located within the gap space.

[0054] Specifically, wiring layers 4 are provided at both ends of the insulating substrate 6 in the thickness direction. The electronic integrated chip 10 and the host dedicated integrated circuit chip 15 are both connected to the wiring layers 4 by flip-chip bonding, such as... Figure 3 As shown, copper pillar solder joints 14 are formed between the two corresponding welding structures. After welding, the area of ​​the copper pillar solder joint needs to be filled with underfill adhesive 13 for reinforcement and fixation. Similarly, the photonic integrated chip 3 is flip-chip bonded to the other side of the insulating substrate 6 and connected to the wiring layer 4 disposed on the other side of the insulating substrate 6. The flip-chip bonding process includes reflow soldering, thermoforming bonding, or laser-assisted bonding. After bonding, local underfill (i.e., filling with underfill adhesive 13) is performed. The underfill adhesive 13 is confined within the groove structure of the insulating substrate 6 to avoid contaminating the optical waveguide 5 of the photonic integrated chip 3. The circuit board 11 is also connected to the insulating substrate 6 by soldering, as shown. Figure 3As shown, a plurality of solder balls 12 are formed between the circuit board 11 and the insulating substrate 6. These solder balls 12 provide support between the insulating substrate 6 and the circuit board 11, forming the spacing space. This spacing space ensures the mounting space for the electronic integrated chip 10 between the insulating substrate 6 and the circuit board 11, thereby avoiding mechanical interference and ensuring the integrity of the package structure. Furthermore, it should be noted that the aforementioned dual-sided chip configuration simplifies the process route, allowing the photonic integrated chip 3 and the electronic integrated chip 10 to be flip-chip connected to opposite sides of the glass substrate, avoiding the complex through-silicon via (TSV) manufacturing process resulting from stacking the photonic integrated chip 3 and the electronic integrated chip 10.

[0055] The aforementioned arrangement of the photonic integrated chip 3 and the electronic integrated chip 10 at opposite ends of the insulating substrate 6 along its thickness direction, through structural design and process integration, achieves high-density, high-reliability, and low-loss optoelectronic co-packaging of glass substrates. This approach is suitable for next-generation data centers and high-performance computing optical interconnect systems and has promising application prospects.

[0056] In another embodiment, such as Figure 3 and Figure 4 As shown, both the photonic integrated chip 3 and the electronic integrated chip 10 are disposed at the end of the insulating substrate 6 away from the circuit board 11; multiple photonic integrated chips 3 and multiple electronic integrated chips 10 are provided, and one photonic integrated chip 3 is connected to multiple electronic integrated chips 10, so that multiple photonic engines are formed on one end of the insulating substrate 6, and multiple waveguides in the multiple photonic engines are disposed at the peripheral position of the insulating substrate 6.

[0057] Specifically, the photonic engine includes an electronic integrated chip 10 comprising a driver chip, a transimpedance amplifier chip, and a microcontroller chip (MCU) 18. The MCU 18, combined with the microcontroller chip 18, forms multiple photonic engine functional areas on the end face of the insulating substrate 6 away from the circuit board 11. Typically, sixteen photonic engines are arranged around the host application-specific integrated circuit chip 15. Each photonic engine includes an electronic integrated chip 10 and a photonic integrated chip 3. Increasing the number of photonic engines linearly increases the communication bandwidth. This layout utilizes the high integration of the insulating substrate 6 to achieve a compact photonic engine array, meeting high-bandwidth communication requirements. Furthermore, this same-side arrangement can reduce the overall thickness of the entire package structure to a certain extent, contributing to a thinner and lighter package.

[0058] In some embodiments, such as Figure 3As shown, one of the photonic integrated chip 3, the electronic integrated chip 10, and the host dedicated integrated circuit chip 15 is set as the first chip. The chip packaging module structure 100 also includes a heat sink assembly, which is at least connected to the first chip to cool the first chip.

[0059] Because chips generate a large amount of heat during operation, failure to dissipate heat in a timely manner will affect their performance and lifespan. The heat sink assembly can be directly attached to the surface of the first chip, transferring the heat generated by the chip through thermal conduction. The heat sink assembly can be made of highly thermally conductive materials, such as copper or aluminum, which have excellent thermal conductivity and can quickly dissipate heat to the surrounding environment. To achieve efficient heat dissipation, liquid cooling can be used. A thermal interface material 2 is placed between the liquid cooling heat sink 1 and the corresponding chip structure for efficient heat conduction, thereby achieving efficient cooling of the chip structure. Furthermore, the installation position and method of the heat sink assembly also need to be rationally designed to ensure that it can effectively cool the first chip and guarantee the stable operation of the chip packaging module structure 100. Preferably, the operating temperature of the chip structure needs to be controlled below 70°C.

[0060] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A chip packaging module structure, characterized in that, include: Circuit board; An insulating substrate is disposed on one side of the circuit board; A photonic integrated chip is disposed on the insulating substrate, and the photonic integrated chip has an optical waveguide; as well as, A fiber optic array assembly, supported on the substrate or the circuit board, is movable relative to the insulating substrate to connect to the connection port of the optical waveguide for optical coupling. The connection port of the optical waveguide is directly or indirectly exposed to the periphery of the insulating substrate.

2. The chip packaging module structure as described in claim 1, characterized in that, The insulating substrate is entirely located on the side of the photonic integrated chip facing the circuit board; The optical waveguide is directly exposed laterally to the periphery of the insulating substrate.

3. The chip packaging module structure as described in claim 2, characterized in that, The insulating substrate and the photonic integrated chip are spaced apart. The optical waveguide is laterally protruding from the periphery of the insulating substrate; The fiber optic array assembly is supported on the circuit board by a support member.

4. The chip packaging module structure as described in claim 2, characterized in that, The insulating substrate has a first mounting groove on the side facing away from the circuit board. The photonic integrated chip is partially disposed in the first mounting groove. A first filling area is formed between the first mounting groove and the end of the photonic integrated chip for filling the bottom filler. The optical waveguide is at least partially attached to the insulating substrate. The fiber optic array assembly is supported on the insulating substrate; The optical waveguide and the optical fiber array assembly are optically coupled at a location on the insulating substrate.

5. The chip packaging module structure as described in claim 1, characterized in that, The insulating substrate has a second mounting groove on the side facing away from the circuit board. The bottom wall of the second mounting groove also has a third mounting groove. The photonic integrated chip is partially embedded in the third mounting groove. A second filling area is formed between the third mounting groove and the end of the photonic integrated chip for filling with bottom filler adhesive. The sidewall of the second mounting groove laterally shields the optical waveguide. A photonic lead is provided in the sidewall of the second mounting groove. One end of the photonic lead is optically coupled to the optical waveguide, and the other end is laterally led out of the insulating substrate, so that the optical waveguide indirectly exposes the periphery of the insulating substrate laterally through the photonic lead. The fiber optic array assembly is supported on the circuit board by a support member.

6. The chip packaging module structure as described in claim 1, characterized in that, The chip packaging module structure further includes an electronic integrated chip and a host-specific integrated circuit chip. The photonic integrated chip and the electronic integrated chip are disposed at the same end in the thickness direction of the insulating substrate, or separately at opposite ends in the thickness direction of the insulating substrate, and the photonic integrated chip and the electronic integrated chip are connected. The host-specific integrated circuit chip is disposed on the insulating substrate and connected to the electronic integrated chip; and / or, The insulating substrate is configured as a glass insulating substrate.

7. The chip packaging module structure as described in claim 6, characterized in that, The insulating substrate has multiple through holes for connecting its two ends in the thickness direction; When the photonic integrated chip and the electronic integrated chip are disposed at opposite ends in the thickness direction of the insulating substrate, the photonic integrated chip and the electronic integrated chip are vertically interconnected through a plurality of vias.

8. The chip packaging module structure as described in claim 6, characterized in that, The circuit board is located on the side of the electronic integrated chip away from the insulating substrate; A gap is formed between the circuit board and the insulating substrate; The circuit board has a recessed section, and the electronic integrated chip is at least partially disposed in the recessed section, so that the other end of the electronic integrated chip is located in the gap space.

9. The chip packaging module structure as described in claim 6, characterized in that, Both the photonic integrated chip and the electronic integrated chip are located at the end of the insulating substrate away from the circuit board. Multiple photonic integrated chips and multiple electronic integrated chips are provided, and one photonic integrated chip is connected to multiple electronic integrated chips to form multiple photonic engines on one end of the insulating substrate, and multiple waveguides in the multiple photonic engines are provided at the peripheral position of the insulating substrate.

10. The chip packaging module structure as described in claim 6, wherein the host application-specific integrated circuit chip is disposed at the end of the insulating substrate away from the circuit board; and / or, One of the photonic integrated chip, the electronic integrated chip, and the host dedicated integrated circuit chip is set as the first chip. The chip packaging module structure also includes a heat sink assembly, which is at least connected to the first chip to cool the first chip.

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