Top gate array substrate of electronic paper, driving method and electronic paper

Abstract

The invention discloses a top gate array substrate of electronic paper, a driving method and the electronic paper. The substrate comprises an interlayer insulating layer, a gate metal layer, a gate insulating layer, a source and drain electrode layer and a polycrystalline silicon layer, the gate metal layer is manufactured in the interlayer insulating layer, and the gate insulating layer is manufactured between the gate metal layer and the polycrystalline silicon layer; the source and drain electrode layer is manufactured in the gate insulation layer and comprises a source electrode metal wire and a drain electrode metal wire; the source electrode metal wire and the drain electrode metal wire are respectively connected with the polycrystalline silicon layer; a shading insulating layer and a shading layer are further included; the shading insulating layer is manufactured between the polycrystalline silicon layer and the shading layer; the light shielding layer is made of a conductive material and is used for forming uniform potential distribution in the layer during electrification so as to shield and absorb ambient light. The shading effect of the electronic paper array substrate is enhanced, and the problems of TFT leakage current, threshold voltage drift, reduction of pixel voltage maintaining capability, picture ghosting caused by photon-generated carriers, reduction of contrast ratio and the like are avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic paper, and in particular to a top gate array substrate of electronic paper, a driving method and electronic paper. BACKGROUND

[0002] Electronic paper (E-paper) has a wide range of applications in consumer electronics, intelligent transportation and other fields due to its low power consumption, eye protection, flexibility, visibility in sunlight and other characteristics, especially in outdoor environments.

[0003] However, in such an outdoor strong light direct environment, especially for outdoor electronic paper (such as electronic station boards) that requires high reliability, outdoor strong light can easily penetrate the glass / PI substrate and irradiate the IGZO active layer. The photo-generated carriers excited by strong light can increase the TFT leakage current, cause threshold voltage drift and pixel voltage maintenance capability to decrease, and the photo-generated carriers can also cause the appearance of problems such as image sticking and reduced contrast, which can affect the reliability of the electronic paper. SUMMARY

[0004] In the prior art, the shading effect of the electronic paper array substrate is poor, which can cause problems such as TFT leakage current, threshold voltage drift, pixel voltage maintenance capability to decrease, and the appearance of problems such as image sticking and reduced contrast.

[0005] To solve the above problems, a top gate array substrate of electronic paper, a driving method and electronic paper are provided. A conductive shading layer is arranged in the electronic paper array substrate to form a uniform potential distribution in the layer when powered on, so as to shield and absorb ambient light, thereby enhancing the shading effect of the electronic paper array substrate. When the gate metal layer is powered on, the polarity of the input electrical signal of the gate metal layer is obtained, and an electrical signal with opposite polarity is input to the shading layer, thereby avoiding problems such as TFT leakage current, threshold voltage drift, pixel voltage maintenance capability to decrease, and the appearance of problems such as image sticking and reduced contrast.

[0006] In a first aspect, a top gate array substrate of electronic paper includes: an interlayer insulating layer, a gate metal layer, a gate insulating layer, a source-drain layer and a polysilicon layer; The gate metal layer is made in the interlayer insulating layer, and the gate insulating layer is made between the gate metal layer and the polysilicon layer; The source-drain layer is made in the gate insulating layer and includes a source metal line and a drain metal line; The source metal line and the drain metal line are respectively connected to the polysilicon layer; Further including a shading insulating layer and a shading layer; The shading insulating layer is made between the polysilicon layer and the shading layer. The light-shielding layer is made of conductive material, which is used to form a uniform potential distribution in the layer when powered on, so as to shield and absorb ambient light.

[0007] In combination with the top-gate array substrate of the electronic paper of the first aspect of the present application, in a first possible implementation, the array substrate further comprises: a buffer layer and a substrate substrate; The buffer layer is made between the light-shielding layer and the substrate substrate.

[0008] In combination with the first possible implementation of the first aspect of the present application, in a second possible implementation, the light-shielding layer is made of conductive material, and when the gate metal layer is powered on, an electric signal opposite in polarity is input to the light-shielding layer to improve the response speed of the transistor.

[0009] In combination with the second possible implementation of the first aspect of the present application, in a third possible implementation, the light-shielding layer is made of conductive material, and when the gate metal layer is powered on, if the gate metal layer is a high-level signal, a low-level signal is input to the light-shielding layer to quickly turn on the transistor.

[0010] In combination with the second possible implementation of the first aspect of the present application, in a fourth possible implementation, the light-shielding layer is made of conductive material, and when the gate metal layer is powered on, if the gate metal layer is a low-level signal, a high-level signal is input to the light-shielding layer to quickly turn off the transistor.

[0011] In combination with the top-gate array substrate of the electronic paper of the first aspect of the present application, in a fifth possible implementation, the light-shielding layer is made of Mo material.

[0012] The second aspect is a driving method of a top-gate array substrate, which adopts the top-gate array substrate of the electronic paper of the first aspect, and comprises: Step 10: powering on the light-shielding layer of the top-gate array substrate to form a uniform potential distribution in the light-shielding layer, so as to shield and absorb ambient light; Step 20: when the gate metal layer is powered on, obtaining the polarity of the electric signal input to the gate metal layer, and inputting an electric signal opposite in polarity to the light-shielding layer to improve the response speed of the transistor.

[0013] In combination with the driving method of the top-gate array substrate of the second aspect of the present application, in a first possible implementation, the step 20 comprises: Step 21: detecting the level signal of the gate metal layer to obtain the level signal of the gate metal layer; Step 22: if the gate metal layer is a high-level electric signal, inputting a low-level electric signal to the light-shielding layer to quickly turn on the transistor.

[0014] In combination with the driving method of the top-gate array substrate of the second aspect of the present application, in a second possible implementation, the step 20 comprises: Step 23, detecting the level signal of the gate metal layer to obtain the level signal of the gate metal layer; Step 24, if the gate metal layer is a low-level electrical signal, inputting a high-level electrical signal to the light shielding layer to quickly turn on the transistor.

[0015] In a third aspect, an electronic paper adopts the array substrate structure of the first aspect and is driven by the driving method of the second aspect.

[0016] The top-gate array substrate of the electronic paper, the driving method of the electronic paper, and the electronic paper of the present application have the following advantages. By arranging the conductive light shielding layer in the array substrate of the electronic paper, a uniform potential distribution is formed in the layer when power is applied, so as to shield and absorb ambient light, thereby enhancing the light shielding effect of the array substrate of the electronic paper. By obtaining the polarity of the electrical signal input to the gate metal layer when power is applied to the gate metal layer, and inputting an electrical signal of opposite polarity to the light shielding layer, the problems of TFT leakage current, threshold voltage drift, pixel voltage maintenance capability reduction, light-induced carrier, and picture residual image and contrast reduction are avoided. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is a schematic diagram of an IGZO top-gate structure of an existing electronic paper; Figure 2 is a schematic diagram of an IGZO top-gate structure of the present application; Figure 3 is a schematic diagram of a film layer structure of the top-gate array substrate of the electronic paper of the present application; Figure 4 is a schematic diagram of one embodiment of the driving method of the top-gate array substrate of the present application; Figure 5 is Figure 3 is a schematic diagram of one specific embodiment of step 200 in the method; Figure 6 is Figure 3 is a schematic diagram of another specific embodiment of step 200 in the method. DETAILED DESCRIPTION

[0019] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In the existing technology, the light-shielding effect of the electronic paper array substrate is poor, which leads to TFT leakage current, threshold voltage drift, and decreased pixel voltage maintenance capability. Photogenerated carriers can also cause problems such as image ghosting and reduced contrast.

[0025] To address the above issues, a top grid array substrate for electronic paper, a driving method, and electronic paper are proposed.

[0026] Firstly, a top grid array substrate for electronic paper, such as Figure 2 and Figure 3 , Figure 2This is a schematic diagram of the existing IGZO top gate structure of the present invention. Figure 3 This is a schematic diagram of the film layer structure of the top grid array substrate of the electronic paper of the present invention, including: The system comprises an interlayer insulating layer 900, a gate metal layer 700, a gate insulating layer 600, a source / drain layer, and a polysilicon layer 500. The gate metal layer 700 is incorporated into the interlayer insulating layer 900, and the gate insulating layer 600 is formed between the gate metal layer 700 and the polysilicon layer 500. The source / drain layer is formed within the gate insulating layer 600 and includes a source metal line 810 and a drain metal line 820. The source metal line 810 and the drain metal line 820 are respectively connected to the polysilicon layer 500. The system also includes a light-shielding insulating layer 400 and a light-shielding layer 300. The light-shielding insulating layer 400 is formed between the polysilicon layer 500 and the light-shielding layer 300. The light-shielding layer 300 is a conductive material used to form a uniform potential distribution within the layer when energized, thereby blocking and absorbing ambient light.

[0027] In this embodiment, the light-shielding layer 300, after being energized, can form a more uniform potential distribution, enhancing its ability to block and absorb light, resulting in stronger shielding capabilities and further reducing photo-generated leakage current. Furthermore, when the light-shielding layer 300 and the gate metal layer 700 are energized synchronously, they can form a dual-gate structure, further enhancing the electric field control capability of the IGZO channel, further reducing electrical stress leakage current, and simultaneously improving the response speed of the TFT transistor. After being energized, it can also compensate for the voltage threshold (Vth value) of the IGZO, optimizing Vth stability: contributing to image uniformity and long-term stability.

[0028] In one possible implementation, the array substrate further includes a buffer layer 200 and a substrate 100; the buffer layer 200 is formed between the light-shielding layer 300 and the substrate 100.

[0029] In one possible implementation, the light-shielding layer 300 is made of a conductive material. When the gate metal layer 700 is energized, an electrical signal with the opposite polarity is supplied to the light-shielding layer 300 to improve the transistor response speed.

[0030] In this embodiment, the channel electric field is controlled by utilizing the principle of electron repulsion and attraction between like charges, thereby improving the transistor response speed and reducing leakage current.

[0031] In one possible implementation, the light-shielding layer 300 is a conductive material. When the gate metal layer 700 is energized, if the gate metal layer 700 is a high-level (VGH) electrical signal, a low-level (VGL) electrical signal is supplied to the light-shielding layer 300 to quickly turn on the transistor.

[0032] In this embodiment, when the gate metal layer 700 receives a VGH signal, especially when Vgs (source-drain voltage) > Vth (threshold voltage), all channel electrons are in the front channel due to the principle of opposite attraction, and the TFT transistor gradually turns on. At this time, a VGL signal can be given to the light-shielding layer 300 (LS layer). By utilizing the principle of like repulsion, all electrons are in the front channel, and the on-state current increases instantaneously.

[0033] In one possible implementation, the light-shielding layer 300 is a conductive material. When the gate metal layer 700 is energized, if the gate metal layer 700 is a low-level VGL electrical signal, a high-level VGH electrical signal is supplied to the light-shielding layer 300 to quickly turn off the transistor.

[0034] In this embodiment, when the gate metal layer 700 receives a VGL signal, all the channel electrons are in the back channel due to the principle of like charges repelling each other, and the TFT gradually turns off. At this time, a VGH signal can be input to the light-shielding layer 300 (LS layer). By utilizing the principle of opposite charges attracting each other, all electrons are in the back channel, and the off-state current decreases instantaneously.

[0035] Preferably, the light-shielding layer 300 is made of Mo material.

[0036] In this embodiment, by providing a conductive light-shielding layer 300 in the electronic paper array substrate, a uniform potential distribution is formed within the layer when energized, thereby blocking and absorbing ambient light and enhancing the light-shielding effect of the electronic paper array substrate. By obtaining the polarity of the electrical signal passed through the gate metal layer 700 when energized, and passing an electrical signal of opposite polarity to the light-shielding layer 300, problems such as TFT leakage current, threshold voltage drift, and decreased pixel voltage maintenance capability are avoided. Photogenerated carriers can also cause problems such as image retention and reduced contrast.

[0037] Secondly, a driving method for a top gate array substrate, employing a top gate array substrate structure of a first-party electronic paper top gate array substrate, such as... Figure 4 , Figure 4 This is a schematic diagram of an embodiment of the driving method for the top gate array substrate of the present invention; including: Step 10: Power on the light-shielding layer 300 of the top gate array substrate to form a uniform potential distribution within the light-shielding layer 300, so as to block and absorb ambient light; Step 20: When the gate metal layer 700 is powered on, obtain the polarity of the electrical signal passed into the gate metal layer 700, and pass an electrical signal of opposite polarity into the light-shielding layer 300 to improve the transistor response speed.

[0038] In one possible implementation, such as Figure 5 , Figure 5 yes Figure 3A schematic diagram of a specific embodiment of step 200; step 20 includes: Step 21: Detect the level signal of the gate metal layer 700 to obtain the level signal of the gate metal layer; Step 22: If the gate metal layer 700 is a high-level electrical signal, pass a low-level electrical signal to the light-shielding layer 300 to quickly turn on the transistor.

[0039] In one possible implementation, such as Figure 6 , Figure 6 yes Figure 3 Another specific embodiment of step 200 is illustrated in the diagram. Step 20 includes: Step 23: Detect the level signal of the gate metal layer 700 to obtain the level signal of the gate metal layer; Step 24: If the gate metal layer 700 is a low level electrical signal, pass a high level electrical signal to the light-shielding layer 300 to quickly turn on the transistor.

[0040] Thirdly, an electronic paper employs the array substrate structure of the first aspect and is driven using the driving method of the second aspect.

[0041] The electronic paper top grid array substrate, driving method, and electronic paper described in this invention enhance the light-shielding effect of the electronic paper array substrate by setting a conductive light-shielding layer 300 in the electronic paper array substrate. When energized, a uniform potential distribution is formed within the layer to block and absorb ambient light. By obtaining the polarity of the electrical signal passed through the gate metal layer 700 when energized, and passing an electrical signal of opposite polarity to the light-shielding layer 300, problems such as TFT leakage current, threshold voltage drift, and decreased pixel voltage maintenance capability are avoided. Photogenerated carriers can also cause problems such as image retention and reduced contrast.

[0042] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A top grid array substrate for electronic paper, characterized in that, include: Interlayer insulating layer, gate metal layer, gate insulating layer, source / drain layer, polysilicon layer; In the fabrication of the interlayer insulating layer using the gate metal layer, the gate insulating layer is formed between the gate metal layer and the polysilicon layer; The source and drain layers are fabricated in the gate insulating layer and include source metal lines and drain metal lines; The source metal line and the drain metal line are respectively connected to the polysilicon layer; This also includes a light-shielding insulating layer and a light-shielding layer; The light-shielding insulating layer is formed between the polycrystalline silicon layer and the light-shielding layer; The light-shielding layer is made of a conductive material and is used to form a uniform potential distribution within the layer when energized, so as to block and absorb ambient light.

2. The top grid array substrate of electronic paper according to claim 1, characterized in that, The array substrate further includes: Buffer layer and substrate; The buffer layer is formed between the light-shielding layer and the substrate.

3. The top grid array substrate of electronic paper according to claim 2, characterized in that, The light-shielding layer is made of a conductive material. When the gate metal layer is energized, an electrical signal with opposite polarity is passed to the light-shielding layer to improve the transistor response speed.

4. The top grid array substrate of electronic paper according to claim 3, characterized in that, The light-shielding layer is made of a conductive material. When the gate metal layer is energized, if the gate metal layer is at a high level, a low level signal is supplied to the light-shielding layer to quickly turn on the transistor.

5. The top grid array substrate of electronic paper according to claim 4, characterized in that, The light-shielding layer is made of a conductive material. When the gate metal layer is energized, if the gate metal layer is at a low level, a high level signal is supplied to the light-shielding layer to quickly turn off the transistor.

6. The top grid array substrate of electronic paper according to any one of claims 1-5, characterized in that, The light-shielding layer is made of Mo material.

7. A driving method for a top grid array substrate, employing the top grid array substrate of electronic paper according to any one of claims 1-6, comprising: Step 10: Apply current to the light-shielding layer of the top grid array substrate to form a uniform potential distribution within the light-shielding layer, so as to block and absorb ambient light. Step 20: When the gate metal layer is energized, obtain the polarity of the electrical signal passed through the gate metal layer, and pass an electrical signal of opposite polarity to the light-shielding layer to improve the transistor response speed.

8. The driving method for the top gate array substrate according to claim 7, characterized in that, Step 20 includes: Step 21: Detect the level signal of the gate metal layer to obtain the level signal of the gate metal layer; Step 22: If the gate metal layer is a high-level electrical signal, a low-level electrical signal is passed to the light-shielding layer to quickly turn on the transistor.

9. The driving method for the top gate array substrate according to claim 7, characterized in that, Step 20 includes: Step 23: Detect the level signal of the gate metal layer to obtain the level signal of the gate metal layer; Step 24: If the gate metal layer is a low-level electrical signal, a high-level electrical signal is passed to the light-shielding layer to quickly turn on the transistor.

10. An electronic paper, characterized in that, The array substrate structure described in any one of claims 1-6 is used, and the driving method described in claims 7-9 is used for driving.

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