Low-noise reference current generating circuit with gain calibration function

Abstract

The invention discloses a low-noise reference current generating circuit with a gain calibration function. The low-noise reference current generating circuit is suitable for a single-chip high-speed high-precision current-steering DAC (Digital-to-Analog Converter). The circuit comprises an external reference voltage, an external resistor, an operational amplifier, a suspension current mirror, a biasing circuit and a P / N end trimming current mirror array, the suspension current mirror is composed of four groups of NMOS / PMOS transistor pairs with interconnected source electrodes, and the suspension current mirror is connected between a reference current branch and the DAC biasing circuit in series. A closed loop is formed by multiple operational amplifiers and a suspension current mirror, and reference current IREF = VREF / Rset is accurately generated; and after being copied by the suspension current mirror, the bias circuit provides bias for the two trimming arrays respectively, a current difference value forms trimming current ICAL, and the trimming current ICAL is reinjected into an original branch and summed with the IREF to obtain bias current IBIAS. According to the design, an extra current conversion link in a traditional scheme is omitted, the noise level is close to that of a calibration-free circuit, meanwhile, gain errors caused by manufacturing mismatch are accurately compensated, and both calibration precision and low noise are taken into consideration.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a low-noise reference current generation circuit with gain calibration function. Background Technology

[0002] High-speed, high-precision current-driven DAC chips are key components in wireless communication systems, instrumentation, and other electronic systems. They mainly consist of four parts: a current source array, a decoding circuit and latches, a clock generation circuit, and a reference current generation circuit. The reference current generation circuit uses a reference voltage (externally connected or generated by an internal reference source) and an external resistor to generate a reference current, which is then used by a current mirror bias circuit to generate the gate bias voltage required by each device in the DAC main current source array.

[0003] Figure 1 A schematic diagram of a traditional reference current generation circuit is given, taking a current-controlled DAC chip using a PMOS current source as an example. VREF and Rset are the external reference voltage and external resistor of the chip, respectively. The operational amplifiers OTA1, NM0, Rset, and the bias circuit of the DAC main current source array (PM0a, PM1a, PM2a, PM3a) form a closed loop. This loop obtains the reference current IEF = VREF / Rset by controlling the voltage difference across the resistor Rset to be equal to VREF. This IEF is directly used as the bias current IBIAS, which generates the gate bias voltages VBP0 and VBP1 required by PM0b[i] and PM1b[i] in the DAC main current source array via PM0a, PM1a, PM2a, and PM3a.

[0004] The current gain of a DAC is defined as the ratio of its full-scale output current to the reference current IREF. During chip manufacturing, due to device mismatch, deviations in the size ratio and threshold voltage of each PM0b[i] and PM0a will occur, which will cause changes in the current mirror current ratio, thus leading to current gain errors in the DAC. Therefore, for system applications requiring accurate current gain from the DAC, a gain calibration must be performed on the DAC at the factory.

[0005] Figure 2 The diagram shows a traditional reference current generation circuit scheme with gain calibration function. Compared to... Figure 1This scheme adds two pairs of current mirrors (PM4a / PM4b, NM1a / NM1b) between the drain of NM0 and the bias circuit of the DAC main current source array (PM0a, PM1a, PM2a, PM3a). These two pairs of current mirrors replicate the reference current IREF proportionally from the reference current branch to generate the P-terminal adjustment current source array PM4c[i] and the N-terminal adjustment current source array NM1c[i] for gain calibration. The output / input current magnitudes of the adjustment current source arrays PM4c[i] and NM1c[i] are configured by switches, and the current difference between the two is the adjustment current ICAL used for gain calibration; this current is summed with the reference current IREF replicated in NM2b to generate the bias current IBIAS used for the DAC main current source array. By configuring the m-bit control switch control word of PM4c[i] and NM1c[i], the ratio of IBIAS to IREF can be adjusted, thereby achieving accurate calibration of the DAC current gain.

[0006] and Figure 1 compared to, Figure 2 The drawback of the reference current generation circuit is that the additional two current mirrors introduce greater noise, especially 1 / f noise. As can be seen from the comparison... Figure 1 In the reference current generation circuit shown, the noise of VBP0 mainly originates from PM0a, Rset, and op-amp OTA1; while Figure 2 In addition to the three mentioned above, both pairs of current mirrors PM4a / PM4b and NM1a / NM1b will introduce noise into VBP0, which will significantly increase the output current noise density under static conditions and the output noise spectral density (NSD) under dynamic conditions of the DAC.

[0007] Therefore, a new technological solution is needed. Summary of the Invention

[0008] In view of this, embodiments of the present invention provide a low-noise reference current generation circuit with gain calibration function, so as to at least solve the problem of high current noise in circuits with gain calibration function in the prior art.

[0009] The embodiments of the present invention provide the following technical solutions: This invention provides a low-noise reference current generation circuit with gain calibration function, including an external reference voltage, an external resistor, a first operational amplifier, an NMOS transistor NM0, a floating current mirror, a PMOS transistor PMOc, a third operational amplifier, a PMOS transistor PMOa, a PMOS transistor PM1a, a first bias circuit, a current mirror circuit, a P-terminal adjustment current mirror array, a second bias circuit, and an N-terminal adjustment current mirror array. The positive input terminal of the first operational amplifier is connected to the external reference voltage; the gate of the NMOS transistor NM0 is connected to the output terminal of the first operational amplifier, and the source is connected to analog ground; The floating current mirror includes a reference current branch, a replica current branch a, a replica current branch c, and a replica current branch d. One end of the reference current branch is connected to the drain of the NMOS transistor NM0. One end of the replica current branch a is connected to the negative input terminal of the first operational amplifier and connected to the external resistor. One end of the replica current branch c and one end of the replica current branch d are connected to each other, and one end of the replica current branch c is connected to the drain of the NMOS transistor NM1. One end of the replica current branch d is connected to the positive input terminal of the second operational amplifier OTA2. The negative input terminal of the second operational amplifier is connected to the negative input terminal of the first operational amplifier. The output terminal of the second operational amplifier is connected to the NMOS transistor NM1. The source of the NMOS transistor NM1 is connected to analog ground. The other end of the reference current branch is connected to the drain of the PMOS transistor PMOc and the positive input terminal of the third operational amplifier. The source of the PMOS transistor PMOc is connected to the analog power supply voltage. The gate of the PMOS transistor PMOc is connected to the output terminal of the third operational amplifier. The negative input terminal of the third operational amplifier is connected to the drain of the PMOS transistor PM1a, the gate of the PMOS transistor PMOa, the DAC main current array, and the other end of the replication current branch. The source of the PMOS transistor PM1a is connected to the drain of the PMOS transistor PMOa. The drain of the PMOS transistor PM1a is also connected to the other end of the replication current branch a. The source of the PMOS transistor PMOa is connected to the analog voltage. The gate of the PMOS transistor PM1a is connected to the first bias circuit. The first bias circuit, the current mirror circuit, and the P-terminal adjustment current mirror array are connected in series. The first bias circuit is connected to the replication current branch c and the replication current branch d respectively. The P-terminal adjustment current mirrors the DAC main current to provide bias voltage. The current mirror circuit is connected to the second bias circuit, and the second bias circuit is connected to the N-terminal adjustment current mirror array. The current difference between the N-terminal adjustment current mirror array and the P-terminal adjustment current mirror array constitutes the adjustment current for gain calibration, and the adjustment current is injected back into the drain of the NMOS transistor NM2a.

[0010] Preferably, the floating current mirror includes NMOS transistors NM2b and PMOS transistor PM2b, NMOS transistor NM2a and PMOS transistor PM2a, NMOS transistor NM2c and PMOS transistor PM2c, and NMOS transistor NM2d and PMOS transistor PM2d whose sources are interconnected; The gates of NMOS transistors NM2b, NM2a, NM2c, and NM2d are all interconnected, and the gates of PMOS transistors PM2b, PM2a, PM2c, and PM2d are all interconnected. The drain of the NMOS transistor NM2b is connected to the drain of the PMOS transistor PMOc. The gate of the NMOS transistor NM2b is connected to its own source. The drain of the PMOS transistor PM2b is connected to its own gate and the drain of the NMOS transistor NM0c. The gate of the PMOS transistor PM2b is connected to its own source. The drain of the NMOS transistor NM2a is connected to the negative input terminal of the third operational amplifier and the drain of the PMOS transistor PM1a, and its gate is connected to its own source. The drain of the PMOS transistor PM2a is connected to the negative input terminal of the first operational amplifier, and its gate is connected to its own source. The drain of the NMOS transistor NM2c is connected to the first bias circuit, and its gate is connected to the gate of the PMOS transistor PM2c. The drain of the PMOS transistor is connected to the drain of the NMOS transistor NM1. The drain of the NMOS transistor NM2d is connected to the first bias circuit, and its gate is connected to the gate of the PMOS transistor PM2d. The drain of the PMOS transistor PM2d is connected to the positive input terminal of the second operational amplifier and the drain of the PMOS transistor PM2c. The gates of the NMOS transistor NM2c and the PMOS transistor PM2c are interconnected, and the gates of the NMOS transistor NM2d and the PMOS transistor PM2d are interconnected, and both are connected to the source of the NMOS transistor NM2a and the PMOS transistor PM2a.

[0011] Preferably, the first bias circuit includes PMOS transistors PM4, PM1c, PM3d, and PM1d. The source of PMOS transistor PM4 is connected to the analog voltage, and its gate is connected to the drain and gate of PMOS transistor PM1c. The drain of PMOS transistor PM1c is connected to the source of PMOS transistor PM1c. The gate of PMOS transistor PM1c is connected to the gate of PMOS transistor PM1d, and the drain of PMOS transistor PM1c is connected to the drain of NMOS transistor NM2c. The drain of PMOS transistor PM1d is connected to the gate of PMOS transistor PM3d and the drain of NMOS transistor NM2d, respectively. The source of PMOS transistor PM1d is connected to the drain of PMOS transistor PM3d. The source of PMOS transistor PM3d1 is connected to the analog voltage.

[0012] Preferably, the current source circuit includes PMOS transistors PM3e, PM1e, PM3f, and PM1f; The source of PMOS transistor PM3e is connected to the analog voltage, its gate is connected to the gate of PMOS transistor PM3d, and its drain is connected to the source of PMOS transistor PM1e; the gate of PMOS transistor PM1e is connected to the gate of PMOS transistor PM1d, and its drain is connected to the second bias circuit; the source of PMOS transistor PM3f is connected to the analog voltage, its gate is connected to the gate of PMOS transistor PM3e, and its drain is connected to the source of PMOS transistor PM1f; the gate of PMOS transistor PM1f is connected to the gate of PMOS transistor PM1e, and its drain is connected to the second bias circuit.

[0013] Preferably, the second bias circuit includes NMOS transistors NM4c, NMOS transistor NM5, NMOS transistor NM4a, and NMOS transistor NM3a; The drain of NMOS transistor NM4c is connected to the drain and gate of PMOS transistor PM1e, the source is connected to the drain of NMOS transistor NM5, and the gate is connected to the gate of NMOS transistor NM4a. The source of NMOS transistor NM5 is connected to analog ground, and the gate is connected to the gate of NMOS transistor NM4c. The drain of NMOS transistor NM4a is connected to the gate of NMOS transistor NM3a and the drain of PMOS transistor PM1f, respectively, and the source is connected to the drain of NMOS transistor NM3a. The source of NMOS transistor NM3a is connected to analog ground.

[0014] Preferably, the reference current is obtained by controlling the voltage difference across the external resistor as a reference voltage.

[0015] Preferably, the outflow current of both the P-terminal adjustment current mirror array and the N-terminal adjustment current mirror array is configured by a switch.

[0016] Preferably, the output terminals of both the P-terminal adjustment current mirror array and the N-terminal adjustment current mirror array are connected to the drain of the NMOS transistor NM2a.

[0017] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least: This invention proposes a low-noise reference current generation circuit with gain calibration function. By introducing a floating current mirror, the reference current is extracted from the reference current branch and externally generated to adjust the gain. This adjusted current is then reconnected to the reference current branch and summed directly with the original reference current to obtain the final bias current, which is used to generate the gate bias voltage of the DAC current source array. This extraction and reconnection circuit method eliminates the two additional current conversions required in traditional solutions, thereby reducing noise. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an existing current-controlled DAC reference current generation circuit. Figure 2 This is a schematic diagram of an existing current-rudder DAC reference current generation circuit with gain adjustment function. Figure 3 This is a schematic diagram of a low-noise reference current generation circuit with gain calibration function according to an embodiment of the present invention. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0025] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0026] like Figure 3 As shown, this embodiment of the invention provides a low-noise reference current generation circuit with gain calibration function, including an external reference voltage, an external resistor, a first operational amplifier (OTA1), an NMOS transistor NM0, a floating current mirror, a PMOS transistor PM0c, a third operational amplifier (OTA3), a PMOS transistor PM0a, a PMOS transistor PM1a, a first bias circuit, a current mirror circuit, a P-terminal adjustment current mirror array, a second bias circuit, and an N-terminal adjustment current mirror array. The positive input terminal of the first operational amplifier is connected to an external reference voltage; the gate of the NMOS transistor NM0 is connected to the output terminal of the first operational amplifier, and its source is connected to analog ground.

[0027] The floating current mirror includes a reference current branch, a replica current branch a, a replica current branch c, and a replica current branch d. One end of the reference current branch is connected to the drain of NMOS transistor NM0. One end of the replica current branch a is connected to the negative input terminal of the first operational amplifier and connected to an external resistor. One end of the replica current branch c and one end of the replica current branch d are connected to each other, and one end of the replica current branch c is connected to the drain of NMOS transistor NM1. One end of the replica current branch d is connected to the positive input terminal of the second operational amplifier (OTA2). The negative input terminal of the second operational amplifier is connected to the negative input terminal of the first operational amplifier. The output terminal of the second operational amplifier is connected to NMOS transistor NM1. The source of NMOS transistor NM1 is connected to analog ground.

[0028] The other end of the reference current branch is connected to the drain of PMOS transistor PM0c and the positive input terminal of the third operational amplifier. The source of PMOS transistor PM0c is connected to the analog power supply voltage. The gate of PMOS transistor PM0c is connected to the output terminal of the third operational amplifier. The negative input terminal of the third operational amplifier is connected to the drain of PMOS transistor PM1a, the gate of PMOS transistor PM0a, the DAC main current array, and the other end of the replication current branch. The source of PMOS transistor PM1a is connected to the drain of PMOS transistor PM0a. The drain of PMOS transistor PM1a is also connected to the other end of replication current branch a. The source of PMOS transistor PM0a is connected to the analog voltage.

[0029] The gate of PMOS transistor PM1a is connected to the first bias circuit. The first bias circuit, the current mirror circuit, and the P-terminal adjustment current mirror array are connected in series. The first bias circuit is connected to the replication current branch c and the replication current branch d respectively. The P-terminal adjustment current mirror provides the bias voltage by reflecting the DAC main current. The current mirror circuit is connected to the second bias circuit, and the second bias circuit is connected to the N-terminal adjustment current mirror array. The current difference between the N-terminal adjustment current mirror array and the P-terminal adjustment current mirror array constitutes the adjustment current for gain calibration, and the adjustment current is injected back to the drain of NMOS transistor NM2a.

[0030] One way to obtain a reference current is to control the voltage difference across the external resistor as the reference voltage.

[0031] The levitated current mirror is used to achieve calibration and reduce noise, replacing the two additional pairs of independent current mirrors in the prior art.

[0032] The first operational amplifier, the third operational amplifier, the NMOS transistor NMO, the external resistor Rset, the first bias circuit, and the floating current mirror form a closed loop. The reference current IREF = VREF / Rset is accurately generated by ensuring that the voltage difference across the external resistor Rset is equal to the reference voltage VREF.

[0033] Specifically, the reference current IREF flows through the floating current mirror and is replicated through its branches (NM2C / PM2C, NM2d / PM2d). It is then used by the first bias circuit (PM4, PM1c / PM1d, PM3d) to generate the gate bias voltage of the P-terminal adjustment current source array (PM3g[i]). The replicated IREF is then folded towards the N-terminal adjustment current source array through the current mirror circuit (PM3e / PM3f). It is then used by the second bias circuit (NM3a, NM5, NM4a / NM4c) to generate the gate bias voltage of the N-terminal adjustment current source array (NM3b[i]). The difference between the currents of the two branches is the final adjustment current ICAL. ICAL is connected back to the reference current branch and summed with the original reference current IREF to obtain the bias current IBIAS of the DAC main current source array = IREF + ICAL.

[0034] Among them, the bias current IBIAS flows through PMOS transistors PM0a and PM1a to generate the gate bias voltages VBP0 and VBP1 required by the DAC main current source array, thus completing the bias supply.

[0035] Furthermore, the floating current mirror includes NMOS transistors NM2b and PM2b, NMOS transistor NM2a and PM2a, NMOS transistor NM2c and PM2c, and NMOS transistor NM2d and PM2d, all with their sources interconnected; the gates of NMOS transistors NM2b, NMOS transistor NM2a, NMOS transistor NM2c, and NMOS transistor NM2d are all interconnected, and the gates of PMOS transistors PM2b, PM2a, PM2c, and PM2d are all interconnected; the drain of NMOS transistor NM2b is connected to the drain of PMOS transistor PM0c, and the gate of NMOS transistor NM2b is connected to its own source; the drain of PMOS transistor PM2b is connected to its own gate and the drain of NMOS transistor NM0c, and the gate of PMOS transistor PM2b is connected to its own source; the drain of NMOS transistor NM2a is connected to the third... The negative input terminal of the operational amplifier is connected to the drain of PMOS transistor PM1a, and its gate is connected to its own source. The drain of PMOS transistor PM2a is connected to the negative input terminal of the first operational amplifier, and its gate is connected to its own source. The drain of NMOS transistor NM2c is connected to the first bias circuit, and its gate is connected to the gate of PMOS transistor PM2c. The drain of PMOS transistor NM2c is connected to the drain of NMOS transistor NM1. The drain of NMOS transistor NM2d is connected to the first bias circuit, and its gate is connected to the gate of PMOS transistor PM2d. The drain of PMOS transistor PM2d is connected to the positive input terminal of the second operational amplifier and the drain of PMOS transistor PM2c. The gates of NMOS transistor NM2c and PMOS transistor PM2c are interconnected, and the gates of NMOS transistor NM2d and PMOS transistor PM2d are interconnected. After these interconnections, they are all connected to the sources of NMOS transistor NM2a and PMOS transistor PM2a.

[0036] Specifically, by constructing reference and replication branches for the floating current mirror through four sets of source-interconnected NMOS / PMOS transistor pairs, the gate-source voltage of each set of devices is consistent, enabling interference-free extraction and accurate replication of the original reference current (IREF). This provides a stable current reference for the generation of the external adjustment current (ICAL) and maintains the closed-loop stability of the reference current branch to accurately transmit the reference current signal and reduce current replication errors caused by device mismatch. The source-interconnect structure simplifies the link, avoids additional intermediate conversions, and reduces noise introduction.

[0037] Further, the first bias circuit includes PMOS transistors PM4, PM1c, PM3d, and PM1d; the source of PMOS transistor PM4 is connected to the analog voltage, its gate is connected to the drain of PMOS transistor PM1c, the gate of PMOS transistor PM1c is connected to the gate of PMOS transistor PM1c, and its drain is connected to the source of PMOS transistor PM1c; the gate of PMOS transistor PM1c is connected to the gate of PMOS transistor PM1d, and the drain of PMOS transistor PM1c is connected to the drain of NMOS transistor NM2c; the drain of PMOS transistor PM1d is connected to the gate of PMOS transistor PM3d and the drain of NMOS transistor NM2d, respectively, and the source of PMOS transistor PM1d is connected to the drain of PMOS transistor PM3d; the source of PMOS transistor PM3d1 is connected to the analog voltage.

[0038] The first bias circuit is used to receive the current signal from the floating current mirror replication branches (NM2c, NM2d). Through the mirror structure of PMOS transistor gate interconnection and source-drain coupling, the replication current is converted into a stable gate bias voltage, which provides a suitable bias drive for the P-terminal trimming current source array (PM3g[i]). At the same time, it relies on analog voltage (AVDD) power supply to ensure bias stability, so as to generate a low-noise, high-consistency bias voltage and ensure that the P-terminal trimming current is accurate and controllable.

[0039] Furthermore, the current source circuit includes PMOS transistors PM3e, PM1e, PM3f, and PM1f; the source of PMOS transistor PM3e is connected to the analog voltage, its gate is connected to the gate of PMOS transistor PM3d, and its drain is connected to the source of PMOS transistor PM1e; the gate of PMOS transistor PM1e is connected to the gate of PMOS transistor PM1d, and its drain is connected to the second bias circuit; the source of PMOS transistor PM3f is connected to the analog voltage, its gate is connected to the gate of PMOS transistor PM3e, and its drain is connected to the source of PMOS transistor PM1f; the gate of PMOS transistor PM1f is connected to the gate of PMOS transistor PM1e, and its drain is connected to the second bias circuit.

[0040] The current source circuit receives and accurately replicates the current signal from the first bias circuit through a mirror structure with multiple PMOS transistor gate interconnections and source-drain coupling. It maintains current stability by relying on analog voltage (AVDD) power supply and transmits the adapted current signal to the second bias circuit. This provides a precise current reference for the bias generation of the N-terminal adjustment current source array (NM3b[i]) and ensures consistency with the current ratio of the P-terminal adjustment circuit.

[0041] Furthermore, the second bias circuit includes NMOS transistors NM4c, NMOS transistor NM5, NMOS transistor NM4a, and NMOS transistor NM3a; the drain of NMOS transistor NM4c is connected to the drain and gate of PMOS transistor PM1e, the source is connected to the drain of NMOS transistor NM5, and the gate is connected to the gate of NMOS transistor NM4a; the source of NMOS transistor NM5 is connected to analog ground, and the gate is connected to the gate of NMOS transistor NM4c; the drain of NMOS transistor NM4a is connected to the gate of NMOS transistor NM3a and the drain of PMOS transistor PM1f, respectively, the source is connected to the drain of NMOS transistor NM3a, and the source of NMOS transistor NM3a is connected to analog ground.

[0042] In this embodiment of the invention, the magnitudes of the outflow current of both the P-terminal and N-terminal trimmed current mirror arrays are configured via switches. Furthermore, the output terminals of both the P-terminal and N-terminal trimmed current mirror arrays are connected to the drain of the NMOS transistor NM2a.

[0043] This invention proposes a reference current generation circuit with gain adjustment function suitable for monolithic current-controlled DACs, such as... Figure 3 As shown. NM2a / NM2b and PM2a / PM2b form a floating current mirror, which is connected in series between the external resistor Rset and the bias circuit (PM0a / PM1a) of the DAC main current source array.

[0044] The working principle of this invention is as follows: The reference current flows through NM2a / PM2a and is replicated through the NM2C / PM2C and NM2d / PM2d branches of the current mirror. This replicated current is then used by the bias circuits PM4, PM1c / PM1d, and PM3d to generate the gate bias voltage for the P-terminal adjustment current source array PM3g[i] used for gain calibration. Further, the current mirror branch PM3e / PM3f redirects the first replicated current IREF back to the N-terminal, generating the gate bias voltage for the N-terminal adjustment current source array NM3b[i] used for gain calibration through the bias circuits NM3a, NM5, and NM4a / NM4c. The difference between the currents in NM3b[i] and PM3g[i] serves as the final adjustment current ICAL for gain calibration. ICAL is connected back to the drain of NM2a and summed with the original reference current IREF to obtain the bias current IBIAS used for biasing the DAC main current source array. After IBIAS flows through PM0a and PM1a, it obtains the bias voltages VBP0 and VBP1 of the DAC current source array.

[0045] In summary, besides the operational amplifier OTA1, resistor Rset, and PM0a, the only devices contributing noise to VBP0 in the reference current generation circuit proposed in this invention are the trimming current source arrays NM3b[i] and PM3g[i]. Since the magnitude of the trimming current ICAL is much smaller than the reference current IREF, the noise introduced by NM3b[i] and PM3g[i] can be ignored. The noise on VBP0 is related to... Figure 1 The reference current generation circuit, which does not include gain adjustment function, is approximately the same.

[0046] This invention introduces a set of floating current mirrors into the reference current branch of existing solutions. A closed-loop control mechanism is used to determine the reference current as the quotient of the reference voltage and the external resistor. The floating current mirrors replicate the reference current from the reference current branch, generating an external adjustment current for gain calibration. This adjustment current is then fed back into the reference current branch and summed with the original reference current to serve as the bias current for the DAC main current source array. This bias current generates the gate bias of the DAC main current source array through a bias circuit. Compared to traditional reference current generation circuits, the reference current generation circuit proposed in this invention offers the advantage of low noise while providing gain calibration functionality.

[0047] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0048] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A low-noise reference current generation circuit with gain calibration function, characterized in that, It includes an external reference voltage, an external resistor, a first operational amplifier, an NMOS transistor NM0, a floating current mirror, a PMOS transistor PM0c, a third operational amplifier, a PMOS transistor PM0a, a PMOS transistor PM1a, a first bias circuit, a current mirror circuit, a P-terminal adjustment current mirror array, a second bias circuit, and an N-terminal adjustment current mirror array. The positive input terminal of the first operational amplifier is connected to the external reference voltage; the gate of the NMOS transistor NM0 is connected to the output terminal of the first operational amplifier, and the source is connected to analog ground; The floating current mirror includes a reference current branch, a replica current branch a, a replica current branch c, and a replica current branch d. One end of the reference current branch is connected to the drain of the NMOS transistor NM0. One end of the replica current branch a is connected to the negative input terminal of the first operational amplifier and connected to the external resistor. One end of the replica current branch c and one end of the replica current branch d are connected to each other, and one end of the replica current branch c is connected to the drain of the NMOS transistor NM1. One end of the replica current branch d is connected to the positive input terminal of the second operational amplifier OTA2. The negative input terminal of the second operational amplifier is connected to the negative input terminal of the first operational amplifier. The output terminal of the second operational amplifier is connected to the NMOS transistor NM1. The source of the NMOS transistor NM1 is connected to analog ground. The other end of the reference current branch is connected to the drain of the PMOS transistor PMOc and the positive input terminal of the third operational amplifier. The source of the PMOS transistor PMOc is connected to the analog power supply voltage. The gate of the PMOS transistor PMOc is connected to the output terminal of the third operational amplifier. The negative input terminal of the third operational amplifier is connected to the drain of the PMOS transistor PM1a, the gate of the PMOS transistor PMOa, the other end of the replication current branch, and the DAC main current array. The source of the PMOS transistor PM1a is connected to the drain of the PMOS transistor PMOa. The drain of the PMOS transistor PM1a is also connected to the other end of the replication current branch a. The source of the PMOS transistor PMOa is connected to the analog voltage. The gate of the PMOS transistor PM1a is connected to the first bias circuit. The first bias circuit, the current mirror circuit, and the P-terminal adjustment current mirror array are connected in series. The first bias circuit is connected to the other end of the replicated current branch c and the replicated current branch d respectively. The P-terminal adjustment current mirrors the DAC main current to provide a bias voltage. The current mirror circuit is connected to the second bias circuit, and the second bias circuit is connected to the N-terminal adjustment current mirror array. The current difference between the N-terminal adjustment current mirror array and the P-terminal adjustment current mirror array constitutes the adjustment current for gain calibration, and the adjustment current is injected back into the drain of the NMOS transistor NM2a.

2. The low-noise reference current generation circuit according to claim 1, characterized in that, The floating current mirror includes NMOS transistors NM2b and PMOS transistor PM2b, NMOS transistor NM2a and PMOS transistor PM2a, NMOS transistor NM2c and PMOS transistor PM2c, and NMOS transistor NM2d and PMOS transistor PM2d whose sources are connected to each other; The gates of NMOS transistors NM2b, NM2a, NM2c, and NM2d are all interconnected, and the gates of PMOS transistors PM2b, PM2a, PM2c, and PM2d are all interconnected. The drain of the NMOS transistor NM2b is connected to the drain of the PMOS transistor PMOc. The gate of the NMOS transistor NM2b is connected to its own source. The drain of the PMOS transistor PM2b is connected to its own gate and the drain of the NMOS transistor NM0c. The gate of the PMOS transistor PM2b is connected to its own source. The drain of the NMOS transistor NM2a is connected to the negative input terminal of the third operational amplifier and the drain of the PMOS transistor PM1a, and its gate is connected to its own source. The drain of the PMOS transistor PM2a is connected to the negative input terminal of the first operational amplifier, and its gate is connected to its own source. The drain of the NMOS transistor NM2c is connected to the first bias circuit, and its gate is connected to the gate of the PMOS transistor PM2c. The drain of the PMOS transistor is connected to the drain of the NMOS transistor NM1. The drain of the NMOS transistor NM2d is connected to the first bias circuit, and its gate is connected to the gate of the PMOS transistor PM2d. The drain of the PMOS transistor PM2d is connected to the positive input terminal of the second operational amplifier and the drain of the PMOS transistor PM2c. The gates of the NMOS transistor NM2c and the PMOS transistor PM2c are interconnected, and the gates of the NMOS transistor NM2d and the PMOS transistor PM2d are interconnected, and both are connected to the source of the NMOS transistor NM2a and the PMOS transistor PM2a.

3. The low-noise reference current generation circuit according to claim 2, characterized in that, The first bias circuit includes PMOS transistors PM4, PM1c, PM3d, and PM1d. The source of PMOS transistor PM4 is connected to the analog voltage, and its gate is connected to the drain and gate of PMOS transistor PM1c. The drain of PMOS transistor PM1c is connected to the source of PMOS transistor PM1c. The gate of PMOS transistor PM1c is connected to the gate of PMOS transistor PM1d, and the drain of PMOS transistor PM1c is connected to the drain of NMOS transistor NM2c. The drain of PMOS transistor PM1d is connected to the gate of PMOS transistor PM3d and the drain of NMOS transistor NM2d, respectively. The source of PMOS transistor PM1d is connected to the drain of PMOS transistor PM3d. The source of PMOS transistor PM3d1 is connected to the analog voltage.

4. The low-noise reference current generation circuit according to claim 3, characterized in that, The current source circuit includes PMOS transistors PM3e, PM1e, PM3f, and PM1f. The source of PMOS transistor PM3e is connected to the analog voltage, its gate is connected to the gate of PMOS transistor PM3d, and its drain is connected to the source of PMOS transistor PM1e; the gate of PMOS transistor PM1e is connected to the gate of PMOS transistor PM1d, and its drain is connected to the second bias circuit; the source of PMOS transistor PM3f is connected to the analog voltage, its gate is connected to the gate of PMOS transistor PM3e, and its drain is connected to the source of PMOS transistor PM1f; the gate of PMOS transistor PM1f is connected to the gate of PMOS transistor PM1e, and its drain is connected to the second bias circuit.

5. The low-noise reference current generation circuit according to claim 4, characterized in that, The second bias circuit includes NMOS transistors NM4c, NM5, NM4a, and NM3a; The drain of NMOS transistor NM4c is connected to the drain and gate of PMOS transistor PM1e, the source is connected to the drain of NMOS transistor NM5, and the gate is connected to the gate of NMOS transistor NM4a. The source of NMOS transistor NM5 is connected to analog ground, and the gate is connected to the gate of NMOS transistor NM4c. The drain of NMOS transistor NM4a is connected to the gate of NMOS transistor NM3a and the drain of PMOS transistor PM1f, respectively, and the source is connected to the drain of NMOS transistor NM3a. The source of NMOS transistor NM3a is connected to analog ground.

6. The low-noise reference current generation circuit according to claim 1, characterized in that, The reference current is obtained by controlling the voltage difference across the external resistor as a reference voltage.

7. The low-noise reference current generation circuit according to claim 1, characterized in that, The magnitude of the outflow current of both the P-terminal and N-terminal adjustment current mirror arrays is configured via switches.

8. The low-noise reference current generation circuit according to claim 7, characterized in that, The output terminals of both the P-terminal and N-terminal adjustment current mirror arrays are connected to the drain of the NMOS transistor NM2a.

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