Instruction dependency relationship maintenance method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, in particular to an instruction dependency relationship maintenance method and device, electronic equipment and a storage medium, the method comprises the following steps: in response to instruction window state update information from an upstream processing module, determining an index value corresponding to an instruction identifier in the state update information, the index value is used for indicating a corresponding position of the instruction identifier in a first binary bit set, and the first binary bit set comprises a plurality of binary bits representing whether the instruction is valid or not; on the basis of the instruction window state updating information and the first binary bit set, a dependency bit set corresponding to the index value is updated through bit operation, and the dependency bit set is used for representing other effective instructions which any effective instruction can reach on the basis of binary bits. According to the embodiment of the invention, the efficiency of instruction dependency maintenance and query can be effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and storage medium for maintaining instruction dependencies. Background Technology

[0002] In the early stages of GPU development, software modeling is typically used to simulate the hardware rendering pipeline to verify its functionality and performance, and to provide a unified verification platform for software development. During this process, the GPU pipeline needs to parse and execute a large number of compiler-generated instructions, and this parsing and execution often occur in parallel. To ensure the correctness of parallel execution, instruction dependency checking becomes a critical step in the pipeline. It is used to determine whether there are direct or indirect dependencies between any two instructions, thereby guaranteeing the legality and order of instruction scheduling.

[0003] In related technologies, the maintenance and querying of instruction dependencies are typically implemented based on graph structures, representing dependencies by constructing instruction nodes and their dependent edges. When the state of the instruction window changes (e.g., inserting or deleting instructions), the graph structure needs to be updated. Such maintenance operations often involve the dynamic addition and deletion of nodes and edges, introducing significant management overhead in scenarios where instruction dependencies change dynamically. Furthermore, dependency queries require pathfinding using graph traversal algorithms (such as depth-first search or breadth-first search), resulting in high computational complexity. These graph-based methods are insufficient in terms of both the real-time performance of dependency maintenance and the response speed of dependency queries, leading to low maintenance and query efficiency and failing to meet the stringent efficiency requirements of high-performance pipeline simulations. Summary of the Invention

[0004] In view of this, this disclosure proposes a technical solution for maintaining instruction dependencies.

[0005] According to one aspect of this disclosure, a method for maintaining instruction dependencies is provided, comprising:

[0006] In response to instruction window status update information from the upstream processing module, the index value corresponding to the instruction identifier in the status update information is determined. The index value is used to indicate the corresponding position of the instruction identifier in a first binary bit set, which includes multiple binary bits indicating whether the instruction is valid.

[0007] Based on the instruction window state update information and the first set of binary bits, the dependency bit set corresponding to the index value is updated through bit operations. The dependency bit set is used to represent other valid instructions that any valid instruction can reach based on binary bits.

[0008] In one possible implementation, the number of binary bits in the first binary bit set is N, and the index value ranges from 0 to N-1, where N is a constant greater than the maximum length of the instruction window.

[0009] In one possible implementation, the first set of binary bits is implemented based on a circular queue of length N, where each position in the circular queue corresponds to a binary bit, and a value of 1 for the bit indicates that the instruction corresponding to the index value is currently in the valid instruction window;

[0010] Determining the index value corresponding to the instruction identifier in the status update information includes:

[0011] In response to the status update information indicating the insertion of a new instruction, an index value of a free binary bit is allocated through the circular queue, and the free binary bit is set to 1;

[0012] Construct a mapping relationship between the program counter value of the new instruction and the allocated index value.

[0013] In one possible implementation, the circular queue includes three pointers: a head pointer, a tail pointer, and a delay pointer;

[0014] The first pointer points to the position of the binary bit corresponding to the most recently inserted instruction;

[0015] The tail pointer points to the position of the next binary bit that will be marked as invalid;

[0016] The delay pointer points to the starting position of the delay clearing operation.

[0017] In one possible implementation, the method further includes:

[0018] When inserting a new instruction, after setting the binary bit to 1, the head pointer is moved one bit in the forward direction of the queue to the newly set position of 1;

[0019] In response to the status update information indicating the deletion of expired instructions, the tail pointer is moved one position in the forward direction of the queue to mark the instruction as expired.

[0020] In one possible implementation, the method further includes:

[0021] When the first pointer moves to coincide with the delayed pointer, all binary bits in the circular queue within the range indicated by the delayed pointer to the bit before the tail pointer are set to 0, and the delayed pointer is updated to the tail pointer.

[0022] In one possible implementation, the dependency bit set includes a dependency bit set maintained for each index value, each dependency bit set being an N-bit second binary bit set, where a 1 in the j-th bit indicates that the instruction corresponding to the index value depends on the instruction corresponding to the index value j.

[0023] The step of updating the dependency bit set corresponding to the index value through bitwise operations based on the instruction window state update information and the first binary bit set includes:

[0024] When the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, the bitwise OR operation is performed between the bitwise dependent bit set corresponding to index value b and the bitwise dependent bit set corresponding to index value a, and the result is used as the updated bitwise dependent bit set of index value a.

[0025] Perform a bitwise AND operation between the updated set of dependency bits and the first set of binary bits, and remove the dependency records of instructions that are no longer in the valid window.

[0026] In one possible implementation, the dependency bit set further includes a direct dependency bit set maintained for each index value, each of the direct dependency bit sets being an N-bit third binary bit set, where the k-th bit being 1 indicates that the instruction corresponding to index value k directly depends on the instruction corresponding to that index value; the method further includes:

[0027] If the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, then the bit corresponding to index value a in the set of directly dependent bits of index value b is set to 1.

[0028] In one possible implementation, determining the dependency relationship between the first instruction and the second instruction based on the dependency bit set includes:

[0029] Obtain the first index value s corresponding to the first instruction and the second index value t corresponding to the second instruction;

[0030] Check if the t-th bit in the dependency bit set of the first index value s is 1;

[0031] If the value is 1, then the first instruction is determined to depend on the second instruction.

[0032] In one possible implementation, the method further includes:

[0033] In response to a dependency query request from an upstream processing module, the dependency relationship between the first instruction and the second instruction is determined based on the dependency bit set.

[0034] In one possible implementation, the method further includes:

[0035] In response to a dependency path query request for the first instruction to the second instruction, a fourth binary bit set is initialized, wherein the bit corresponding to the first index value s of the first instruction is set to 1;

[0036] Based on the set of dependent bits of the first instruction, the set of direct dependent bits of each index value, and the set of the fourth binary bits, the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction is determined.

[0037] In one possible implementation, determining the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction includes:

[0038] Following the order from the tail pointer to the position before the head pointer in the circular queue, traverse each bit in the dependency bit set of the first index value s that is 1, and perform the following steps for the current index value:

[0039] Perform a bitwise AND operation between the set of direct dependent bits of the current index value and the fourth set of binary bits to obtain the set of preceding binary bits;

[0040] Determine a predecessor index value from the predecessor binary bit set;

[0041] The path information of the current index value is determined based on the predecessor index value and stored in the path record;

[0042] Set the bit corresponding to the current index value to 1 to update the fourth binary bit set;

[0043] Check if the current index value is equal to the second index value t. If yes, stop traversing; otherwise, continue traversing to the next index.

[0044] After stopping the traversal, the path information corresponding to the second index value t is obtained from the path record and output.

[0045] In one possible implementation, the method further includes:

[0046] Record and output key status information during the instruction dependency maintenance and query process. The key status information includes at least one of the following: program counter values ​​that are inserted or deleted, newly added direct dependencies, query requests and results, and extracted dependency paths.

[0047] According to another aspect of this disclosure, an instruction dependency maintenance apparatus is provided, comprising:

[0048] An index value determination module is used to determine the index value corresponding to the instruction identifier in the status update information in response to the instruction window status update information from the upstream processing module. The index value is used to indicate the corresponding position of the instruction identifier in a first binary bit set, which includes multiple binary bits indicating whether the instruction is valid.

[0049] The dependency set maintenance module is used to update the dependency bit set corresponding to the index value through bit operations based on the instruction window state update information and the first binary bit set. The dependency bit set is used to represent other valid instructions that can be reached by any valid instruction based on binary bits.

[0050] According to another aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0051] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0052] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0053] In this embodiment, in response to instruction window state update information from the upstream processing module, an index value corresponding to the instruction identifier in the state update information is determined. This index value indicates the corresponding position of the instruction identifier in a first set of binary bits, which includes multiple binary bits indicating whether an instruction is valid. This allows the dynamic changes of the instruction window to be tracked and represented by a compact bitmap data structure, thereby reflecting the set of valid instructions in real time with low overhead. Subsequently, based on the instruction window state update information and the first set of binary bits, the dependency bit set corresponding to the index value is updated through bit operations. This dependency bit set is used to represent other valid instructions that any valid instruction can reach based on binary bits, thereby encoding the direct and indirect dependencies between instructions into a computationally efficient bit pattern, which is maintained synchronously with the window state. Therefore, the dynamic changes of the instruction window are mapped to a compact bitmap data structure, enabling low-overhead, real-time maintenance of the effective instruction set. Simultaneously, through a bitwise operation-based update mechanism for the dependency bit set, the dependencies between instructions are encoded into an efficient bit pattern, ensuring synchronized and accurate maintenance with changes in the instruction window state. This provides a real-time and structured dependency data foundation for subsequent operations. The dependency bit set can be used for dependency lookup. Since the dependency bit set represents other effective instructions reachable from any effective instruction based on binary bits, dependency lookup eliminates the need for real-time graph traversal or path searching. Dependencies can be determined based on binary bits, significantly reducing computational complexity and improving the efficiency of instruction dependency maintenance and lookup.

[0054] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0055] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0056] Figure 1 A schematic diagram illustrating the interaction between the upstream processing module and the instruction dependency checking module provided according to an embodiment of this disclosure is shown.

[0057] Figure 2 A flowchart illustrating a method for maintaining instruction dependencies according to an embodiment of the present disclosure is shown.

[0058] Figure 3 A schematic diagram of a circular queue structure according to an embodiment of the present disclosure is shown.

[0059] Figure 4 A schematic diagram of the structure of an instruction dependency checking module provided according to an embodiment of the present disclosure is shown.

[0060] Figure 5 A swimlane diagram illustrating the interaction flow of each module in the instruction dependency checking module provided according to an embodiment of the present disclosure is shown.

[0061] Figure 6 A schematic diagram of the structure of a software simulation platform provided according to an embodiment of the present disclosure is shown.

[0062] Figure 7 A block diagram illustrating an apparatus for maintaining instruction dependencies according to an embodiment of the present disclosure.

[0063] Figure 8 This is a block diagram illustrating an apparatus for maintaining instruction dependencies according to an exemplary embodiment. Detailed Implementation

[0064] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0065] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0066] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0067] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0068] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0069] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0070] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0071] In the development process of a Graphics Processing Unit (GPU), to perform functional verification and software development before the hardware design is completed, it is usually necessary to simulate the GPU's rendering pipeline through software modeling. The core of this simulation process lies in parsing and executing a large number of rendering instructions generated by the compiler, and the parsing and execution of these instructions often occur in parallel. To ensure the correctness of parallel execution, instruction dependency checking becomes an indispensable key component of the simulated pipeline. It needs to be able to quickly determine whether there is an indirect dependency between any two instructions based on the known direct dependencies in the instruction window, thereby providing a legal basis for instruction scheduling.

[0072] In related technologies, the implementation of such instruction-dependent query functions typically employs two main paths. One path is based on Electronic System Level (ESL) modeling using C++ frameworks such as SystemC, which accurately describes hardware behavior by simulating signal and event interactions between modules. While this method can achieve high modeling accuracy, it requires handling a large number of low-level hardware details such as registers and signals, resulting in complex and time-consuming model construction, and a low level of code abstraction.

[0073] Another approach is to abstract instructions and their dependencies into a graph structure and use graph traversal algorithms (such as depth-first search or breadth-first search) for dependency queries. However, in typical application scenarios where the instruction window is small (e.g., no more than 10 instructions), traditional graph traversal algorithms fail to fully utilize this limited scale, potentially introducing unnecessary computational overhead and affecting query efficiency.

[0074] Furthermore, the above implementation methods often tightly couple the representation of dependencies with specific hardware information such as the program counter value of the instruction, which limits the versatility and reusability of the module, and also increases the difficulty for software developers to understand and locate problems during the debugging process.

[0075] Based on this, this disclosure provides a method for maintaining instruction dependencies to solve at least one of the problems of the prior art.

[0076] For ease of description, in one or more embodiments of this specification, the execution subject of the method may be an instruction dependency checking module. The following description uses the instruction dependency checking module as the execution subject to illustrate the implementation of the method. It should be understood that using the instruction dependency checking module as the execution subject is merely an illustrative example and should not be construed as a limitation of the method.

[0077] Figure 1 This diagram illustrates the interaction between an upstream processing module and an instruction dependency checking module according to an embodiment of this disclosure. The upstream processing module may be a GPU pipeline simulation unit, such as... Figure 1 As shown, when the instruction window state changes (e.g., inserting a new instruction, deleting an expired instruction, or adding a direct dependency), the GPU pipeline simulation unit sends state update information, including the operation type and related program counter values, to the instruction dependency checking module. This module internally maps and indexes instruction identifiers and updates the dependency bit set in real-time based on bitwise operations. When the pipeline simulation unit subsequently issues a dependency query request, the instruction dependency checking module directly judges based on the maintained dependency bit set and returns the query result (whether a dependency exists, or if necessary, the dependency path) to the upstream, serving as the basis for the legality of instruction scheduling and execution.

[0078] At the implementation level, this solution shields low-level hardware details such as registers and signals, abstracting instruction-dependent lookups to a higher level of software modeling. This high level of abstraction avoids strong coupling with specific hardware circuits, thereby significantly reducing unnecessary inter-module communication and management overhead. This not only improves software development efficiency but also creates more room for performance optimization of the algorithm itself.

[0079] Figure 2 A flowchart illustrating a method for maintaining instruction dependencies according to an embodiment of this disclosure is shown. Figure 2 As shown, this method is applied to the instruction simulation process of a graphics processor pipeline, including:

[0080] In step S11, in response to the instruction window status update information from the upstream processing module, the index value corresponding to the instruction identifier in the status update information is determined. The index value is used to indicate the corresponding position of the instruction identifier in the first binary bit set, which includes multiple binary bits indicating whether the instruction is valid.

[0081] During the instruction simulation of a graphics processing unit (GPU) pipeline, a large number of rendering instructions generated by the compiler are parsed and executed, and the parsing and execution of these instructions often occur in parallel. To ensure the correctness of parallel instruction execution, instruction dependency checking is a critical step in the simulation pipeline. The instruction dependency checking module maintains instruction dependencies for subsequent instruction dependency checks.

[0082] The instruction dependency checking module can receive instruction window state update information from upstream processing modules (e.g., modules simulating GPU pipelines). The instruction identifier can be information used to distinguish different instructions. For example, the instruction identifier can be the instruction's program counter value (PC), which indicates the instruction's memory address.

[0083] An index value can be an integer located within a specific continuous range of values. This index value is used to efficiently reference the corresponding instruction in subsequent bit-based or array-based data structures. Associating instruction identifiers with long bits or variable ranges with a finite index facilitates processing using fixed-length, compact data structures.

[0084] The first binary bit set is a data structure that uses a sequence of binary bits to represent a set. In this set, the position of each binary bit is associated with a specific index value, and thus with a specific instruction. The status value set for a binary bit (e.g., set to 1) indicates that the instruction corresponding to that index value is currently valid and belongs to the set of valid instructions in the instruction window.

[0085] Instruction window state update information refers to the information sent by the upstream processing module to the instruction dependency checking module during the graphics processor pipeline simulation to synchronize the dynamic changes of the instruction window. This information indicates that events such as instruction insertion or deletion have occurred in the instruction window, thereby triggering a corresponding update of the internal state of the instruction dependency checking module. Specifically, this information may include the operation type and the associated instruction identifier (e.g., program counter value). The operation type is used to characterize the update action to be performed; for example, indicating that a new instruction needs to be added to the current window, or indicating that an instruction already in the window has become invalid and removed after execution, or adding a new dependency.

[0086] Based on the received status update information, the instruction dependency checking module determines the index value corresponding to the instruction identifier. In some specific implementations, a mapping table between instruction identifiers and index values ​​can be maintained to support bidirectional lookup. For the operation of inserting a new instruction, the instruction dependency checking module allocates a free index value through its internal circular queue and stores the mapping relationship between the instruction identifier of the new instruction (e.g., a 64-bit PC value) and the allocated index value. Subsequently, the instruction dependency checking module updates the first binary bit set according to the index value, setting the binary bits corresponding to the index value in the set to 1, so that the set can reflect the composition of all valid instructions in the current instruction window.

[0087] For example, if the index value assigned to a new instruction is 5, then the 5th bit (assuming the least significant bit is bit 0) of the first set of binary bits can be set to 1. This indicates that index value 5 now corresponds to an instruction within the valid window. By maintaining such a set of bits, the index range of all currently valid instructions can be quickly obtained, facilitating subsequent determination of whether dependencies exist among valid instructions. For operations such as deleting instructions or querying dependencies, the index value corresponding to the instruction identifier is determined by querying the stored mapping table.

[0088] In step S12, based on the instruction window state update information and the first binary bit set, the dependency bit set corresponding to the index value is updated by bit operations. The dependency bit set is used to represent other valid instructions that any valid instruction can reach based on binary bits.

[0089] A dependency bit set can be a data structure used to record dependencies between instructions. This set can be organized in the form of binary bits, where each instruction within the effective window can be associated with an independent bit set. Each such bit set can contain multiple binary bits, and each bit can correspond to a possible instruction index. If a bit is set to 1, it indicates that the instruction associated with that bit set depends on another instruction indicated by the index value corresponding to that bit. In this way, a bit set can compactly represent all other instructions that an instruction directly or indirectly depends on.

[0090] To ensure that the dependency record remains synchronized with the dynamic changes of the instruction window and the newly established direct dependencies between instructions, the instruction dependency checking module can update the dependency bit set based on the received instruction window state update information and the maintained first binary bit set. The update process typically involves performing corresponding bitwise logical operations on a specific bit set according to the type of update information (e.g., whether a new instruction is inserted or a new direct dependency is added).

[0091] In some implementations, the instruction window state update information can indicate the addition of a direct dependency between two existing instructions. For example, it can be specified that the instruction with index 'a' directly depends on the instruction with index 'b'. In this case, the instruction dependency checking module can obtain the current dependency bit set corresponding to index 'b' (this set records all instructions that 'b' can reach) and perform a bitwise OR operation with the current dependency bit set corresponding to index 'a'. Afterward, the instruction dependency checking module can write the result back as the updated dependency bit set for index 'a'. This transfers all existing dependencies of instruction 'b' (including direct and indirect dependencies) to instruction 'a', thus fully establishing all indirect dependencies reachable through 'b' in the bit set of 'a'.

[0092] Furthermore, to ensure that the dependency bit set only records instructions within the currently valid window and avoids retaining outdated dependencies on deleted instructions, the instruction dependency checking module can perform a bitwise AND operation between the dependency bit set and the first binary bit set (i.e., the valid instruction set) when or after updating the dependency bit set. This operation clears the bits corresponding to the indices of expired instructions, thereby removing invalid dependency records and maintaining the accuracy and simplicity of the dependency data. Through this mechanism combining instruction status and bitwise operations, efficient and real-time maintenance of dependencies can be achieved.

[0093] For details on updating the dependency bit set, please refer to the possible implementations provided in this disclosure; they will not be elaborated here.

[0094] In this embodiment, in response to instruction window state update information from the upstream processing module, an index value corresponding to the instruction identifier in the state update information is determined. This index value indicates the corresponding position of the instruction identifier in a first set of binary bits, which includes multiple binary bits indicating whether an instruction is valid. This allows the dynamic changes of the instruction window to be tracked and represented by a compact bitmap data structure, thereby reflecting the set of valid instructions in real time with low overhead. Subsequently, based on the instruction window state update information and the first set of binary bits, the dependency bit set corresponding to the index value is updated through bit operations. This dependency bit set is used to represent other valid instructions that any valid instruction can reach based on binary bits, thereby encoding the direct and indirect dependencies between instructions into a computationally efficient bit pattern, which is maintained synchronously with the window state. Therefore, the dynamic changes of the instruction window are mapped to a compact bitmap data structure, enabling low-overhead, real-time maintenance of the effective instruction set. Simultaneously, through a bitwise operation-based update mechanism for the dependency bit set, the dependencies between instructions are encoded into an efficient bit pattern, ensuring synchronized and accurate maintenance with changes in the instruction window state. This provides a real-time and structured dependency data foundation for subsequent operations. The dependency bit set can be used for dependency lookup. Since the dependency bit set represents other effective instructions reachable from any effective instruction based on binary bits, dependency lookup eliminates the need for real-time graph traversal or path searching. Dependencies can be determined based on binary bits, significantly reducing computational complexity and improving the efficiency of instruction dependency maintenance and lookup.

[0095] In one possible implementation, the number of binary bits in the first binary bit set is N, and the index value ranges from 0 to N-1, where N is a constant greater than the maximum length of the instruction window.

[0096] In the simulation of a graphics processing unit (GPU) pipeline, the instruction window can be a buffer area or logical set used to temporarily store and manage instructions that are currently being processed or awaiting processing. This window can characterize the range of instructions that the pipeline can simultaneously observe and perform dependency analysis at a given moment. Typically, the instruction window is finite in size, simulating the actual physical limitations or design constraints present in the hardware pipeline.

[0097] The first set of binary bits can be a set with a fixed number of binary bits, denoted as N. N can be a predefined constant. The value of this constant N can be based on the length of the instruction window, for example, making it greater than the maximum number of instructions the instruction window can hold simultaneously (i.e., the maximum length of the instruction window). This design provides a fixed-size index space for the mapping of instruction identifiers, large enough to accommodate all potentially active instructions.

[0098] For example, when simulating a graphics processor pipeline with a maximum instruction window length of 10, the constant N can be set to 32. Then, the sets in this disclosure can be implemented using the uint32 data type. This value ensures that the index space (0 to 31) is sufficient to cover and exceed all potentially concurrently valid instructions, providing ample buffering for dynamic instruction insertion and deletion. It also facilitates efficient bit set operations using the native bit manipulation instructions of 32-bit integers in modern processors.

[0099] Under this configuration, a circular queue of length 32 can be maintained to implement the first set of binary bits. Each position in the queue corresponds to an index value from 0 to 31, and the binary bit stored therein indicates whether the instruction at the corresponding index value is currently in the valid instruction window (e.g., 1 indicates valid, 0 indicates invalid).

[0100] When an upstream module instructs the insertion of a new instruction, the circular queue allocates an index value (let's say 5) from its managed free position and sets the value of the 5th bit in the queue to 1. The mapping between the new instruction's program counter value (e.g., 0x4008 for 64-bit instruction) and the allocated index value 5 is stored in a separate mapping table (such as a hash table). Thus, all valid instructions are organized into a fixed and contiguous index space from 0 to 31 for reference.

[0101] In this embodiment of the disclosure, the number of binary bits in the first binary bit set is N, and the index value ranges from 0 to N-1, where N is a constant greater than the maximum length of the instruction window. All bitwise operations based on the fixed-range index (such as bitwise AND, bitwise OR, shift, and bitwise test) have deterministic and constant-time complexity, which makes dependency update and query operations highly efficient and predictable in performance.

[0102] In one possible implementation, the first set of binary bits is implemented based on a circular queue of length N, where each position in the circular queue corresponds to a binary bit, and a value of 1 for the bit indicates that the instruction corresponding to the index value is currently in the valid instruction window;

[0103] Determining the index value corresponding to the instruction identifier in the status update information includes:

[0104] In response to the status update information indicating the insertion of a new instruction, an index value of a free binary bit is allocated through the circular queue, and the free binary bit is set to 1;

[0105] Construct a mapping relationship between the program counter value of the new instruction and the allocated index value.

[0106] The first set of binary bits is implemented using a circular queue of length N. The circular queue is a logically contiguous, fixed-length linear data structure, with its length consistent with a preset constant N. Each storage location (or slot) in the queue corresponds to an index value from 0 to N-1 and stores one binary bit. The value of this binary bit indicates whether the instruction pointed to by its corresponding index value is currently within a valid instruction window: when the bit is set to 1, it indicates that the corresponding instruction is currently valid; when the bit is 0, it indicates that the corresponding instruction is not currently within a valid window.

[0107] When the instruction dependency checking module responds to a status update indicating the insertion of a new instruction, it first allocates an index value that is currently idle (i.e., the corresponding binary bit is 0) based on the circular queue's internal management state (e.g., the current head pointer position and queue forward direction). Next, the instruction dependency checking module locates the specific position in the circular queue corresponding to this index value and sets the value of the binary bit stored at that position to 1, recording the "valid" state of the new instruction in the circular queue's bitmap, thereby updating the set of currently valid instructions represented by the entire queue. Finally, the mapping between the original identifier of this new instruction (e.g., its program counter value) and the index value just allocated by the circular queue is constructed and stored for subsequent lookups.

[0108] Figure 3 A schematic diagram of a circular queue structure according to an embodiment of this disclosure is shown. The above-described operation based on direct index addressing and bit setting is extremely efficient in implementation. For example, assuming the circular queue length N is 32 and the free index value allocated to the circular queue is 5, the instruction dependency checking module can directly access the position with index 5 in the queue (in a specific implementation, this is usually represented by the 5th bit of a 32-bit integer variable) and set it to 1 with a single bit manipulation instruction. In this way, the operation of adding a new instruction to the valid set can be completed in constant time, achieving a window state update with O(1) time complexity.

[0109] After the instruction dependency checking module allocates a free index value for the new instruction through a circular queue and sets the corresponding bit in the first binary bit set to 1, the mapping relationship can be constructed.

[0110] Specifically, the instruction dependency checking module internally maintains a data structure for efficiently storing and querying the correspondence between instruction identifiers and index values. Since the instruction identifier is a program counter value, its bit width may be large (e.g., 64 bits), while the internal index space is a small range of integers from 0 to N-1. To achieve fast lookup from a large key-value pair to a small index, a hash table-based mapping structure can be used. This process uses the program counter value of the new instruction as the hash key and the index value allocated by the circular queue as the associated value. This key-value pair is inserted into the hash table, thereby establishing and persistently storing a deterministic mapping from that specific program counter value to its internally used index value.

[0111] The hash table data structure is configured to support lookup and insertion operations with an average time complexity of approximately O(1). Its core purpose is that when subsequent requests for status updates involving existing instructions (such as deleting instructions or adding direct dependencies) or dependency queries are received, the instruction dependency checking module can quickly and directly obtain the internal index value corresponding to a given program counter value by performing a hash lookup on this hash table. This method avoids the storage waste caused by allocating excessively large arrays to accommodate sparse, large address spaces, and also eliminates the overhead of linear traversal queries.

[0112] In this embodiment, a first binary bit set is implemented based on a circular queue of length N. An efficient and orderly instruction identification management and state maintenance mechanism is achieved by allocating free index values ​​and establishing a mapping between program counter values ​​and index values ​​in response to the state update information of inserted new instructions. By directly mapping the state changes of the instruction window to the bit operations of the circular queue, the state update operation achieves constant-time complexity. Simultaneously, by maintaining the mapping relationship between program counter values ​​and internal index values, the intuitiveness of the external interface (using program counter values) is preserved, while internally, compact data representation and fast access are achieved. This effectively reduces the dependence on the original instruction address, improves the independence of the module and data processing efficiency, and provides a stable and efficient foundation for subsequent bit operation maintenance and querying of dependencies.

[0113] In one possible implementation, the circular queue includes three pointers: a head pointer, a tail pointer, and a delay pointer;

[0114] The first pointer points to the position of the binary bit corresponding to the inserted instruction;

[0115] The tail pointer points to the position of the next binary bit that will be marked as invalid;

[0116] The delay pointer points to the starting position of the delay clearing operation.

[0117] To manage the state of the circular queue, three pointers can be introduced: a head pointer, a tail pointer, and a delay pointer. These pointers are used to logically identify different position ranges within the circular queue, in order to collaboratively track and maintain the state of the instruction window.

[0118] The head pointer indicates the position in the circular queue that has been most recently set to active status. When a new instruction is inserted, the corresponding bit in the circular queue based on its mapped index is activated (set to 1), and the head pointer can then move to this new position. Therefore, the head pointer points to the queue position corresponding to the most recently added instruction in the currently active instruction window.

[0119] The tail pointer indicates the next position in the circular queue that will be marked as invalid due to instruction expiration. It points to the next position in the sequence after the earliest instruction that entered the current window. As instructions complete execution and are removed from the window, the tail pointer moves in the direction of the queue's forward movement, signifying that the expiration boundary of the earliest instruction in the instruction window is advancing.

[0120] Delayed pointers can be used to mark the starting boundary of a delayed cleanup operation. In a circular queue, the bits within the range from the position pointed to by the delayed pointer to the position preceding the current tail pointer may represent instructions that are logically expired but whose states have not yet been synchronized and cleared from the relevant data structures (such as dependency bit sets). The existence of delayed pointers allows cleanup operations to be performed in batches with a delay, rather than being processed immediately each time an instruction expires.

[0121] In a concrete example, assume the circular queue length is 32. At a certain moment, the head pointer points to index 15, the tail pointer points to index 8, and the deferred pointer points to index 5. This means the currently valid instruction window roughly covers the interval from index 8 to index 15 (considering the circular queue). The interval from index 5 to index 7 represents expired but not completely cleared instructions. When a new instruction is inserted, causing the head pointer to move to index 16, and this movement causes the head pointer to coincide with the deferred pointer (index 5), a deferred clearing operation is triggered. The instruction dependency checking module clears the records in the interval from index 5 to index 7 from all relevant bit sets, and then sets the deferred pointer to the current tail pointer value (index 8). This mechanism combines multiple sporadic clearing overheads into a single batch operation.

[0122] like Figure 3 The above, Figure 3The diagram illustrates the state of a circular queue of length 32 (index range 0 to 31) at a given moment, visually demonstrating the relative positions of the front, end, and lazy pointers and the corresponding queue intervals. The diagram shows consecutive positions from left to right, with indices ranging from 31 to 0, but it's important to understand that the circular queue is logically connected end-to-end. The direction of queue movement is indicated by the arrows in the diagram.

[0123] In this example, the tail pointer (end) currently points to a higher index (e.g., index 30), the lazy pointer (lazy_end) points to a slightly lower index (e.g., index 27), and the front pointer (front) points to an even lower index (e.g., index 2). Due to the logical circular nature of the circular queue, the closed interval from the tail pointer (end) along the queue's forward direction (which can be viewed as a leftward loop to the leftmost position 31 and then back to the rightmost position 1) until the front pointer's position represents the currently valid instruction window. All positions within this interval have their binary bits set to 1, indicating that the instructions corresponding to these indices are currently valid.

[0124] The range from the lazy pointer (lazy_end) to the position preceding the tail pointer (end) represents instructions that have been marked as expired (i.e., their instructions have been moved out of the window logic and the tail pointer has moved), but whose corresponding bit states and associated dependency data have not yet been physically cleared. The lazy pointer marks the starting point of the accumulated operations to be cleared.

[0125] The front pointer points to the most recently activated position (index 2). To its left, the range of indices 3 to 26, logically belongs to the available free area or the area that has not yet been used by the current window cycle.

[0126] In this embodiment, an efficient state management mechanism is formed by setting a head pointer, a tail pointer, and a delayed pointer in a circular queue. The head pointer points to the position of the most recently activated bit, the tail pointer points to the position of the next bit to be marked as invalid, and the delayed pointer points to the starting position of the delayed clearing operation. The movement of the head and tail pointers can track the head and tail boundaries of the instruction window in real time with low overhead. The introduction of the delayed pointer and delayed clearing strategy allows for batch and asynchronous execution of the cleanup of expired instruction-related data, avoiding triggering a traversal cleanup operation every time a single instruction expires, thus amortizing the average time complexity of the cleanup operation to a constant level. This design effectively balances the real-time performance and operational efficiency of state maintenance, providing a foundation for the continuous and efficient maintenance of instruction dependencies.

[0127] In one possible implementation, the method further includes:

[0128] When inserting a new instruction, after setting the binary bit to 1, the head pointer is moved one bit in the forward direction of the queue to the newly set position of 1;

[0129] In response to the status update information indicating the deletion of expired instructions, the tail pointer is moved one position in the forward direction of the queue to mark the instruction as expired.

[0130] When the instruction dependency checking module responds to an indication to insert a new instruction's status update information, its maintenance operations may include: finding the corresponding position in the circular queue based on the index value obtained from the new instruction mapping, setting the binary bit of that position to 1, and marking the instruction as valid. Then, after setting the bit, the instruction dependency checking module moves the head pointer one position in the queue's forward direction, making it point to this newly set position. Through this movement, the head pointer is updated to always point to the position of the latest active instruction, thereby dynamically identifying the logical header of the valid instruction window.

[0131] On the other hand, when the instruction dependency checking module responds to an instruction to delete expired instructions' status update information, it can perform another pointer update operation. This module can move the tail pointer one position in the queue's forward direction. That is, the instruction previously represented by the position pointed to by the tail pointer (i.e., the oldest instruction in the current window) is now marked as expired. The new position pointed to by the tail pointer becomes the location of the next instruction waiting to be marked as expired. It should be noted that the binary bits corresponding to the original position of the tail pointer may not be immediately cleared to zero; their physical state clearing may be done in conjunction with a delayed pointer mechanism in subsequent batch operations. The movement of the tail pointer mainly serves to logically confirm that the instruction's expiration boundary has been advanced.

[0132] In a specific example, suppose the circular queue length is 32, the current front pointer points to index 5, and the end pointer points to index 10. When a new instruction is mapped to index 6, the instruction dependency check module sets the corresponding bit at index 6 to 1, and then moves the front pointer from index 5 to index 6. At this point, the latest boundary of the valid window is updated to index 6. Subsequently, if a request to delete the oldest instruction is received, the module moves the end pointer from index 10 to index 11. This indicates that the instruction corresponding to index 10 has expired, and the logical end boundary of the valid window is updated to index 11. By combining pointer movement with bit setting, the window state update can be completed in constant time.

[0133] In this embodiment, an efficient and low-overhead instruction window state maintenance mechanism is implemented by moving the head pointer one bit forward in the queue direction to the newly set position after setting the binary bit to 1 when inserting a new instruction, and by moving the tail pointer one bit forward in the queue direction to mark the instruction as expired in response to an indication to delete expired instruction status update information. The movement operations of the head and tail pointers themselves involve only simple pointer arithmetic, with a time complexity of constant order, which makes tracking the dynamic changes of the head and tail of the window extremely fast. This design is directly related to the update of the bit set, ensuring the synchronization between the logical boundaries of the data structure and the changes in the physical state, thus providing a solid foundation for the accurate update of the dependent bit set.

[0134] In one possible implementation, the method further includes:

[0135] When the first pointer moves to coincide with the delayed pointer, all binary bits in the circular queue within the range indicated by the delayed pointer to the bit before the tail pointer are set to 0, and the delayed pointer is updated to the tail pointer.

[0136] As the instruction dependency checking module continuously processes the insertion and deletion of instructions, the first pointer moves continuously with the addition of new instructions, while the delayed pointer remains stationary until a specific condition is met. Here, the situation where the first pointer moves to coincide with the delayed pointer can mean that, as the first pointer moves along the queue's forward direction, its current position becomes the same as the position currently pointed to by the delayed pointer. This indicates that the physical storage location corresponding to the accumulated expired instruction interval defined from the delayed pointer to the position before the tail pointer is about to be overwritten or reused by newly entering instructions. At this point, the instruction dependency checking module needs to perform a synchronization cleanup to release the state associated with these positions.

[0137] When the coincidence condition is met, the instruction dependency checking module can perform a batch cleanup operation. Specifically, this module determines a contiguous range that needs to be cleaned up, starting from the position currently pointed to by the delay pointer and ending at the position before the position pointed to by the tail pointer (in the logical order of the circular queue). The module sets the binary bit corresponding to each position in the circular queue that falls within this range to 0. This operation clears the residual state of all expired instructions in the valid bit set, allowing these positions to be reused by subsequent new instructions.

[0138] After completing the bit clearing operation, the instruction dependency checking module updates the delay pointer to the position pointed to by the current tail pointer, so that the delay pointer moves to a new starting point and prepares for the next round of delay clearing cycle.

[0139] In a specific example, suppose the circular queue is 32 bytes long, the current tail pointer (end) points to index 10, the lazy pointer (lazy_end) points to index 5, and the front pointer (front) is moving from index 4 to index 5. When a new instruction is inserted, causing the front pointer to move to index 5, the front pointer coincides with the lazy pointer. At this point, the instruction dependency checking module performs a cleanup operation: it sets all bits in the interval from the lazy pointer (index 5) to the position before the tail pointer (index 9) (i.e., indices 5, 6, 7, 8, and 9) to 0. Subsequently, the module updates the lazy pointer to the current tail pointer value (index 10). In this way, the lazy pointer is synchronized to a new, later starting position, and the previously accumulated expired state has been cleared in batches.

[0140] In this embodiment, when the first pointer coincides with the delayed pointer, all binary bits within the range indicated by the delayed pointer to the previous bit in the circular queue are set to 0, and the delayed pointer is updated to the tail pointer. This achieves an efficient and low-overhead delayed state cleanup mechanism, decoupling the physical cleanup operation from the logical expiration flag, allowing the cleanup operation to be executed in batches. This combines multiple scattered memory accesses or bit operations into a single centralized operation. This significantly reduces the average time overhead caused by maintaining the instruction window state, especially in scenarios with high-frequency instruction insertion and deletion, effectively avoiding performance fluctuations caused by frequent cleanup. Simultaneously, delayed cleanup ensures that invalid states are not retained in the data structure for extended periods, maintaining the simplicity and accuracy of the bit set upon which dependency calculations are based, thereby improving the overall throughput and response efficiency of the instruction dependency checking module.

[0141] In one possible implementation, the dependency bit set includes a dependency bit set maintained for each index value, each dependency bit set being an N-bit second binary bit set, where a 1 in the j-th bit indicates that the instruction corresponding to the index value depends on the instruction corresponding to the index value j.

[0142] The step of updating the dependency bit set corresponding to the index value through bitwise operations based on the instruction window state update information and the first binary bit set includes:

[0143] When the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, the bitwise OR operation is performed between the bitwise dependent bit set corresponding to index value b and the bitwise dependent bit set corresponding to index value a, and the result is used as the updated bitwise dependent bit set of index value a.

[0144] Perform a bitwise AND operation between the updated set of dependency bits and the first set of binary bits, and remove the dependency records of instructions that are no longer in the valid window.

[0145] Where j, a, and b are all integers from 0 to N-1.

[0146] The dependency bit set may include a separate data unit maintained for each possible index value in the circular queue, called the dependency bit set. Each such dependency bit set can be a binary bit sequence of fixed length N, i.e., the second binary bit set. In this bit sequence, the position of each binary bit can be associated with a specific index value; for example, the state of the j-th bit (assuming the least significant bit is bit 0) can be used to characterize whether the instruction indicated by the index value corresponding to the dependency bit set depends on another instruction indicated by index value j. If the bit is 1, it indicates that a dependency exists; if it is 0, it indicates that no dependency exists. In this way, all direct and indirect dependencies between instructions can be encoded into a fixed-length bitmap, allowing the querying and updating of the dependency network to be transformed into efficient bit operations.

[0147] When the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, the instruction dependency checking module can perform a bitwise-based merging operation. First, it obtains the current dependency bit set corresponding to index value b, which already contains the dependency information of all other instructions reachable by index value b. Simultaneously, it obtains the current dependency bit set corresponding to index value a. Then, the instruction dependency checking module performs a bitwise OR operation on these two bit sets. The bitwise OR operation generates a new bit set where any bit that is 1 in the dependency bit set of index value b, or 1 in the dependency bit set of index value a, will be 1 in the result bit set. After the operation, the instruction dependency checking module writes this result bit set back as the updated dependency bit set for index value a.

[0148] This update process leverages the parallelism and efficiency of bitwise operations to achieve transitive merging of dependencies. Since the dependency bit set of index b has been pre-computed and contains all direct and indirect dependencies of b, it is merged into the dependency bit set of index a through a bitwise OR operation. Thus, the dependency bit set of index a integrates all instruction dependencies reachable through b in one go. This method avoids the need for recursive traversal of the dependency graph or recompiling the transitive closure each time a new direct dependency is added; instead, incremental updates of dependencies can be completed with a single bitwise operation.

[0149] In a specific example, assume the instruction window index range N=32, and the instruction dependency check module receives a status update indicating that the instruction at index 5 directly depends on the instruction at index 3. The module first reads the dependency bit set for index 3, assuming its 32-bit value is 0x0000000C (binary...001100), indicating that index 3 depends on both index 2 and index 3 (positions 2 and 3 from right to left are 1, initial bit 0). Simultaneously, the module reads the dependency bit set for index 5, assuming its current value is 0x00000000 (no dependency yet). Next, the module performs a bitwise OR operation on these two values: 0x0000000C OR 0x00000000 = 0x0000000C. Then, the module writes the result, 0x0000000C, back as the new dependency bit set for index 5. Thus, the set of dependent bits for index 5 now indicates that it depends on index 2 and index 3, where the dependency on index 3 is direct, and the dependency on index 2 is an indirect dependency passed through index 3. Through this operation, dependencies are rapidly propagated and recorded.

[0150] In this embodiment, a highly efficient and accurate dependency propagation and update mechanism is achieved by designing the dependency bit set to maintain an N-bit dependency bit set for each index value, where the j-th bit being 1 indicates that the instruction corresponding to the index value depends on the instruction corresponding to index value j. When the state update information indicates a direct dependency, the relevant dependency bit set is updated by performing a bitwise OR operation. This bitwise operation-based merging operation directly integrates dependency information at the binary bit level, and its computational complexity depends only on the length of the bit set (usually constant), thus avoiding the recursive or iterative overhead that may be caused by traditional graph traversal algorithms. It ensures that when a new direct dependency is added, all its implicit indirect dependencies can be merged into the dependency record of the target instruction immediately and completely, so that the dependency bit set always maintains the latest transitive closure state. This provides a real-time and accurate bitmap index for subsequent dependency queries, significantly improving the efficiency and response speed of dependency maintenance, while reducing computational resource consumption.

[0151] After updating the specific instruction dependency bit set (e.g., merging new dependencies through bitwise operations), the instruction dependency checking module can perform a bitwise AND operation between the updated dependency bit set and the first binary bit set. The first binary bit set is a bitmap that is always synchronized with the currently active instruction window, where a bit that is 1 indicates that the corresponding instruction index is currently active. The rules for the bitwise AND operation are: the bit in the result bit set is 1 only if both input bit sets have bits of 1 at the same position; otherwise, it is 0.

[0152] For each bit in the dependency bit set, if the instruction index corresponding to that bit is also marked as valid (bit value 1) in the current first binary bit set, then the dependency record is retained in the operation result (result bit is 1). Conversely, if the instruction index corresponding to that bit has been marked as invalid (bit value 0) in the current first binary bit set, for example, if the instruction has expired and been removed from the window, then this dependency record will be removed from the operation result (result bit is cleared). After the operation is completed, the instruction dependency checking module can write back the obtained, filtered result as the final dependency bit set maintained by the instruction index.

[0153] As commands are constantly added and removed from the command window, a command's dependency bit set may gradually accumulate references to outdated commands. By periodically (e.g., after each dependency bit set update) performing a bitwise AND operation with the latest valid command bitmap, these invalid references can be removed in real time, ensuring that each dependency bit set always records only dependencies on valid commands within the current window. This guarantees that any subsequent queries or calculations based on the dependency bit set are grounded in accurate data.

[0154] In a specific example, suppose the updated dependency bit set for instruction index 5 is 0x0000007F (all lower 7 bits are 1), indicating that it depends on instructions at indices 0 to 6. Simultaneously, suppose the current first bit set (valid instruction set) is 0x0000001F (all lower 5 bits are 1), indicating that only instructions at indices 0 to 4 are currently valid, while instructions at indices 5 and 6 are expired. The instruction dependency checking module performs a bitwise AND operation on these two values: 0x0000007F AND 0x0000001F = 0x0000001F. The resulting value 0x0000001F indicates that, in the dependency record for index 5, only dependencies on valid indices 0 to 4 are retained, while the dependency records for expired indices 5 and 6 have been successfully removed.

[0155] In this embodiment, invalid entries in the dependency record are removed in real time by performing a bitwise AND operation between the updated dependency bit set and the first binary bit set. This ensures that the information stored in the dependency bit set is always strictly limited to the current valid instruction window, avoiding data redundancy and logical errors that might result from retaining dependency references to expired instructions. This real-time cleanup mechanism relies on efficient bitwise operations, with a constant-time complexity, and does not introduce significant performance overhead. It not only reduces unnecessary storage usage but, more importantly, provides accurate basic data for dependency queries (e.g., determining whether instructions are dependent), thereby improving the overall reliability, accuracy, and processing efficiency of instruction dependency checks.

[0156] In one possible implementation, the dependency bit set further includes a direct dependency bit set maintained for each index value, each of the direct dependency bit sets being an N-bit third binary bit set, where the k-th bit being 1 indicates that the instruction corresponding to index value k directly depends on the instruction corresponding to that index value; the method further includes:

[0157] If the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, then the bit corresponding to index value a in the set of directly dependent bits of index value b is set to 1.

[0158] In addition to maintaining a set of dependency bits that indicates "who" an instruction depends on, the dependency bit set can also maintain a data structure that indicates "who directly depends on" an instruction, namely, a set of direct dependency bits.

[0159] A separate set of direct dependency bits can be maintained for each index value in the circular queue; for ease of description, this is represented as a third set of binary bits. Similar to the dependency bit set, each set of direct dependency bits is also a binary bit sequence of length N. In this bit sequence, the state of the k-th bit (counting from bit 0) means that if this bit is set to 1, it indicates that the instruction corresponding to index value k directly depends on the instruction corresponding to the index value associated with this set of direct dependency bits. This reverse recording method allows for quick identification of which instructions directly depend on the dependent instruction from its perspective.

[0160] When the instruction dependency checking module processes state update information, if the information explicitly indicates a new direct dependency, such as specifying that "the instruction corresponding to index value a directly depends on the instruction corresponding to index value b," then in addition to updating the (forward) dependency bit set mentioned above, the corresponding direct dependency bit set will also be updated synchronously. The specific update operation may include: the instruction dependency checking module locates the direct dependency bit set corresponding to index value b, then finds the binary bit (i.e., bit a) corresponding to index value a in that direct dependency bit set, and sets the value of that bit to 1. This operation explicitly adds index value a to the "dependency list" of index value b, accurately recording this newly established direct dependency edge from a to b.

[0161] Maintaining inverted indexes of direct dependencies facilitates the tracing of dependencies. The forward dependency bit set (the second set of bits) represents which instructions can be reached by the current instruction, while the inverted direct dependency bit set (the third set of bits) represents which instructions can directly reach the current instruction. Together, they form a complete, bidirectional dependency bitmap. For example, when querying a dependency path or analyzing a dependency chain, the direct dependency bit set can provide crucial "reverse connection" information, enabling tracing back from the target instruction to its direct predecessor node.

[0162] In a specific example, assuming N=32, the instruction dependency checking module receives a status update indicating that the instruction at index 5 directly depends on the instruction at index 2. After updating the positive dependency, the module simultaneously updates the direct dependency bit set, that is, it accesses the direct dependency bit set corresponding to index 2. Assume this 32-bit set originally had a value of 0x00000000. The module sets bit 5 (starting from bit 0) to 1. If represented as a 32-bit integer, setting bit 5 to 1 is equivalent to performing a bitwise OR operation between the value and (1 << 5) (i.e., 0x00000020). After the update, the direct dependency bit set value for index 2 becomes 0x00000020. This result indicates that currently, only the instruction at index 5 directly depends on the instruction corresponding to index 2.

[0163] In this embodiment, a direct dependency bit set is maintained for each index value, where the k-th bit being 1 indicates that the instruction corresponding to index value k directly depends on the instruction corresponding to that index value. When the status update information indicates a direct dependency, the bit in the relevant direct dependency bit set for the corresponding index value is set to 1. This maintains the reverse link information for each edge in the dependency graph. This reverse information complements the forward dependency bit set, greatly enhancing the expressive power and query flexibility of dependency data. Especially when path extraction, dependency chain analysis, or complex debugging is required, the direct dependency bit set provides a direct basis for reverse tracing from the dependent party. This allows such operations to efficiently locate the direct predecessor without traversing the entire forward dependency graph, thus significantly expanding the functional scope of the instruction dependency checking module and improving its ability and efficiency in handling complex query scenarios.

[0164] In one possible implementation, the method further includes: in response to a dependency query request from an upstream processing module, determining the dependency relationship between the first instruction and the second instruction based on the dependency bit set.

[0165] A dependency query request is used to check whether a dependency exists between two specified instructions within the current instruction window. The request can contain two instruction identifiers, such as the program counter values ​​of the first instruction and the second instruction, to specify the instruction pair to be checked.

[0166] Based on the maintained set of dependency bits, the instruction dependency checking module can perform a judgment operation. Specifically, the instruction dependency checking module can first map the two instruction identifiers contained in the query request to corresponding index values, such as a first index value s and a second index value t. Subsequently, the instruction dependency checking module can obtain the set of dependency bits associated with the first index value s. This set of bits is a binary sequence, where the state of each bit represents whether the instruction corresponding to the index value s depends on the instruction indicated by the index value corresponding to that bit.

[0167] The logic for the judgment can be implemented by checking the state of a specific bit. The instruction dependency checking module can check whether the bit corresponding to the second index value t (i.e., the t-th bit) in the dependency relationship bit set corresponding to the first instruction is set to 1. If the value of this bit is 1, it can be determined that the instruction corresponding to the first index value s depends on the instruction corresponding to the second index value t, and thus the first instruction depends on the second instruction. Conversely, if the value of this bit is 0, it can be determined that the first instruction does not depend on the second instruction.

[0168] In a specific example, the upstream processing module might need to query the dependency between two instructions with program counter values ​​of 0x2000 and 0x2080. The instruction dependency checking module uses an internal mapping table to find the first index value s corresponding to 0x2000, which is 8, and the second index value t corresponding to 0x2080, which is 15. Next, the instruction dependency checking module reads the set of dependency bits corresponding to index value 8 (e.g., a 32-bit binary number). By checking whether the 15th bit (counting from bit 0) of this integer is 1, the existence of a dependency can be directly determined.

[0169] In this embodiment of the disclosure, dependency query is performed based on a pre-calculated bit set, eliminating the need for real-time graph traversal or path search during the query, thereby enabling efficient dependency judgment with constant time complexity.

[0170] In one possible implementation, determining the dependency relationship between the first instruction and the second instruction based on the dependency bit set includes:

[0171] Obtain the first index value s corresponding to the first instruction and the second index value t corresponding to the second instruction;

[0172] Check if the t-th bit in the dependency bit set of the first index value s is 1;

[0173] If the value is 1, then the first instruction is determined to depend on the second instruction.

[0174] When the instruction dependency checking module responds to a dependency query request from the upstream, it first performs index transformation, extracts the original identifiers (such as their program counter values) of the first instruction and the second instruction from the request, and obtains their corresponding numerical indexes, namely the first index value s and the second index value t, respectively by querying the internally maintained mapping relationship.

[0175] After obtaining the index value, the instruction dependency checking module performs a status check operation, reading the dependency bit set (i.e., the second binary bit set mentioned above) associated with the first index value s. This bit set is an N-bit binary sequence that encodes the dependency information of all other instructions reachable from the index value s. Then, the value of the specific binary bit (i.e., the t-th bit) corresponding to the second index value t in this bit sequence is checked to verify whether there is an encoded record of a reachable path from node s to node t in the pre-calculated and maintained dependency network.

[0176] The judgment logic is directly determined by the state of the binary bit. If the check finds that the t-th bit in the dependency bit set is 1, it indicates that in the model recorded in the dependency bit set, the instruction corresponding to index value s depends on the instruction corresponding to index value t. Therefore, the instruction dependency checking module can determine that the first instruction in the original query depends on the second instruction. Conversely, if the t-th bit is 0, it indicates that there is no such dependency, and the first instruction does not depend on the second instruction.

[0177] Thus, the problem of "graph reachability query," which typically requires traversal and computation, is transformed into a direct "memory read-bit check" operation. Its effectiveness depends entirely on the continuous and correct maintenance of the dependency bit set in the preceding steps. When a new direct dependency is added, all indirect dependencies are integrated into the relevant dependency bit set in real time through transitive merging of bit operations. Therefore, at any given time, the j-th bit of a dependency bit set is 1 if and only if the corresponding instruction depends on the instruction at index j (whether directly or indirectly). This eliminates the need for any real-time computation or traversal during the query; only a specific bit of a pre-computed result needs to be verified, resulting in a time complexity of O(1).

[0178] In a specific example, suppose a query request inquires about the dependency between two instructions corresponding to program counter values ​​0x1000 and 0x1040. The instruction dependency checking module first maps 0x1000 to a first index value s=8 and 0x1040 to a second index value t=15. Then, it reads the dependency bit set corresponding to index value 8, assuming it's a 32-bit integer, its binary representation is "... 0000 1000 0000 0000 0000" (only the 15th bit is 1). The instruction dependency checking module checks the 15th bit of this integer (counting from bit 0) and finds it to be 1. Therefore, it determines that the instruction corresponding to program counter value 0x1000 depends on the instruction corresponding to 0x1040. The entire judgment process does not involve any loops or recursion, only two mapping table lookups, one memory read, and one bit test, and can be completed in a very short time.

[0179] In this embodiment, the dependency relationship is determined by obtaining the index values ​​s and t corresponding to the first and second instructions, and checking whether the t-th bit in the dependency bit set of the first index value s is 1. This simplifies the complex dependency graph path search problem into a bitmap index lookup operation with constant time complexity. Its execution speed does not significantly change with the increase in instruction window size or dependency complexity, providing a stable and extremely fast query response. This fundamentally solves the performance bottleneck problem of traditional graph traversal-based query methods in simulation environments with high real-time requirements, enabling the instruction dependency checking module to support high-frequency, low-latency instruction scheduling and verification needs, significantly improving the execution efficiency of the entire pipeline simulation process.

[0180] In one possible implementation, the method further includes:

[0181] In response to a dependency path query request for the first instruction to the second instruction, a fourth binary bit set is initialized, wherein the bit corresponding to the first index value s of the first instruction is set to 1;

[0182] Based on the set of dependent bits of the first instruction, the set of direct dependent bits of each index value, and the set of the fourth binary bits, the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction is determined.

[0183] This process can be triggered by a dependency path query request, which can be initiated by the upper-level debugging module to query all intermediate instruction nodes on a reachable path from the first instruction to the second instruction.

[0184] In response to this request, the path extraction module within the instruction dependency check module can perform path extraction initialization. The module prepares an auxiliary data structure, referred to for ease of description as the fourth bit set. This set is also a sequence of N bits used to dynamically track instruction nodes that have been discovered and are reachable from the first instruction during the path search process. The initialization operation involves the path extraction module setting the bit in the fourth bit set corresponding to the first index value s of the first instruction to 1. This signifies that the starting point of the path search (the first instruction s) has been visited and is included in the current "reachable domain."

[0185] After initialization, the core step of path extraction is to iteratively expand the reachable domain while simultaneously recording path information. The path extraction module performs calculations based on three sets of key data: the first set of dependent bits (indicating all instructions reachable from index s), the second set of direct dependent bits for each index value (indicating which instructions directly reach each node), and a dynamically updated fourth set of binary bits (the set of currently found reachable nodes). By analyzing the relationships between these bit sets, the module can progressively determine the nodes on the path from index s to index t.

[0186] In this embodiment, after determining the existence of dependencies, a path query request is responded to, a fourth binary bit set is initialized, and path nodes are determined based on the dependency bit set, the direct dependency bit set, and the fourth set. Thus, using the maintained forward and reverse dependency bitmaps, bitwise operations are used instead of traditional graph traversal algorithms to gradually deduce and verify the path. This avoids searching the entire graph during queries; the computational cost is mainly related to the length of the path itself, rather than being directly linked to the total size of the command window or the overall complexity of the dependency network. This not only makes the path extraction operation itself highly efficient, but more importantly, it provides powerful visual debugging support for the software development and debugging phases, enabling rapid location of specific dependency transmission chains, thereby improving the efficiency of problem diagnosis and the insight into the entire simulated development process.

[0187] In one possible implementation, determining the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction includes:

[0188] Following the order from the tail pointer to the position before the head pointer in the circular queue, traverse each bit in the dependency bit set of the first index value s that is 1, and perform the following steps for the current index value:

[0189] Perform a bitwise AND operation between the set of direct dependent bits of the current index value and the fourth set of binary bits to obtain the set of preceding binary bits;

[0190] Determine a predecessor index value from the predecessor binary bit set;

[0191] The path information of the current index value is determined based on the predecessor index value and stored in the path record;

[0192] Set the bit corresponding to the current index value to 1 to update the fourth binary bit set;

[0193] Check if the current index value is equal to the second index value t. If yes, stop traversing; otherwise, continue traversing to the next index.

[0194] After stopping the traversal, the path information corresponding to the second index value t is obtained from the path record and output.

[0195] During path determination, iterative traversal can be performed in a specific order, namely, according to the order in the circular queue from the tail pointer to the position before the head pointer. This order stipulates that the traversal should start from the position pointed to by the tail pointer in the circular queue, and proceed sequentially along the direction of queue movement until the position before the head pointer is reached. This order usually corresponds to the time order in which instructions entered the window, traversing from the earliest (oldest) instruction to the most recently added instruction.

[0196] The path extraction module checks the binary bits that are 1 in the dependency bit set of the first index value s one by one in this order. Each bit that is 1 corresponds to a candidate node index value that can be reached from s, and this is recorded as the current index value.

[0197] For each current index value encountered during traversal, the path extraction module performs an iterative operation to determine its position in the path and add it to the path record:

[0198] First, a predecessor node lookup is performed by performing a bitwise AND operation between the set of direct dependencies of the current index value and the set of the fourth binary bits at the current moment. The set of direct dependencies indicates all instruction indices that directly depend on the current index value. The set of the fourth binary bits dynamically maintains the set of instruction indices that have been confirmed to be reachable from the starting point s. The result of the bitwise AND operation generates a predecessor binary bit set, where bits that are 1 represent instruction indices that are both directly dependent on the current index value and belong to the currently known reachable set. These nodes are potential bridges connecting the first index value s and the current index value.

[0199] In other words, the predecessor node here is the instruction node directly preceding the current node (current index value) on the dependency path being searched, and with which it has a direct dependency. Specifically, when constructing a dependency path from the starting instruction s to the target instruction t, for an intermediate instruction node on the path (denoted as the current node), its predecessor node is the instruction node that is immediately adjacent to the current node in the path sequence and which the current node directly depends on. In other words, there is a direct dependency edge between the predecessor node and the current node, and through the predecessor node, it can connect to an earlier node, ultimately tracing back to the starting point s.

[0200] Next, a specific predecessor index value is determined from the set of predecessor binary bits. Several selection strategies exist, such as choosing the smallest index value or the largest index value (i.e., the index corresponding to the highest bit 1). The selected predecessor index value will be considered the direct predecessor node of the current node's current index value on the path constructed in this operation.

[0201] Then, path information is recorded, and based on the determined predecessor index value, a path connection relationship is established from the predecessor index value to the current index value. This relationship is stored in a dedicated path record data structure. The path record can be an N-bit binary array, where each index position stores the path information to that index (e.g., the index of its predecessor node).

[0202] Subsequently, the binary bit corresponding to the current index value in the fourth binary bit set is set to 1, and the current index value is formally included in the set of confirmed reachable nodes starting from the starting point s, so that the current index value can become a potential predecessor of other nodes in subsequent traversals.

[0203] Finally, a termination condition check is performed to determine if the current index value is equal to the target index value t. If they are equal, it means that the path to the target node has been successfully found and constructed, and the entire traversal process can stop. If they are not equal, the process continues to traverse the next 1 bit in the dependency bit set according to the predetermined order.

[0204] When the traversal stops upon finding the target or after traversing all relevant bits, the path extraction module extracts the path information corresponding to the second index value t from the maintained path records. This information is typically represented as a linked list or sequence, showing the nodes traversed along the entire path from s to t. Finally, this path information is output as a response to the dependent path query request.

[0205] In this embodiment, the dependency bit set is traversed in a circular queue from the tail pointer to the position before the head pointer. For each reachable node, standardized predecessor probing, selection, recording, and set updating are performed until the target node is found. Thus, by utilizing the temporal order of instructions within the window (oldest to newest) to guide the traversal, the path construction process becomes deterministic and predictable, often finding a dependency chain that conforms to temporal logic. Combined with efficient bitwise operations for predecessor filtering, the computational complexity of path search is effectively limited to a linear range equal to the path length, avoiding the overhead of full graph traversal. Its time complexity is the same as the number of nodes on the path. This not only ensures high performance in path extraction but also provides a clear and easily understood instruction dependency propagation trajectory for the debugging process, significantly enhancing the ability to diagnose and analyze problems in a simulated environment.

[0206] In one possible implementation, the method further includes:

[0207] Record and output key status information during the instruction dependency maintenance and query process. The key status information includes at least one of the following: program counter values ​​that are inserted or deleted, newly added direct dependencies, query requests and results, and extracted dependency paths.

[0208] Key state information can be data points that characterize the core operations and state transitions during instruction dependency maintenance and querying. This information is not essential to the core algorithm logic, but it is crucial for understanding module behavior, verifying its correctness, and troubleshooting. In this implementation, the logging module within the instruction dependency checking module can achieve this function, selectively recording and outputting various types of key state information.

[0209] This information can include, but is not limited to, the following: First, information about changes in the command window's members, i.e., the program counter values ​​for insertions or deletions, which records which specific commands were added to or removed from the active window; second, information about updates to the dependency graph, i.e., newly added direct dependencies, which records the newly established direct dependency edges between two commands; third, query interaction information, including query requests and results, which records what dependency questions the upstream module posed and the module's answer (yes or no); and fourth, deeper derivation information, i.e., the extracted dependency paths, where the log module can output the specific command sequence traversed from the starting point to the destination during path queries.

[0210] While the instruction dependency checking module executes its core logic, the logging module can simultaneously perform recording operations. For example, when the instruction dependency checking module processes the status update information of an inserted instruction, the logging module can record the program counter value of that instruction as an event in the log buffer or send it directly to the output interface. Similarly, when the instruction dependency checking module processes an update that adds a direct dependency, the logging module can record the identifiers of the two dependent instructions. For each dependency query, whether it is a simple judgment or path extraction, the logging module can pair and record the input (the identifiers of the two instructions) and the output (whether the dependency exists or the specific path). This information can be output in various ways, such as writing to a circular buffer in memory, outputting to a standard debug interface, or sending it to upper-layer monitoring tools via the event bus.

[0211] In this embodiment, by recording and outputting key state information during the instruction dependency query process, including inserted or deleted program counter values, newly added direct dependencies, query requests and results, and extracted dependency paths, detailed tracking and debugging support is provided for the operation of the instruction dependency checking module. Without interfering with the efficient execution of the core algorithm, a lightweight logging mechanism significantly enhances the module's observability. This allows software developers to intuitively monitor the dynamic evolution of the instruction window and dependencies, accurately verify the correctness of dependency query results, and quickly locate specific operation sequences and state nodes when problems occur. This not only significantly reduces the difficulty and time cost of integration debugging and performance analysis in complex simulation environments but also improves the maintainability and reliability of the entire system, providing strong support for efficient software and hardware collaborative development and verification.

[0212] Figure 4 A schematic diagram of the structure of an instruction dependency checking module provided according to an embodiment of this disclosure is shown. Figure 4 As shown, this module includes: a mapping module, used to maintain the mapping relationship between instruction identifiers and index values, and to query or store the corresponding index value when an upstream instruction identifier is received; a circular queue, used to manage the index space within a preset range, allocate free index values, and update the first binary bit set representing the currently valid instruction set based on the allocated index values; a dependency set maintenance module, which updates and maintains the dependency bit set through bit operations based on the instruction window state update information and the first binary bit set; a path extraction module, which extracts the specific instruction dependency path based on the dependency bit set in response to a path query request; and a log module, used to record and output key status information during the module's operation. These sub-modules work together to achieve efficient maintenance, querying, and debugging support for instruction dependencies. Their specific working principles can be found in the possible implementations provided in this disclosure, and will not be elaborated here.

[0213] By effectively isolating clearly defined modules (such as mapping modules, circular queues, and dependency set maintenance modules) from internal data structures, a highly cohesive and loosely coupled software architecture is achieved. This significantly improves the reusability and portability of each functional module, as well as the scalability and stability of the overall system.

[0214] Figure 5 A swimlane diagram illustrating the interaction flow of each module in the instruction dependency checking module provided according to an embodiment of this disclosure is shown. Figure 5 As shown, when the upstream graphics processor pipeline sends a new program counter (PC) instruction to the instruction dependency checking module, the circular queue module allocates a free index value based on its internal management state (such as the head pointer), updates the corresponding queue pointer, and sets the binary bit at the corresponding position of the index value to 1 to complete the insertion of the new instruction into the valid window. The mapping module determines the PC value's storage location in its internal mapping table through hash calculation and establishes a mapping relationship between the index value provided by the circular queue and this PC value for storage. The dependency set maintenance module monitors the circular queue's state update and manages the dependency bit set using a delayed update strategy; that is, when the head pointer moves to coincide with the delayed pointer, all binary bits in the circular queue within the range indicated by the delayed pointer to the previous bit of the tail pointer are set to 0. During this process, the path extraction module is not activated. Finally, the log module records key information about this new instruction event, such as the program counter value and the allocated index value, and outputs the log.

[0215] When processing an instruction to delete a program counter value, the upstream graphics processor pipeline issues a delete instruction. The mapping module responds to this request, queries its internally maintained mapping table to obtain the index (denoted as `index`) corresponding to the program counter value to be deleted, and then deletes this mapping record. The circular queue module receives this index (`index`) and obtains the index (`index'`) corresponding to its own maintained tail pointer pointing to the next expected expired instruction. It then performs a consistency check to verify that `index` and `index'` are consistent, ensuring that the deletion order conforms to the instruction window's first-in, first-out (FIFO) management rule. After successful verification, the circular queue module updates its internal pointers accordingly (e.g., moves the tail pointer) to logically mark the instruction as expired. The dependency set maintenance module synchronizes this change and cleans up records related to this index value in the dependency set. During this process, the path extraction module is not activated. Finally, the logging module records the key parameters of this deletion operation, such as the deleted program counter value and its index (`index`), and outputs the corresponding log information.

[0216] The upstream graphics processor pipeline issues a request to add a direct dependency, indicating that program counter value PC_0 directly depends on program counter value PC_1. The mapping module responds to this request, queries its internally maintained mapping relationships, and retrieves the internal index values ​​corresponding to PC_0 and PC_1 respectively. The dependency set maintenance module receives these two index values ​​and performs the core dependency update operation: it performs a bitwise OR operation between the dependency bit set corresponding to index value PC_1 and the dependency bit set corresponding to index value PC_0, and writes the result back as the updated dependency bit set for index value PC_0, thereby passing all existing dependencies of PC_1 (including direct and indirect dependencies) to PC_0. Simultaneously, to support subsequent path queries, this module also sets the bit representing PC_0 to 1 in the direct dependency bit set corresponding to index value PC_1 to record this direct dependency edge. The path extraction module is not activated in this transaction. Finally, the logging module records key information about this operation, such as the two program counter values ​​and their index values ​​involved in the added direct dependency, and outputs the log.

[0217] The upstream graphics processor pipeline issues a dependency query request, specifying that it needs to determine whether the program counter value PC_0 depends on PC_1 and requesting the specific dependency path. The mapping module responds to this request, queries its internally maintained mapping relationships, and obtains the internal index values ​​corresponding to PC_0 and PC_1 respectively.

[0218] The dependency set maintenance module receives these two index values. If the query only needs to determine whether a dependency exists, this module directly checks whether the binary bit representing the index value PC_1 in the dependency bit set corresponding to index value PC_0 is 1, thus returning a "yes" or "no" result in constant time complexity.

[0219] If the query explicitly requests the extraction of a specific dependency path, the path extraction module is activated. This module utilizes the dependency bit set and direct dependency bit set provided by the dependency set maintenance module. Through a series of bitwise operations (such as bitwise AND, finding the most significant bit, etc.), it traces backward in the instruction window from oldest to newest to construct a dependency path from index PC_0 to index PC_1. The time complexity of this process is proportional to the path length.

[0220] Finally, the logging module records key information about this query operation, including the program counter value, the corresponding index value, the query results (whether there are dependencies), and the possible dependency paths that can be extracted, and outputs the log.

[0221] Figure 6 A schematic diagram of the structure of a software simulation platform provided according to an embodiment of this disclosure is shown. Figure 6As shown, the platform adopts a layered architecture design, mainly consisting of two parts: host and virtual device. The host may contain drivers, while the virtual device further integrates key modules such as ESL-based GPU firmware, ESL-based GPU rendering pipeline, and memory management unit (MMU), which together realize full software simulation of GPU hardware behavior.

[0222] Specifically, the host acts as the upper-layer development and runtime environment, providing software developers with a unified interface for programming, debugging, and testing. Developers access the lower-layer virtual devices through driver interfaces provided by the operating system. These virtual devices internally implement high-fidelity simulation of GPU processor behavior based on open-source virtual machine software (QEMU), thereby executing graphics rendering-related instructions and data processing without relying on actual hardware.

[0223] The core functional modules of a GPU include GPU firmware, GPU pipeline, and memory management unit (MMU), all of which are encapsulated as library files and integrated within the virtual device module. During program execution, the host computer transmits rendering instructions to the GPU firmware via drivers and writes graphics data into the emulated memory space managed by the MMU. The GPU pipeline is responsible for receiving and parsing rendering instructions and executing the corresponding graphics calculations and rendering processes.

[0224] The GPU rendering pipeline incorporates a built-in BIT-DAG InstructionDependency Check module. This module dynamically analyzes the dependencies between rendering instructions to ensure the correctness and efficiency of instruction execution. Simultaneously, this module supports the output of front-end runtime logs, providing developers with debugging data and performance analysis information to assist in algorithm optimization and problem localization.

[0225] In summary, this software simulation platform achieves flexible and debuggable software simulation of GPU hardware functions through virtualization and modular design. In particular, the instruction dependency checking module improves the reliability and development efficiency of the simulation process.

[0226] By constructing the aforementioned dedicated simulation verification platform based on a virtual machine and integrating the instruction dependency checking module into the simulated GPU Pipeline, a highly efficient development and testing environment is provided for software developers, which can be used even before the hardware design is completed. This platform incorporates Electronic System-Level (ESL) modeling principles, encapsulating key functions such as dependency querying into independent, clearly defined software modules. This allows software function verification, performance evaluation, and early application development to be carried out in parallel, significantly reducing the waiting time for hardware dependencies and improving the overall project's R&D and iteration efficiency.

[0227] Figure 7 A block diagram of an instruction dependency maintenance apparatus according to an embodiment of the present disclosure is shown, such as Figure 4 As shown, the image processing device 20 includes:

[0228] The index value determination module 21 is used to determine the index value corresponding to the instruction identifier in the status update information in response to the instruction window status update information from the upstream processing module. The index value is used to indicate the corresponding position of the instruction identifier in a first binary bit set, which includes multiple binary bits indicating whether the instruction is valid.

[0229] The dependency set maintenance module 22 is used to update the dependency bit set corresponding to the index value through bit operations based on the instruction window state update information and the first binary bit set. The dependency bit set is used to represent other valid instructions that any valid instruction can reach based on binary bits.

[0230] In one possible implementation, the number of binary bits in the first binary bit set is N, and the index value ranges from 0 to N-1, where N is a constant greater than the maximum length of the instruction window.

[0231] In one possible implementation, the first set of binary bits is implemented based on a circular queue of length N, where each position in the circular queue corresponds to a binary bit, and a value of 1 for the bit indicates that the instruction corresponding to the index value is currently in the valid instruction window;

[0232] The index value determination module is used for:

[0233] In response to the status update information indicating the insertion of a new instruction, an index value of a free binary bit is allocated through the circular queue, and the free binary bit is set to 1;

[0234] Construct a mapping relationship between the program counter value of the new instruction and the allocated index value.

[0235] In one possible implementation, the circular queue includes three pointers: a head pointer, a tail pointer, and a delay pointer;

[0236] The first pointer points to the position of the binary bit corresponding to the most recently inserted instruction;

[0237] The tail pointer points to the position of the next binary bit that will be marked as invalid;

[0238] The delay pointer points to the starting position of the delay clearing operation.

[0239] In one possible implementation, the apparatus further includes a pointer-dependent set maintenance module for:

[0240] When inserting a new instruction, after setting the binary bit to 1, the head pointer is moved one bit in the forward direction of the queue to the newly set position of 1;

[0241] In response to the status update information indicating the deletion of expired instructions, the tail pointer is moved one position in the forward direction of the queue to mark the instruction as expired.

[0242] In one possible implementation, the device further includes a setting module for:

[0243] When the first pointer moves to coincide with the delayed pointer, all binary bits in the circular queue within the range indicated by the delayed pointer to the bit before the tail pointer are set to 0, and the delayed pointer is updated to the tail pointer.

[0244] In one possible implementation, the dependency bit set includes a dependency bit set maintained for each index value, each dependency bit set being an N-bit second binary bit set, where a 1 in the j-th bit indicates that the instruction corresponding to the index value depends on the instruction corresponding to the index value j.

[0245] The dependency set maintenance module is used for:

[0246] When the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, the bitwise OR operation is performed between the bitwise dependent bit set corresponding to index value b and the bitwise dependent bit set corresponding to index value a, and the result is used as the updated bitwise dependent bit set of index value a.

[0247] Perform a bitwise AND operation between the updated set of dependency bits and the first set of binary bits, and remove the dependency records of instructions that are no longer in the valid window.

[0248] In one possible implementation, the dependency bit set further includes a direct dependency bit set maintained for each index value, each direct dependency bit set being an N-bit third binary bit set, where the k-th bit being 1 indicates that the instruction corresponding to index value k directly depends on the instruction corresponding to that index value; the device further includes:

[0249] The direct dependency update module is used to set the bit corresponding to index value a in the direct dependency bit set of index value b to 1 when the state update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b.

[0250] In one possible implementation, the device further includes:

[0251] The dependency query module is used to respond to a dependency query request from the upstream processing module and determine the dependency relationship between the first instruction and the second instruction based on the dependency bit set.

[0252] In one possible implementation, the dependency query module is used to:

[0253] Obtain the first index value s corresponding to the first instruction and the second index value t corresponding to the second instruction;

[0254] Check if the t-th bit in the dependency bit set of the first index value s is 1;

[0255] If the value is 1, then the first instruction is determined to depend on the second instruction.

[0256] In one possible implementation, the apparatus further includes a path extraction module for:

[0257] In response to a dependency path query request for the first instruction to the second instruction, a fourth binary bit set is initialized, wherein the bit corresponding to the first index value s of the first instruction is set to 1;

[0258] Based on the set of dependent bits of the first instruction, the set of direct dependent bits of each index value, and the set of the fourth binary bits, the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction is determined.

[0259] In one possible implementation, the path extraction module is used to:

[0260] Following the order from the tail pointer to the position before the head pointer in the circular queue, traverse each bit in the dependency bit set of the first index value s that is 1, and perform the following steps for the current index value:

[0261] Perform a bitwise AND operation between the set of direct dependent bits of the current index value and the fourth set of binary bits to obtain the set of preceding binary bits;

[0262] Determine a predecessor index value from the predecessor binary bit set;

[0263] The path information of the current index value is determined based on the predecessor index value and stored in the path record;

[0264] Set the bit corresponding to the current index value to 1 to update the fourth binary bit set;

[0265] Check if the current index value is equal to the second index value t. If yes, stop traversing; otherwise, continue traversing to the next index.

[0266] After stopping the traversal, the path information corresponding to the second index value t is obtained from the path record and output.

[0267] In one possible implementation, the device further includes:

[0268] The log module is used to record and output key status information during the instruction dependency maintenance and query process. The key status information includes at least one of the following: program counter values ​​for insertion or deletion, newly added direct dependencies, query requests and results, and extracted dependency paths.

[0269] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0270] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0271] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0272] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0273] Figure 8 This is a block diagram illustrating an apparatus for maintaining instruction dependencies according to an exemplary embodiment. For example, apparatus 1900 may be provided as a server or terminal device. (Refer to...) Figure 8The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0274] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0275] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0276] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0277] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0278] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0279] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0280] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0281] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0282] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0283] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for maintaining instruction dependencies, characterized in that, include: In response to instruction window status update information from the upstream processing module, the index value corresponding to the instruction identifier in the status update information is determined. The index value is used to indicate the corresponding position of the instruction identifier in a first binary bit set, which includes multiple binary bits indicating whether the instruction is valid. Based on the instruction window state update information and the first set of binary bits, the dependency bit set corresponding to the index value is updated through bit operations. The dependency bit set is used to represent other valid instructions that any valid instruction can reach based on binary bits.

2. The method according to claim 1, characterized in that, The number of binary bits in the first binary bit set is N, and the index value ranges from 0 to N-1, where N is a constant greater than the maximum length of the instruction window.

3. The method according to claim 1, characterized in that, The first set of binary bits is implemented based on a circular queue of length N. Each position in the circular queue corresponds to a binary bit. A value of 1 for a bit indicates that the instruction at the corresponding index value is currently in the valid instruction window. Determining the index value corresponding to the instruction identifier in the status update information includes: In response to the status update information indicating the insertion of a new instruction, an index value of a free binary bit is allocated through the circular queue, and the free binary bit is set to 1; Construct a mapping relationship between the program counter value of the new instruction and the allocated index value.

4. The method according to claim 3, characterized in that, The circular queue includes three pointers: a head pointer, a tail pointer, and a delay pointer; The first pointer points to the position of the binary bit corresponding to the most recently inserted instruction; The tail pointer points to the position of the next binary bit that will be marked as invalid; The delay pointer points to the starting position of the delay clearing operation.

5. The method according to claim 4, characterized in that, The method further includes: When inserting a new instruction, after setting the binary bit to 1, the head pointer is moved one bit in the forward direction of the queue to the newly set position of 1; In response to the status update information indicating the deletion of expired instructions, the tail pointer is moved one position in the forward direction of the queue to mark the instruction as expired.

6. The method according to claim 4, characterized in that, The method further includes: When the first pointer moves to coincide with the delayed pointer, all binary bits in the circular queue within the range indicated by the delayed pointer to the bit before the tail pointer are set to 0, and the delayed pointer is updated to the tail pointer.

7. The method according to claim 1, characterized in that, The dependency bit set includes a dependency bit set maintained for each index value. Each dependency bit set is an N-bit second binary bit set, where the j-th bit being 1 indicates that the instruction corresponding to the index value depends on the instruction corresponding to the index value j. The step of updating the dependency bit set corresponding to the index value through bitwise operations based on the instruction window state update information and the first binary bit set includes: When the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, the bitwise OR operation is performed between the bitwise dependent bit set corresponding to index value b and the bitwise dependent bit set corresponding to index value a, and the result is used as the updated bitwise dependent bit set of index value a. Perform a bitwise AND operation between the updated set of dependency bits and the first set of binary bits, and remove the dependency records of instructions that are no longer in the valid window.

8. The method according to claim 1, characterized in that, The dependency bit set also includes a direct dependency bit set maintained for each index value, each direct dependency bit set being an N-bit third binary bit set, where the k-th bit being 1 indicates that the instruction corresponding to index value k directly depends on the instruction corresponding to that index value; the method further includes: If the status update information indicates that the instruction corresponding to index value a directly depends on the instruction corresponding to index value b, then the bit corresponding to index value a in the set of directly dependent bits of index value b is set to 1.

9. The method according to claim 1, characterized in that, The method further includes: In response to a dependency query request from an upstream processing module, the dependency relationship between the first instruction and the second instruction is determined based on the dependency bit set.

10. The method according to claim 9, characterized in that, Determining the dependency relationship between the first instruction and the second instruction based on the dependency bit set includes: Obtain the first index value s corresponding to the first instruction and the second index value t corresponding to the second instruction; Check if the t-th bit in the dependency bit set of the first index value s is 1; If the value is 1, then the first instruction is determined to depend on the second instruction.

11. The method according to claim 1, characterized in that, The method further includes: In response to a dependency path query request for the first instruction to the second instruction, a fourth binary bit set is initialized, wherein the bit corresponding to the first index value s of the first instruction is set to 1; Based on the set of dependent bits of the first instruction, the set of direct dependent bits of each index value, and the set of the fourth binary bits, the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction is determined.

12. The method according to claim 11, characterized in that, Determining the path node from the first index value s corresponding to the first instruction to the second index value t corresponding to the second instruction includes: Following the order from the tail pointer to the position before the head pointer in the circular queue, traverse each bit in the dependency bit set of the first index value s that is 1, and perform the following steps for the current index value: Perform a bitwise AND operation between the set of direct dependent bits of the current index value and the fourth set of binary bits to obtain the set of preceding binary bits; Determine a predecessor index value from the predecessor binary bit set; The path information of the current index value is determined based on the predecessor index value and stored in the path record; Set the bit corresponding to the current index value to 1 to update the fourth binary bit set; Check if the current index value is equal to the second index value t. If yes, stop traversing; otherwise, continue traversing to the next index. After stopping the traversal, the path information corresponding to the second index value t is obtained from the path record and output.

13. The method according to claim 1, characterized in that, The method further includes: Record and output key status information during the instruction dependency maintenance and query process. The key status information includes at least one of the following: program counter values ​​that are inserted or deleted, newly added direct dependencies, query requests and results, and extracted dependency paths.

14. A device for maintaining instruction dependencies, characterized in that, include: An index value determination module is used to determine the index value corresponding to the instruction identifier in the status update information in response to the instruction window status update information from the upstream processing module. The index value is used to indicate the corresponding position of the instruction identifier in a first binary bit set, which includes multiple binary bits indicating whether the instruction is valid. The dependency set maintenance module is used to update the dependency bit set corresponding to the index value through bit operations based on the instruction window state update information and the first binary bit set. The dependency bit set is used to represent other valid instructions that can be reached by any valid instruction based on binary bits.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 13.

16. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 13.

17. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 13.

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