Data mapping table updating method and device, solid state disk and storage medium
By loading multiple target index tables into the solid-state drive at once and utilizing the pre-built index structure, the problem of excessive CPU resource consumption in random write scenarios is solved, achieving efficient data mapping table synchronization and improving system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, the synchronization process of the data mapping table in random write scenarios of solid-state drives (SSDs) leads to excessive CPU resource consumption, especially in DRAM-Less architectures where memory resources are limited, making it difficult to meet the requirements of efficient synchronization.
By loading multiple target index tables into memory at once and using a pre-built index structure to quickly identify whether the target index table to which the mapping entry belongs has been loaded, concurrent update management is achieved, reducing invalid queries and repeated traversals.
It improves the data mapping table synchronization efficiency, reduces CPU resource consumption, and enhances the response speed of the solid-state drive and system performance in address mapping update operations.
Smart Images
Figure CN121807732A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solid-state drive technology, and in particular to a data mapping table update method, apparatus, solid-state drive, and storage medium. Background Technology
[0002] In solid-state drives (SSDs), logical-to-physical address mapping tables (L2P tables) and physical-to-logical address mapping tables (P2L tables) are typically used to manage the mapping relationship between logical addresses and physical addresses. When the host writes data, the controller writes the data to the physical location of the NAND flash memory and records the corresponding logical address information in the P2L table. To ensure mapping consistency, unsynchronized entries in the P2L table need to be periodically updated to the corresponding L2P tables. In existing technologies, this synchronization process is performed by loading the L2P table one by one: after loading one L2P table, all P2L table entries to be updated are traversed, the entries belonging to that table are found and updated, and then the table is flushed and released before processing the next table. This method has significant drawbacks in random write scenarios. Since only one L2P table is processed at a time, the system needs to repeatedly traverse the entire P2L table, resulting in a large amount of CPU resources being consumed by invalid queries, especially during large-scale or full-disk random writes, where performance overhead increases significantly. Furthermore, under the DRAM-Less architecture, memory resources are limited, and frequent loading and unloading further exacerbate the system burden, making it difficult to meet the requirements of efficient synchronization. Summary of the Invention
[0003] In view of this, embodiments of this application provide a data mapping table update method, apparatus, solid-state drive, and storage medium to achieve efficient synchronization of the data mapping table.
[0004] In a first aspect, embodiments of this application provide a data mapping table update method, including: Retrieve multiple physical address to logical address mapping entries to be updated; A set of target index tables to be updated is determined based on each logical address in the mapping entry to be updated, and at least two target index tables are selected from the set of target index tables and loaded into memory; Iterate through all the mapping entries to be updated. For any mapping entry, determine the identifier of the target index table it belongs to based on the corresponding logical address. If the pre-established index structure is queried according to the identifier, when it is determined that the current target index table has been loaded, the physical address information corresponding to the current logical address in the current target index table is updated, and the corresponding mapping entry is marked as synchronized; Repeat the process for the remaining mapping entries to be updated until all of them are marked as synchronized.
[0005] In some embodiments, the step of querying the pre-built index structure based on the identifier, before determining that the current target index table has been loaded, further includes: The index structure is established in the memory; wherein the index structure is a linked list array, the linked list array includes multiple hash slots, each hash slot corresponds to a linked list head node; the identifier of any target index table is determined by a hash function to determine the corresponding hash slot, and is attached to the linked list corresponding to the hash slot.
[0006] In some embodiments, querying the pre-built index structure based on the identifier, after determining that the current target index table has been loaded, includes: Calculate the modulo result of the identifier of the target index table with a preset integer to obtain the corresponding hash index; The hash index is used to locate the corresponding head node of the linked list in the linked list array; Traverse each node in the linked list guided by the head node of the linked list, and compare the target index table identifier recorded in each of the linked list nodes. If there exists an identifier in the linked list node that is the same as the identifier of the current target index table, then it is confirmed that the current target index table has been loaded.
[0007] In some embodiments, determining a set of target index tables to be updated based on each logical address in the mapping entry to be updated includes: Iterate through all the mapping entries to be updated and extract the logical address recorded in each mapping entry; Based on the preset address mapping granularity, the identifier of the target index table to which each logical address belongs is calculated, and the current identifier is deduplicated to form the target index table set.
[0008] In some embodiments, selecting at least two target index tables from the target index table set and loading them into memory includes: The number of target index tables to be loaded in a single operation is dynamically determined based on the current available memory resources and system load. When the number of target index tables reaches a preset threshold, the upward adjustment of the number of target index tables will stop.
[0009] In some embodiments, after updating the physical address information corresponding to the current logical address in the current target index table and marking the corresponding mapping entry as synchronized, the method further includes: flushing the updated target index table to a non-volatile storage medium.
[0010] In some embodiments, the target index table is a logical-to-physical address mapping table, and the mapping entries belong to the table entries in the physical-to-logical address mapping table.
[0011] Secondly, embodiments of this application provide a data mapping table updating apparatus, comprising: The acquisition module is used to acquire multiple mapping entries from physical addresses to logical addresses that need to be updated; The determining module is used to determine a set of target index tables to be updated based on each logical address in the mapping entry to be updated, and to select at least two target index tables from the set of target index tables and load them into memory; The traversal module is used to traverse all the mapping entries to be updated. For any mapping entry, the identifier of the target index table to which it belongs is determined according to the corresponding logical address. The update module is used to query the pre-established index structure according to the identifier, and when it is determined that the current target index table has been loaded, update the physical address information corresponding to the current logical address in the current target index table, and mark the corresponding mapping entry as synchronized; The synchronization control module is used to repeatedly execute the remaining mapping entries to be updated until all the mapping entries to be updated are marked as synchronized.
[0012] Thirdly, embodiments of this application provide a solid-state drive (SSD) including a processor and a memory. The memory stores a computer program, and the processor executes the computer program to implement the data mapping table update method described above.
[0013] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed on a processor, implements the aforementioned data mapping table update method.
[0014] The embodiments of this application have the following beneficial effects: By loading multiple target index tables into memory at once and completing the ownership determination and update operations for multiple mapping entries in a single traversal, this application can reduce the overhead of repeated traversal caused by table-by-table loading in traditional schemes. This method can avoid invalid queries on a large number of irrelevant mapping entries when processing only one target index table at a time, thereby reducing CPU resource consumption, especially significantly improving the mapping table synchronization efficiency under high random write load scenarios. Furthermore, this application introduces a pre-established index structure to quickly identify whether the target index table corresponding to the currently pending mapping entry is already in memory, thereby enabling concurrent update management of multiple target index tables, and shortening the overall synchronization time while ensuring data consistency, thus improving the response speed and system performance of solid-state drives in address mapping update operations. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This paper illustrates a first flowchart of a data mapping table update method according to an embodiment of this application. Figure 2 This paper illustrates a second flowchart of a data mapping table update method according to an embodiment of this application. Figure 3 A schematic diagram of the third process of the data mapping table update method according to an embodiment of this application is shown; Figure 4 A fourth flowchart of the data mapping table update method according to an embodiment of this application is shown; Figure 5 A schematic diagram of a data mapping table update apparatus according to an embodiment of this application is shown. Detailed Implementation
[0017] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0018] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0019] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0020] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.
[0021] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0022] The following describes the data mapping table update method using specific examples.
[0023] Figure 1 A schematic flowchart of a data mapping table update method according to an embodiment of this application is shown. Exemplarily, the data mapping table update method includes steps S100-S500: Step S100: Obtain multiple mapping entries from physical addresses to logical addresses to be updated.
[0024] The mapping entries belong to the entries in the Physical to Logical Address Mapping Table (P2L); each mapping entry to be updated records the mapping relationship between a logical address and the corresponding physical address, wherein the logical address is used to determine its home location in the Logical to Physical Address Mapping Table (L2P).
[0025] Specifically, after the solid-state drive (SSD) receives a write request from the host and completes the data flushing to the flash memory, the controller generates the corresponding mapping entries and temporarily stores them in the P2L table cache. These mapping entries are marked as unsynchronized when they are generated, indicating that the correspondence between the logical address and the physical address contained therein has not yet been reflected in the logical-to-physical address mapping table (L2P, i.e., the target index table).
[0026] When preset synchronization trigger conditions are met, the data mapping table update process begins. These trigger conditions may include, but are not limited to: the number of unsynchronized mapping entries accumulated in the P2L table cache reaching a threshold, the system entering an idle period, or the arrival of a background task scheduling opportunity. At this time, all currently unsynchronized mapping entries are retrieved from the P2L table cache as the multiple mapping entries to be updated in this process.
[0027] It should be noted that each mapping entry, in addition to its logical address and corresponding physical address, also includes a synchronization status bit. This synchronization status bit indicates whether the entry has been updated in the target index table. The initial value can be unsynchronized, and it is set to synchronized after the update is completed. By reading the above fields, the system can accurately identify all mapping entries that need to participate in this synchronization process.
[0028] Step S200: Determine a set of target index tables to be updated based on the logical addresses in the mapping entries to be updated, and select at least two target index tables from the target index table set to load into memory.
[0029] The target index table is a logical-to-physical address mapping table (L2P table) used to record the physical storage location corresponding to each logical address. Each target index table corresponds to a contiguous logical address space, and its coverage is determined by a preset address mapping granularity. For example, if each target index table can manage a 4MB logical address space, then the logical address range [0, 4M) belongs to the first target index table, [4M, 8M) belongs to the second, and so on. To efficiently complete the synchronous update of multiple mapping entries, this embodiment adopts the following approach: first, all target index tables that need to participate in this update operation are identified centrally, forming a set of target index tables to be updated; then, some or all of the entries are loaded into memory for processing in batches.
[0030] In some implementations, such as Figure 2 As shown, a set of target index tables to be updated is determined based on each logical address in the mapping entry to be updated, including steps S210-S220: Step S210: Traverse all mapping entries to be updated and extract the logical addresses recorded in each mapping entry.
[0031] As an example, the system sequentially accesses each mapping entry to be updated obtained in step S100 and extracts its contained logical address (LAA). This process can be implemented by looping through all unsynchronized entries in the P2L table cache. Understandably, the traversal order can be linear or sorted according to the logical address before processing, as long as no unsynchronized entry is missed.
[0032] Step S220: Calculate the identifier of the target index table to which each logical address belongs based on the preset address mapping granularity, and perform deduplication on the current identifier to form a target index table set.
[0033] As an example, for each extracted logical address, the identifier of its target index table (i.e., the target index table number or index ID) is calculated based on the address mapping granularity configured in the system. Specifically, assuming each target index table manages N logical address units (e.g., each unit is 512 bytes or 4KB), the target index table identifier is equal to the logical address divided by the address mapping granularity and rounded down.
[0034] After calculating the target index table identifier corresponding to each mapping entry, it is added to a set. During the collection process, a deduplication operation is also performed to ensure that the same target index table identifier is retained only once. The final set of unique elements is the target index table set that needs to be updated. If there are 1024 mapping entries to be updated, and their logical addresses are distributed across 256 different target index tables, then the target index table set generated after deduplication will contain 256 unique identifiers, indicating that a total of 256 L2P tables need to be updated.
[0035] Furthermore, such as Figure 3 As shown, at least two target index tables are selected from the target index table set and loaded into memory, including steps S230-S240: Step S230: Dynamically determine the number of target index tables to be loaded in a single operation based on the current available memory resources and system load.
[0036] It is understandable that the target index table requires memory space (such as DRAM or SRAM) during loading. However, in DRAM-Less architectures or resource-constrained scenarios, memory capacity is limited, and it is not possible to load all tables in the entire target index table set into memory at once. Therefore, this embodiment adopts a dynamic strategy to determine the number N of target index tables loaded concurrently each time. That is, the system monitors the current available memory resources (such as free memory size), the running status of other background tasks (such as garbage collection GC, wear leveling WE), and the overall system load level in real time, and dynamically adjusts the value of parameter N based on this information. For example, when the system is idle and memory is sufficient, a larger value of N can be set (such as N=8 or 16) to maximize parallel processing efficiency; when the system is performing high-priority background tasks (such as SysGC), the value of N is actively reduced (such as N=2 or 4) to reserve sufficient resources to ensure system stability; in extremely low resource conditions, N can be set to 2. This dynamic adjustment mechanism in this embodiment can be preset through a strategy table in the configuration file, or it can be determined online by the controller firmware through algorithm evaluation.
[0037] Step S240: When the number of target index tables reaches a preset threshold, stop increasing the number of target index tables.
[0038] Furthermore, the system can set a preset threshold for the maximum allowed number of loaded tables (e.g., 32) to prevent memory exhaustion or scheduling delays due to excessive resource requests. Additionally, the trend of performance gains can be considered: as N increases, although the total number of queries decreases, the management overhead of maintaining multiple loaded tables (such as lookup judgments and linked list maintenance) also increases. When the performance improvement brought by further increasing N tends to plateau (i.e., performance gain saturation), it is considered to have reached the optimal operating point, and there is no need to further increase the value of N.
[0039] After completing steps S210-S240 above, select N target index tables to be processed in the current round from the target index table set and start the loading process. The loading process includes, but is not limited to, initiating a read request to the NAND flash memory controller, reading the target index table with the specified number from the non-volatile storage medium into memory, and allocating cache space and management structure for it.
[0040] In some implementations, each target index table has a corresponding cached entity in memory, including but not limited to a memory starting address, a target index table identifier, a reference count (for multi-task sharing control), status flags (including unmodified, modified, loading, and flushing), and a linked list pointer field (for subsequent mounting to the index structure). Once loaded, these target index tables are ready for subsequent traversal and update operations. It is understood that the loading process does not necessarily require parallel reading of all N tables at once; it can also be performed sequentially or in a pipelined manner, as long as all are ready before the start of the current processing round. Meanwhile, the remaining unloaded entries in the target index table set will be processed in subsequent batches according to the same process until the entire set is processed.
[0041] Step S300: Traverse all mapping entries to be updated. For any mapping entry, determine the identifier of the target index table it belongs to based on the corresponding logical address.
[0042] In this step, all the mapping entries to be updated obtained in the above steps are uniformly traversed, and for each mapping entry, the identifier (i.e., the target index table number) of the target index table to which its logical address belongs is calculated, so as to determine whether the entry belongs to a table in the currently loaded target index table set.
[0043] Specifically, the system initiates a loop process, sequentially accessing each mapping entry that has not yet been marked as synchronized. For any mapping entry currently being processed, its recorded logical address (LAA) is extracted. Then, based on the same address mapping granularity and calculation rules as in step S220, the target index table identifier corresponding to that logical address is determined. In this way, the system can accurately identify the distribution location of each mapping entry in the logical address space, and thus determine whether it falls within the range of the target index table currently loaded in memory.
[0044] In step S400, if the pre-established index structure is queried based on the identifier, when it is determined that the current target index table has been loaded, the physical address information corresponding to the current logical address in the current target index table is updated, and the corresponding mapping entry is marked as synchronized.
[0045] After calculating the target index table identifier for any mapping entry in step S300, it is necessary to determine whether the target index table corresponding to the identifier has been loaded into memory in the current batch. Therefore, before step S400, a pre-built index structure needs to be constructed and maintained in memory to efficiently manage the information of multiple target index tables loaded in this round, thereby avoiding the performance overhead of traversing all loaded tables.
[0046] The index structure is a linked list array, which includes multiple hash slots, each hash slot corresponding to a linked list head node. The identifier of any target index table is determined by a hash function to determine the corresponding hash slot, and then attached to the linked list corresponding to the hash slot.
[0047] Before the first execution of this process, or whenever a new set of target index tables is processed, the system dynamically allocates a contiguous space in memory to create the index structure. Specifically, a pointer array ast_L2PHead[Y] can be defined, where Y represents the length of the linked list array (i.e., the total number of hash slots), and each element is a pointer to the head node of a linked list, initially set to NULL. Subsequently, after each target index table is successfully loaded in step S200, its related information is encapsulated into a linked list node and attached to the corresponding position in the index structure. Each linked list node includes at least the target index table identifier, memory address (pointing to the starting address of the target index table in memory), reference count (recording how many tasks are currently using the table), status flags (including unmodified, modified, loading, flushing, etc.), and a linked list pointer (pointing to the next node in the same linked list).
[0048] The process of mounting a linked list node is as follows: obtain the identifier of the target index table to be added, calculate the hash index according to the identifier of the target index table, locate the corresponding head node of the linked list according to the hash index, and then insert the node into the head of the linked list pointed to by the corresponding hash index to become the new head node. If there is no node in the slot, the new node is directly used as the head node; otherwise, the new node is connected to the original head node through a pointer to form a singly linked list structure. In this way, all loaded target index tables are distributed in the corresponding hash slot linked list according to their identifiers, forming a complete index structure. For example, assuming the length of the linked list array Y=32, the identifiers of the currently loaded target index tables are 2, 34, and 66, then their corresponding hash indices are all: 2 mod 32=2. Therefore, these three tables will be mounted to the linked list guided by ast_L2PHead[2] to form a linked list of length 3. This method can effectively reduce the average length N / Y of a single linked list by increasing the array length Y, thereby reducing the traversal overhead caused by collisions. When Y When N (i.e., the array length is not less than the number of tables to be loaded) is reached, the average query performance reaches its optimal level.
[0049] In some implementations, such as Figure 4 As shown, based on the identifier query, the pre-established index structure is used to determine whether the current target index table has been loaded, including steps S410-S440: Step S410: Calculate the modulo result of the identifier of the target index table with a preset integer to obtain the corresponding hash index.
[0050] Step S420: Locate the corresponding head node of the linked list in the linked list array based on the hash index.
[0051] As an example, when processing each mapping entry, a modulo operation is performed based on the target index table identifier ID calculated in step S300 to obtain the corresponding hash index. After obtaining the hash index, the corresponding item in the linked list array is directly accessed to obtain its corresponding linked list head node. This operation has low time complexity and can quickly locate the starting position of the target linked list without traversing the entire array, thus efficiently completing the location.
[0052] Step S430: Traverse each linked list node in the linked list guided by the head node, and compare the target index table identifier recorded in each linked list node.
[0053] Step S440: If there is an identifier in a linked list node that is the same as the identifier of the current target index table, then it is confirmed that the current target index table has been loaded.
[0054] Understandably, during traversal, we can start from the head node of the linked list and check the target index table identifier stored in each node in the linked list sequentially until a match is found or the entire linked list is traversed. If, during the traversal, the target index table identifier of a linked list node is found to be the same as the target index table identifier required by the current mapping entry, it is determined that the target index table has been loaded into memory, and the next update operation can proceed. Conversely, if no matching node is found after the traversal ends, it means that the target index table to which the current mapping entry belongs is not within the scope of this loading, and no further processing is required.
[0055] Once it is confirmed that the current target index table has been loaded, the system performs a data update operation. This includes: locating the corresponding entry in the target index table based on the logical address in the current mapping entry. This location is the offset of the logical address relative to the starting address of its target index table, divided by the unit mapping granularity. Then, the original physical address PAA in the entry is updated to the new physical address value recorded in the current mapping entry. Simultaneously, the synchronization status of the mapping entry is set to synchronized, indicating that it has completed reverse synchronization in the target index table. The status of the target index table is changed from unmodified or loading to modified, indicating that its content has been modified and needs to be flushed to non-volatile storage media in subsequent steps to ensure data persistence. For example, assuming a mapping entry has LAA = 0x80A000, its target index table ID is calculated to be 2, and this table is already loaded in memory. Further calculation shows its offset within the table is the 10th entry (offset=10). The system then updates the PAA field of the 10th entry to the new physical address and sets the synchronization status of that mapping entry to 1.
[0056] The query and update process described in this embodiment can be completed by traversing all the mapping entries to be updated only once during the entire synchronization process, thereby reducing CPU resource consumption. Especially in random write scenarios, traditional solutions require repeated traversal of the P2L table multiple times (one traversal for each L2P table loaded), while this embodiment only requires one scan to complete all valid matches and updates, thus significantly improving processing efficiency.
[0057] Step S500: Repeat the process for the remaining mapping entries to be updated until all mapping entries to be updated are marked as synchronized.
[0058] After loading the target index table and updating its corresponding mapping entries for the current batch, not all mapping entries to be updated have been processed. Some mapping entries have not yet been synchronized because their target index tables were not loaded in this round. Therefore, this embodiment uses a loop control mechanism to continuously process the remaining unsynchronized mapping entries until all mapping entries are marked as synchronized, thereby ensuring the consistency of the entire P2L table cache.
[0059] Specifically, the system determines whether there are any mapping entries that have not yet been marked as synchronized. If so, the next round of processing is initiated, entering a new iteration cycle. Each round of processing includes the following actions: based on the remaining unsynchronized mapping entries, the next set of target index tables to be updated is redefined; then, according to the dynamic strategy in steps S230 and S240, at least several target index tables are selected again for loading; then, the pre-established index structure (i.e., linked list array) is rebuilt or updated in memory to manage the newly loaded target index tables in this round; all the original mapping entries to be updated are traversed again to identify entries belonging to the target index tables already loaded in this round, and the corresponding update and synchronization marking operations are performed. This process is repeated continuously, forming a multi-round batch processing mechanism, with each round focusing on the update tasks of a portion of the target index tables, thus effectively balancing the contradiction between memory resource consumption and processing efficiency.
[0060] After each iteration is completed, the system checks the synchronization status bit of all mapping entries. If it finds that the bit of every mapping entry has been set to synchronized, it determines that the P2L table synchronization task has been completed and terminates the loop process.
[0061] In a specific example, assume there are initially 1024 mapping entries to be updated, distributed across 256 different target index tables. The system completes all processing in 64 rounds, loading 4 tables at a time. After the final round, the synchronization status bit of all mapping entries is set to 1, the controller sends a synchronization completion signal, and can release relevant temporary resources (such as the memory space of the linked list array) and transition to an idle or background task state.
[0062] In addition, the system can be configured with a timeout protection mechanism or a maximum number of retries to prevent infinite loops due to abnormal conditions. For example, if entries are still not synchronized after a predetermined number of rounds, an error log or degradation process can be triggered to ensure system stability.
[0063] To more clearly illustrate the technical solution of this embodiment, a specific numerical example is provided below for detailed explanation. Assuming each L2P table manages 8 consecutive logical address units, its coverage area is as follows: L2P0 manages LAA. L2P1 Management LAA L2P2 Management of LAA L2P3 Management of LAA The current P2L table contains 32 mapping entries awaiting synchronization. Their recorded logical addresses (LAAs) are arranged sequentially as shown in Table 1.
[0064] The specific steps for performing the P2L table synchronization task according to the method in this embodiment are as follows: Step 1: Load L2P0 and L2P1, and update the corresponding mapping entries.
[0065] Specifically, the controller determines that the target index table set to be processed in this round is {L2P0, L2P1}; loads L2P0 and L2P1 from NAND flash memory into memory; constructs a linked list array ast_L2PHead[Y], with array length Y=2; where L2P0's identifier ID=0, calculates the hash index to get 0 % 2 = 0, then encapsulates it as a linked list node and attaches it to ast_L2PHead[0]; L2P1's identifier ID=1, calculates the hash index to get 1%2=1, then attaches it to the head of the linked list of ast_L2PHead[1]. Then, iterate through all P2L Entry once. For the LAA in the current Entry, calculate its L2P table ID. Based on the ID, calculate the hash index k = ID % 2, and then locate it to ast_L2PHead[k]. Iterate through the nodes in the linked list and compare the target index table identifiers recorded in each node. If there is a match, it is confirmed that the L2P table has been loaded in memory. Perform the following operations: (1) Locate the offset position of the corresponding entry in the L2P table; (2) Update its PAA field to the new physical address; (3) Set the synchronization status of the P2L Entry to synchronized. Other Entries that do not belong to L2P0 / L2P1 are not processed for the time being. After completion, flush L2P0 and L2P1 to non-volatile storage media in sequence. The Entries that have been updated at this time are shown in Table 2.
[0066] Table 2:
[0067] Step 2: Load L2P3 and L2P2, and continue updating the remaining Entries.
[0068] Specifically, continue processing the remaining unsynchronized Entries, determine the next target index table as {L2P2,L2P3}; load L2P2 (ID=2) and L2P3 (ID=3) into memory; update the linked list array: L2P2:2%2=0, mount to ast_L2PHead[0]; L2P3:3%2=1; mount to ast_L2PHead[1]; traverse all P2LEntry again, find and update the entries belonging to L2P2 and L2P3; flush L2P2 and L2P3.
[0069] At this point, all mapping entries have been marked as synchronized, and the entire P2L table synchronization task is complete, as shown in Table 3:
[0070] Furthermore, the organization of the linked list array follows the following general chaining rules: For any integer X and a preset array length Y, if the identifier of a certain L2P table is I, then its mounting position is determined by I%Y: all L2P tables that satisfy I≡k(mod Y) are mounted to the linked list guided by ast_L2PHead[k]; for example, when Y=4: the tables with IDs of 0, 4, 8, 12, ... are mounted to ast_L2PHead[0], the tables with IDs of 1, 5, 9, 13, ... are mounted to ast_L2PHead[1], and so on.
[0071] This structure allows the system to determine whether a certain L2P table has been loaded in an average time of O(1), which can significantly reduce CPU query overhead.
[0072] This embodiment improves the address mapping synchronization efficiency of solid-state drives (SSDs) in random write scenarios by introducing a batch processing mechanism and an efficient index structure during the data mapping table update process. Compared to the traditional method of loading target index tables one by one and repeatedly traversing physical-to-logical mapping entries, this embodiment can centrally process multiple loaded target index tables in a single traversal, thereby effectively reducing repeated query operations for missed or updated mapping entries and reducing CPU computational overhead. Furthermore, by constructing a linked list array as a pre-built index structure and using modulo operations to quickly locate the target index table identifier, the system can determine whether a target index table has been loaded into memory in a short time, thus avoiding the performance loss caused by linearly traversing all loaded tables. This index structure supports dynamically adjusting the array length to balance space usage and query efficiency.
[0073] Figure 5 A schematic diagram of a data mapping table updating apparatus according to an embodiment of this application is shown. Exemplarily, the data mapping table updating apparatus includes: The acquisition module 100 is used to acquire multiple mapping entries from physical addresses to logical addresses to be updated; The determination module 200 is used to determine a set of target index tables to be updated based on each logical address in the mapping entry to be updated, and select at least two target index tables from the target index table set to load into memory; Traversal module 300 is used to traverse all mapping entries to be updated. For any mapping entry, the identifier of the target index table to which it belongs is determined according to the corresponding logical address. The update module 400 is used to query the pre-established index structure based on the identifier. When it is determined that the current target index table has been loaded, it updates the physical address information corresponding to the current logical address in the current target index table and marks the corresponding mapping entry as synchronized. The synchronization control module 500 is used to repeatedly execute the remaining mapping entries to be updated until all mapping entries to be updated are marked as synchronized.
[0074] It is understood that the apparatus of this embodiment corresponds to the data mapping table update method of the above embodiments, and the options in the above embodiments are also applicable to this embodiment, so they will not be described again here.
[0075] This application also provides a solid-state drive, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor, by running the computer program, causes the solid-state drive to perform the functions of the various modules in the above-described data mapping table update method or the above-described data mapping table update apparatus.
[0076] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.
[0077] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving execution instructions.
[0078] This application also provides a computer-readable storage medium for storing the computer program used in the aforementioned solid-state drive. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0079] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0080] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0081] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.
[0082] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A method for updating a data mapping table, characterized in that, include: Retrieve multiple physical address to logical address mapping entries to be updated; A set of target index tables to be updated is determined based on each logical address in the mapping entry to be updated, and at least two target index tables are selected from the set of target index tables and loaded into memory; Iterate through all the mapping entries to be updated. For any mapping entry, determine the identifier of the target index table it belongs to based on the corresponding logical address. If the pre-established index structure is queried according to the identifier, when it is determined that the current target index table has been loaded, the physical address information corresponding to the current logical address in the current target index table is updated, and the corresponding mapping entry is marked as synchronized; Repeat the process for the remaining mapping entries to be updated until all of them are marked as synchronized.
2. The data mapping table update method according to claim 1, characterized in that, The step of querying the pre-built index structure based on the identifier, before determining that the current target index table has been loaded, further includes: The index structure is established in the memory; wherein the index structure is a linked list array, the linked list array includes multiple hash slots, each hash slot corresponds to a linked list head node; the identifier of any target index table is determined by a hash function to determine the corresponding hash slot, and is attached to the linked list corresponding to the hash slot.
3. The data mapping table update method according to claim 2, characterized in that, The step of querying the pre-built index structure based on the identifier, after determining that the current target index table has been loaded, includes: Calculate the modulo result of the identifier of the target index table with a preset integer to obtain the corresponding hash index; The hash index is used to locate the corresponding head node of the linked list in the linked list array; Traverse each node in the linked list guided by the head node of the linked list, and compare the target index table identifier recorded in each of the linked list nodes. If there exists an identifier in the linked list node that is the same as the identifier of the current target index table, then it is confirmed that the current target index table has been loaded.
4. The data mapping table update method according to claim 1, characterized in that, The step of determining a set of target index tables to be updated based on each logical address in the mapping entry to be updated includes: Iterate through all the mapping entries to be updated and extract the logical address recorded in each mapping entry; Based on the preset address mapping granularity, the identifier of the target index table to which each logical address belongs is calculated, and the current identifier is deduplicated to form the target index table set.
5. The data mapping table update method according to claim 1, characterized in that, The step of selecting at least two target index tables from the target index table set and loading them into memory includes: The number of target index tables to be loaded in a single operation is dynamically determined based on the current available memory resources and system load. When the number of target index tables reaches a preset threshold, the upward adjustment of the number of target index tables will stop.
6. The data mapping table update method according to claim 1, characterized in that, After updating the physical address information corresponding to the current logical address in the target index table and marking the corresponding mapping entry as synchronized, the method further includes: flushing the updated target index table to a non-volatile storage medium.
7. The data mapping table update method according to claim 1, characterized in that, The target index table is a logical-to-physical address mapping table, and the mapping entries belong to the table entries in the physical-to-logical address mapping table.
8. A data mapping table update device, characterized in that, include: The acquisition module is used to acquire multiple mapping entries from physical addresses to logical addresses that need to be updated; The determining module is used to determine a set of target index tables to be updated based on each logical address in the mapping entry to be updated, and to select at least two target index tables from the set of target index tables and load them into memory; The traversal module is used to traverse all the mapping entries to be updated. For any mapping entry, the identifier of the target index table to which it belongs is determined according to the corresponding logical address. The update module is used to query the pre-established index structure according to the identifier, and when it is determined that the current target index table has been loaded, update the physical address information corresponding to the current logical address in the current target index table, and mark the corresponding mapping entry as synchronized; The synchronization control module is used to repeatedly execute the remaining mapping entries to be updated until all the mapping entries to be updated are marked as synchronized.
9. A solid-state drive, characterized in that, The solid-state drive includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the data mapping table update method according to any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed on a processor, implements the data mapping table update method according to any one of claims 1-7.