Method and device for realizing receiving reordering of network-on-chip nodes
By introducing a packet reordering module into the on-chip network node, the problem of out-of-order packet arrival in multi-core systems is solved, ensuring that packets are submitted in the order they were sent, thus achieving data integrity and security.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-08
- Publication Date
- 2026-04-07
AI Technical Summary
In a multi-core system, multiple core request sources may send data to the same target node simultaneously, causing data packets to arrive out of order. This makes it difficult for the target node receiver to manage and reorder the packets, affecting data integrity.
Design an on-chip network node receive reordering method. By combining the routing network and network interface, a packet reordering module is used to independently reorder multiple VC data streams. This module includes a master control unit, a deep data circular buffer, a buffer space management module, a packet management module, and a message-level linked list to ensure that packets are submitted in the order they were sent.
This ensures that data packets are submitted in the order they are sent, guaranteeing data integrity and security.
Smart Images
Figure CN121807768A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of network-on-chip, and particularly provides a receiving reordering implementation method and device of a network-on-chip node. BACKGROUND
[0002] Network-on-chip (NoC) is a new communication method of system-on-chip (SoC), as a main component of multi-core technology, concurrent communication is realized through distributed routing nodes and time-division multiplexing links, and the traditional bus architecture is replaced to solve the problems of scalability and performance bottleneck, such as the attached Figure 2 A network-on-chip (NoC) node is generally connected to input and output ports of adjacent nodes in east, west, south and north directions and local input and output ports, and each port is divided into 4 VC channels (VC0 / VC1 / VC2 / VC3) in a typical scenario. The basic unit of network-on-chip data transmission is a message, the message is a logical unit of communication, and represents a complete communication intention (such as a cache request, data transmission). Each message can contain multiple data packets (Packet), the data packet is a physical unit of communication, is a fixed-size segment after the message is segmented, and is also a basic unit controlled by a network-on-chip routing algorithm. Each data packet is composed of multiple flits, the flit is the smallest constituent unit of the data packet and is a basic unit of flow control. The data packet contains a head flit, a body flit (control type information can be absent), and a tail flit. Each data packet head flit contains a core ID, a message ID, a data packet ID, a data packet size, a VCID, a first data packet in a message, a last data packet in a message, a flit type, and a flit sequence number, the body flit contains a core ID, a flit type, a flit sequence number, a data packet ID modulo M value, and a payload, and the tail flit contains a core ID, a flit type, a flit sequence number, a data packet ID modulo M value, and a transmission completion flag. The allocation strategy of the data packet ID in the same core is continuous incremental allocation, rather than message-level reset. Different data packets of the same message share the same VCID.
[0003] In a multi-core system, multiple core request sources can simultaneously send data to the same target node, different messages of the same core or data packets in the same message reach the same target node through different routing paths, and in some special scenarios, flits in the same data packet can also reach in disorder. At the receiving end of the target node, the disordered data packets need to be managed and rearranged to ensure that the final output is submitted in the sending order and the data integrity is ensured. SUMMARY
[0004] The present application is aimed at the deficiencies of the prior art, and provides a network-on-chip node receiving reordering implementation method with strong practicability.
[0005] The further technical task of the present application is to provide a receiving reordering implementation device of an on-chip network node which is reasonable in design and safe in application.
[0006] The technical scheme adopted by the present application to solve its technical problems is:
[0007] A receiving reordering implementation method of an on-chip network node, the on-chip network node is divided into a routing network and a network interface, in a local receiving direction, a local output port of the routing network selects each input direction VC data through a corresponding VC channel; the input of the network interface is correspondingly connected to the data transmitted by the VC channel.
[0008] A data packet reordering module is arranged in the network interface part, and the multiple VC data are independently reordered, and the minimum unit accessed by each VC data is a flit.
[0009] Further, the data packet reordering module comprises a master control, a deep data circular buffer area, a buffer area space management module, M data packet management modules and N sets of message level linked lists.
[0010] The master control is responsible for identification of a newly received flit, sending the flit to a certain data packet management module or temporarily storing the flit in a public register group.
[0011] The data circular buffer area stores the flits of multiple cores, multiple messages and multiple data packets received by the VC channel.
[0012] The buffer area space management module opens a complete buffer space according to the data packet size carried by the data packet head flit, and stores the body flit and the tail flit of the subsequent data packet.
[0013] The data packet management module is responsible for identification and writing of a newly arrived flit in the buffer area.
[0014] The message level linked list is responsible for collection of data packets in a message.
[0015] Further, the master control is responsible for sending data packet information of a complete received data packet to a certain message linked list, reading the data buffer area according to the message linked list order and sending the data to a local processing core.
[0016] When a new flit is received, if the flit is a head flit, the M data packet management modules are traversed, the head flit is sent to the first idle data packet management module, and the core ID and the data packet ID are recorded.
[0017] The M data packet management modules are traversed, the core ID and the data packet ID carried by the new flit are taken modulo M, it is inquired whether the head flit of a data packet to which the flit belongs has been received, and if so, the flit is sent to the data packet management module.
[0018] If no head flit of the same data packet is found in the M data packet management modules, the flit is sent to the public register group cache.
[0019] Further, when receiving a new data packet collection completion signal from the data packet management module group, the N message link lists are traversed to query whether there is a non-idle link list with the same message ID by using the core ID, data packet ID and message ID carried by the new data packet. If yes, the data packet information is sent to the message link list with the same message ID.
[0020] If no non-idle link list with the same message ID is found in the N message link lists, the data packet is sent to a new message link list.
[0021] Further, when receiving a data packet collection completion signal from the message link list group, the flits are read from the data cache area in the order of the sorted data packet ID, and the payloads are extracted and sent to the local processing core.
[0022] After all the data packets in the message are sent to the local processing core, the message link list is emptied and enters the idle state.
[0023] Further, the data circular cache area opens cache space according to the data packet level, and the data packet cache space is allocated in the order of the arrival order of the data packet head flit.
[0024] Further, the cache area space management module provides at most M data packet address ranges at the same time, is responsible for the circular management of the cache area read-write pointers, dynamically manages the cache space, and recycles the read data packet space and allocates space for new data packets.
[0025] Further, after receiving the head flit sent by the master, the data packet management module applies for new data packet cache space from the cache area space management module, obtains the first address position of the space, and writes the head flit into the cache space.
[0026] The public register group is checked to see whether the body flit or the tail flit of the same data packet has been received, the address offset is calculated according to the flit type and the flit serial number, and the flit is moved from the register group to the cache space.
[0027] After receiving the body flit or the tail flit sent by the master, the address offset is calculated according to the flit type and the flit serial number, and the subsequent flit is written into the cache space.
[0028] After all the flits of the data packet are collected, the master is informed, the data packet management module is emptied, and enters the idle state.
[0029] Further, the message level chain table records chain table entries in the complete packet receiving order, and concatenates the chain table entries in the packet ID order, at this time, the message does not distinguish whether it is a multi-core message or a message of the same core.
[0030] Specifically, the method comprises the following steps:
[0031] Each chain table entry of the message chain table records a packet information, including a packet ID, whether it is the first or last packet of the message, an address range of a corresponding buffer area of the packet, and a position of a previous packet chain table entry in the chain table and a position of a next packet chain table entry in the chain table.
[0032] Upon receiving a new packet, the packet chain table is dynamically managed, the new packet is inserted, the positions of the new packet and the upper and lower packets in the chain table are adjusted, when all the packets in the message are collected, the master is informed, after all the packets in the message are read from the data buffer area, the message chain table is emptied and enters an idle state.
[0033] The receiving reordering implementation device of the on-chip network node comprises at least one memory and at least one processor.
[0034] The at least one memory is used for storing a machine readable program.
[0035] The at least one processor is used for calling the machine readable program and performing the receiving reordering implementation method of the on-chip network node.
[0036] Compared with the prior art, the receiving reordering implementation method and device of the on-chip network node have the following outstanding beneficial effects:
[0037] The application can ensure that the final output is submitted in the sending order and guarantee data integrity. BRIEF DESCRIPTION OF DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.
[0039] Figure 1 It is a flowchart of the receiving reordering implementation method of the on-chip network node.
[0040] Figure 2 It is an existing architecture diagram in the receiving reordering implementation method of the on-chip network node. DETAILED DESCRIPTION
[0041] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0042] The following is a preferred embodiment:
[0043] like Figure 1 As shown in this embodiment, a method for receiving and reordering data in an on-chip network node is described. The on-chip network node is divided into two parts: a routing network (NR) and a network interface (NI). In the local receiving direction, the local output port of the routing network (NR) selects data from the four input directions according to the four VC channels. The input of the network interface (NI) is correspondingly connected to the data from the four VC channels.
[0044] The packet reordering module (ROB) is located in the network interface (NI) section and independently reorders multiple VC data streams. The following describes the reordering scheme for a single VC data stream. The smallest unit of each VC data stream is a micro-slice, and out-of-order arrival of core-level micro-slices, message-level micro-slices, and intra-packet micro-slices is possible.
[0045] The packet reordering module ROB includes one master controller, one deep data circular buffer, one buffer space management module, M packet management modules, and N sets of message-level linked lists.
[0046] N is the maximum number of out-of-order messages that are likely to occur on a single VC channel of the ROB, including the total number of messages from multiple cores or a single core, determined by actual on-chip network performance simulation. M is the maximum number of out-of-order packets that are likely to occur on a single VC channel of the ROB, determined by actual on-chip network performance simulation.
[0047] The main controller is responsible for identifying newly received microchips①, sending them to a data packet management module② or temporarily storing them in a common register group②, sending the complete received data packet information to a message list④, and reading the data buffer in the order of the message list and sending it to the local processing core⑥.
[0048] The data circular buffer stores the micro-shards of multiple cores, multiple messages, and multiple data packets received by this VC channel. Complete buffer space is allocated at the data packet level, with the data packet buffer space allocated according to the arrival order of the data packet header micro-shards. The depth of the data circular buffer is determined by actual on-chip network performance simulation.
[0049] The buffer space management module opens complete buffer space according to the data packet size carried by the data packet head flit, to store the body flits and tail flits of the subsequent data packet. At most, M data packet address ranges are provided at the same time. The cycle management of the buffer area read-write pointer is responsible. The dynamic management of the buffer space is responsible for recycling the read data packet space and allocating space for new data packets.
[0050] The data packet management module group is mainly responsible for the identification and writing of new flits into the buffer area, including address calculation for writing into the buffer area, flit query in the public register, address calculation for moving from the register to the buffer area, and flit moving.
[0051] The message level linked list group is mainly responsible for collecting data packets in the message, recording linked list entries in the order of complete data packet reception, and concatenating linked list entries in the order of data packet ID. Here, the message does not distinguish between multi-core messages and messages of the same core.
[0052] The ROB master workflow is as follows:
[0053] When the ROB receives a new flit,
[0054] If the flit is a head flit, traverse the M data packet management modules, send the head flit to the first idle data packet management module, and record the core ID and data packet ID.
[0055] Traverse the M data packet management modules, query whether the head flit of the same data packet has been received through the core ID and data packet ID carried by the new flit, and if so, send the flit to its data packet management module.
[0056] If no head flit of the same data packet is found after traversing the M data packet management modules, send the flit to the public register group buffer.
[0057] When receiving a new data packet collection completion signal ③ from the data packet management module group,
[0058] Traverse the N message linked lists, query whether there is a non-idle linked list with the same message ID through the core ID, data packet ID, and message ID carried by the new data packet, and if so, send the data packet information to the message linked list.
[0059] If no non-idle linked list with the same message ID is found after traversing the N message linked lists, send the data packet to a new message linked list.
[0060] When receiving a data packet collection completion signal ⑤ from the message linked list group,
[0061] Read the flits from the data buffer area in the order of sorted data packet ID, and send the valid payload to the local processing core.
[0062] After all data packets in the message are sent to the local processing core, the message linked list is emptied and enters an idle state.
[0063] Workflow of the data packet management module:
[0064] After receiving the head flit sent by the master, a new data packet cache space is applied to the cache space management module, the first address position of the space is obtained, and the head flit is written into the cache space.
[0065] The public register group is checked to see whether the body flit or the tail flit of the same data packet has been received, the address offset is calculated according to the flit type and the flit sequence number, and the flit is moved from the register group to the cache space.
[0066] After receiving the body flit or the tail flit sent by the master, the address offset is calculated according to the flit type and the flit sequence number, and the flit is written into the cache space.
[0067] After all flits of the data packet are collected, the master is informed that the data packet management module is emptied and enters an idle state.
[0068] Workflow of the message-level linked list group:
[0069] Each linked list entry of the message linked list records a data packet information, including the data packet ID, whether it is the first or the last data packet of the message, the address range of the data packet corresponding to the cache space, and the position of the previous data packet linked list entry in the linked list and the position of the next data packet linked list entry in the linked list.
[0070] After receiving a new data packet, the data packet linked list is dynamically managed, the new data packet is inserted, and the positions of the new data packet and the upper and lower data packets in the linked list are adjusted. When all data packets in the message are collected, the master is informed. After all data packets of the message are read from the data cache space, the message linked list is emptied and enters an idle state.
[0071] Based on the above method, the receiving reordering implementation device of the on-chip network node in the embodiment includes at least one memory and at least one processor.
[0072] The at least one memory is configured to store a machine-readable program.
[0073] The at least one processor is configured to call the machine-readable program and execute the receiving reordering implementation method of the on-chip network node.
[0074] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (PLD), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor can be a microprocessor or any conventional processor.
[0075] The memory can be used to store computer programs and / or modules, and the processor can realize various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and calling data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store operating systems, application programs required by at least one function, etc.; and the data storage area can store data created according to the use of the terminal, etc. In addition, the memory can also include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a secure digital (SD) card, a flash card, at least one disk storage period, a flash memory device, or other volatile solid-state memory devices.
[0076] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for implementing receiver reordering in an on-chip network node, characterized in that, The on-chip network node is divided into two parts: a routing network and a network interface. In the local receiving direction, the local output port of the routing network selects the VC data in each input direction through the corresponding number of VC channels; the input of the network interface is connected to the data transmitted by the aforementioned VC channels. The network interface section is equipped with a packet reordering module, which independently reorders multiple VC data streams, and the smallest unit for each VC data stream is a micro-chip.
2. The method for implementing receiver reordering of an on-chip network node according to claim 1, characterized in that, The packet reordering module includes a master control unit, a deep data circular buffer, a buffer space management module, M packet management modules, and N sets of message-level linked lists. The main controller is responsible for identifying newly received microchips and sending them to a data packet management module or temporarily storing them in a common register group. The data circular buffer stores micro-slices of multi-core, multi-message, and multi-data packets received by the VC channel; The buffer space management module allocates a complete buffer space according to the size of the data packet carried by the data packet header micro-pie, which is used to store the body micro-pie and tail micro-pie of subsequent data packets; The data packet management module is responsible for identifying newly arrived microchips and writing them to the cache. The message-level linked list is responsible for collecting data packets within the message.
3. The method for implementing receiver reordering of an on-chip network node according to claim 2, characterized in that, The main controller is responsible for sending the received data packet information to a message list, and reading the data buffer in the order of the message list and sending it to the local processing core. When a new micro-fragment is received, if the micro-fragment is a header micro-fragment, then the M data packet management modules are traversed, and the header micro-fragment is sent to the first idle data packet management module, and the core ID and data packet ID are recorded. Iterate through M data packet management modules, take the modulo value of M using the core ID and data packet ID carried by the new micro-chip, and check whether the header micro-chip belonging to the same data packet as the micro-chip has been received. If so, send the micro-chip to the data packet management module. If none of the header fragments belonging to the same data packet are found after traversing M data packet management modules, then the fragment is sent to the common register group cache.
4. The method for implementing receiver reordering of an on-chip network node according to claim 3, characterized in that, When a new data packet collection completion signal is received from the data packet management module group, the N message lists are traversed. The core ID, data packet ID, and message ID carried by the new data packet are used to check if there is a non-idle list with the same message ID. If so, the data packet information is sent to the message list with the same message ID. If none of the N message lists have a non-idle list with the same message ID, the data packet is sent to a new message list.
5. The method for implementing receiver reordering of an on-chip network node according to claim 4, characterized in that, When a data packet collection completion signal is received from the message list group, the data packets are read sequentially from the data buffer according to their IDs after being sorted by the list, and the payload is extracted and sent to the local processing core. After all data packets in the message are sent to the local processing core, the message list is informed to clear its contents and enter an idle state.
6. The method for implementing receiver reordering of an on-chip network node according to claim 5, characterized in that, The data circular buffer allocates buffer space at the data packet level, and the data packet buffer space is allocated in the order of arrival of the data packet header fragments.
7. The method for implementing receiver reordering of an on-chip network node according to claim 6, characterized in that, The buffer space management module provides the address range of up to M data packets at the same time, and is responsible for the cyclic management of buffer read and write pointers, dynamically managing buffer space, reclaiming space of read data packets, and allocating space for new data packets.
8. The method for implementing receiver reordering of an on-chip network node according to claim 7, characterized in that, After receiving the header micro-piece from the master control, the data packet management module requests new data packet cache space from the cache space management module, obtains the first address of the space, and writes the header micro-piece into the cache space. Check if there is a body fragment or tail fragment of the same data packet that has been received in the common register set. Calculate the address offset based on the fragment type and fragment number, and move the fragment from the register set to the cache space. Upon receiving subsequent micro-slices or tail micro-slices from the master controller, the address offset is calculated based on the micro-slice type and micro-slice sequence number, and the subsequent micro-slices are written into the cache space. Once all micro-shards of the data packet have been collected, the main controller is notified, and the data packet management module is cleared and enters an idle state.
9. A method for implementing receiver reordering of an on-chip network node according to claim 2 or 8, characterized in that, The message-level linked list records linked list entries in the order in which data packets are received completely, and the linked list entries are chained together in the order of data packet ID. At this time, the message does not distinguish whether it is a multi-core message or a message from the same core. Specifically, it includes: Each entry in the message list records information about a data packet, including the data packet ID, whether it is the first or last data packet of the message, the address range of the corresponding buffer, and the position of the previous data packet's entry in the list and the position of the next data packet's entry in the list. Each time a new data packet is received, the data packet linked list is dynamically managed. The new data packet is inserted, and the positions of the new data packet and the data packets above and below it in the linked list are adjusted. When all data packets in the message have been collected, the master controller is notified. After all data packets in the message have been read from the data buffer, the message linked list is cleared and enters an idle state.
10. A receiving reordering implementation device for an on-chip network node, characterized in that, include: At least one memory and at least one processor; The at least one memory is used to store a machine-readable program; The at least one processor is configured to invoke the machine-readable program to perform the method according to any one of claims 1 to 9.