Digital twinning-based complex product testability scheme heuristic generation method

Abstract

The invention discloses a digital twinning-based complex product testability scheme heuristic generation method, which comprises the following steps: constructing a digital twinning model of a complex product sensing system, the digital twinning model integrating component fault data and a multi-level signal flow graph; analyzing a fault propagation path based on the multi-level signal flow graph, and determining a candidate test point set; and using an improved genetic algorithm to optimize the candidate test point set according to the component fault data and the fault propagation path, and generating an optimal testability scheme. According to the method, in the testability scheme generation process, the digital twin technology and the heuristic algorithm are combined, and collaborative improvement of the test efficiency, the fault coverage degree and the resource utilization rate is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testability scheme generation, and more particularly to a complex product testability scheme heuristic generation method based on digital twinning. BACKGROUND

[0002] With the upgrading of equipment manufacturing to "high-precision", the structural complexity and functional coupling of complex products grow exponentially, and their testability requirements shift from "post-fault detection" to "prevention + dynamic adaptation". Traditional testability scheme generation relies on human experience, which has the following three significant defects: First, the lack of quantitative basis for test point selection leads to widespread redundant testing; Second, fault modes cannot automatically cover extreme working conditions and multi-fault concurrent scenarios, making it difficult to deal with new complex faults such as sensor drift, signal link interruption, and multi-source data fusion anomalies; and the test coverage is less than 85%, leaving potential fault risks; Third, the test resource allocation lacks a global optimization mechanism, the scheme iteration cycle is long, and the product development progress is slowed down, which easily causes resource conflicts in complex equipment systems with multiple signal streams.

[0003] Especially when facing intelligent equipment with nonlinear fault propagation characteristics and dynamic time-varying characteristics, traditional methods have reached the performance bottleneck in terms of test efficiency, coverage completeness, and resource utilization.

[0004] Digital twinning technology provides a full-factor, full-process data support foundation for complex system testing by constructing a virtual mapping of physical entities. Combined with the high-efficiency global search capability of heuristic algorithms in combinatorial optimization problems, the deep integration of the two can achieve collaborative optimization of test point optimization, test sequence planning, and resource allocation, providing a scientific solution for complex product testability scheme generation.

[0005] Therefore, in the testability scheme generation process, how to achieve the collaborative improvement of test efficiency, fault coverage, and resource utilization based on digital twinning technology is a problem that needs to be solved by those skilled in the art. SUMMARY

[0006] In view of the above problems, the present application is proposed to provide a complex product testability scheme heuristic generation method based on digital twinning to overcome the above problems or at least partially solve the above problems.

[0007] To achieve the above purpose, the present application adopts the following technical solutions: The embodiment of the present application provides a complex product testability scheme heuristic generation method based on digital twinning, which includes the following steps: S1, constructing a digital twin model of a complex product perception system, the digital twin model integrated with component fault data and a multi-level signal flow graph; S2, analyzing a fault propagation path based on the multi-level signal flow graph to determine a candidate test point set; S3, using an improved genetic algorithm, optimizing the candidate test point set according to the component fault data and the fault propagation path to generate an optimal testability scheme.

[0008] Further, the component fault data includes pin count, repair time, repair cost, rectification time, rectification cost, reliability data, and failure rate.

[0009] Further, the S2 specifically includes: traversing the multi-level signal flow graph, analyzing signal transmission paths between components in the complex product perception system, and analyzing logical relationships between the components; Based on the signal transmission path and the logical relationship, the nodes that meet the preset conditions are identified as candidate test points to form the candidate test point set.

[0010] Further, the S3 specifically includes: S31, initializing a population, the population consisting of multiple individuals, each individual representing a test point selection scheme and a test sequence in a hybrid coding manner; S32, calculating the fitness value of each individual based on the component fault data and the fault propagation path; S33, performing genetic operations according to the fitness value to generate a child population; S34, iteratively performing steps S32-S33 until the convergence condition is met, outputting the test point set and the test sequence corresponding to the individual with the highest fitness value as the optimal testability scheme.

[0011] Further, the fitness value is expressed as: F = w1·F cover +w2·F cost +w3·F time +w4·F iso +w5·F robust Wherein, F represents the fitness value; F cover represents the fault coverage; w1 represents the weight coefficient of F cover ; F cost represents the test cost evaluation value; w2 represents the weight coefficient of F cost ; F time represents the test time evaluation value; w3 represents the weight coefficient of F time ; F isorepresents the fault isolation capability evaluation value; w4 represents the weight coefficient of F iso robust represents the robustness evaluation value; w5 represents the weight coefficient of F robust .

[0012] Further, the fault coverage F cover is represented as: F cover =∑ i ∑ j TP i ×M j ×C ij ) / (N fault ×N test ) wherein TP i represents whether the ith test point is enabled, and TP i ∈{0, 1}, when TP i =0 is disabled, and when TP i =1 is enabled; M j represents whether the jth test scheme is enabled, and M j ∈{0, 1}, when M j =0 is disabled, and when M j =1 is enabled; C ij represents the number of faults that can be detected by the ith test point using the jth test scheme; N fault represents the total number of faults; N test represents the total number of test combinations, wherein 1 test point and the test scheme selected therefrom constitute 1 test combination.

[0013] Further, the test cost evaluation value F cost is represented as: F cost =1-(C actual / C max ) C actual =∑ i (TP i ×C TPi )+∑ j (M j ×C Mj ) wherein C actual represents the actual cost of the current test scheme; C max represents the maximum allowable cost; TP i represents whether the ith test point is enabled, and TP i ∈{0, 1}, when TP i =0 is disabled, and when TP i =1 is enabled; C TPi ​Ci represents the cost of the ith test point; C Mj Cj represents the cost of the jth test scheme.

[0014] Further, the test time evaluation value F time is represented as: F time =1-(T actual / T max ) T actual =max j (∑ i TP i ×t ij ) wherein T actual represents the actual test time of the current test scheme; T max represents the maximum allowed time; TP i represents whether the ith test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, and when TP i =1 is enabled; t ij represents the time of using the jth test scheme at the ith test point.

[0015] Further, the fault isolation capability evaluation value F iso is represented as: F iso =(∑ k I k ) / N fault wherein I k represents whether the fault k can be isolated to the specified range, I k =0 represents that the fault k is not isolated to the specified range, I k =1 represents that the fault k is isolated to the specified range; Nfault represents the total number of faults.

[0016] Further, the robustness evaluation value F robust is represented as: F robust =1-(∑ i ∑ j R ij ×TP i ×M j ) / (∑ i ∑ j TP i ×M j ) wherein R ij represents the failure rate of the test combination (i,j); TP i represents whether the ith test point is enabled, and TPi ∈{0,1}, when TP i =0 is disabled, when TP i =1 is enabled; M j represents whether the jth test scheme is enabled, and M j ∈{0,1}, when M j =0 is disabled, when M j =1 is enabled.

[0017] Through the technical solutions described above, compared with the prior art, the present disclosure provides a complex product testability scheme heuristic generation method based on digital twinning, which has the following beneficial effects: In the testability scheme generation process, the present disclosure combines digital twinning technology and heuristic algorithms to achieve coordinated improvement of test efficiency, fault coverage, and resource utilization. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0019] Figure 1 The flowchart of the complex product testability scheme heuristic generation method based on digital twinning provided in the embodiments of the present disclosure.

[0020] Figure 2 The schematic diagram of the complex product perception system framework provided in the embodiments of the present disclosure.

[0021] Figure 3 The basic function schematic diagram of the fault function module provided in the embodiments of the present disclosure.

[0022] Figure 4 The entry schematic diagram of the fault function module provided in the embodiments of the present disclosure.

[0023] Figure 5 The switch logic schematic diagram provided in the embodiments of the present disclosure.

[0024] Figure 6 The AND gate logic schematic diagram provided in the embodiments of the present disclosure.

[0025] Figure 7 The multi-level signal flow schematic diagram provided in the embodiments of the present disclosure.

[0026] Figure 8 The optimal testability scheme generation schematic diagram provided in the embodiments of the present disclosure.

[0027] Figure 9 A perception system testability scheme report schematic diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0029] An embodiment of the present application discloses a complex product testability scheme heuristic generation method based on digital twinning, as shown in Figure 1 The method comprises the following steps: S1, constructing a digital twinning model of a complex product perception system, wherein the digital twinning model is integrated with component fault data and a multi-level signal flow graph; S2, analyzing a fault propagation path based on the multi-level signal flow graph, and determining a candidate test point set; S3, using an improved genetic algorithm to optimize the candidate test point set according to the component fault data and the fault propagation path, and generating an optimal testability scheme.

[0030] Next, each of the above steps will be described in detail.

[0031] In the above step S1, the composition of the complex product perception system is as shown in Figure 2 The complex product perception system mainly comprises core modules such as a laser radar, a camera, a millimeter wave radar, an IMU (inertial measurement unit), a data processing unit, and a communication link; in an embodiment of the present application, a digital twinning model of the complex product perception system is constructed, wherein the digital twinning model is integrated with component fault data and a multi-level signal flow graph; wherein: (1) Component fault data The component fault data comes from a component fault function module, and the basic functions of the fault function module are as shown in Figure 3 The component fault data specifically comprises pin count, repair time, repair cost, rectification time, rectification cost, reliability data, and fault rate; The components of the complex product perception system may have multiple fault modes due to complex working environments and various task requirements. Taking a sensor as an example: Common failure modes of optical sensors include lens contamination, image blur, sensor damage, etc. Lens contamination can be caused by complex products operating in harsh environments, with dust, water vapor and other pollutants adhering to the lens surface, affecting the transmission and focusing of light, resulting in a decrease in image quality, blurring, increased noise and other problems. According to statistics, about 30% of the optical sensor failures of unmanned aerial vehicles operating in the field environment are caused by lens contamination. Image blur can be caused by lens contamination, focusing system failure, etc. In addition to lens contamination, image blur can also be caused by focusing system failure, which cannot accurately adjust the focal length, resulting in unclear target objects, affecting target recognition and analysis. Sensor damage can be caused by external impact, overvoltage, overheating, etc. The internal components of the sensor are damaged, which cannot work normally. This failure mode accounts for about 15% of sensor failures.

[0032] Failure modes that may occur in infrared sensors include decreased sensitivity, increased measurement error, and detector failure. Decreased sensitivity is usually caused by long-term use of the sensor, internal component aging, resulting in reduced sensitivity to infrared radiation, and inability to accurately detect the thermal information of the target object. In some complex products that perform monitoring tasks for a long time, about 20% of infrared sensors will have decreased sensitivity after one year of use. Increased measurement error can be caused by changes in environmental temperature, humidity, etc., affecting the measurement accuracy of the sensor, resulting in a deviation between the measured value and the actual value. Detector failure is caused by quality problems of the detector itself or severe electromagnetic interference, etc., so that the detector cannot work normally and cannot output effective infrared signals.

[0033] In addition, there are many failure risks in data transmission lines, such as signal interruption, data loss, signal interference, etc. Signal interruption can be caused by line aging, loose joints, physical damage, etc., resulting in a disconnected data transmission channel, and the data collected by the sensor cannot be transmitted to the data processing unit. In some complex products operating in complex terrain environments, signal interruption failures often occur due to the line being easily pulled by external forces, accounting for about 35% of data transmission line failures. Data loss can be caused by noise interference during transmission, transmission protocol errors, data buffer overflow, etc., resulting in the loss of some data during transmission, affecting the integrity and accuracy of the data. Signal interference is usually caused by strong electromagnetic interference sources around, such as communication base stations, high-voltage lines, etc., which interfere with the data transmission signal, causing data errors or garbled codes.

[0034] The components of the perception system and the failure modes and failure phenomena are shown in Table 1 below.

[0035] Table 1: Components of the perception system and failure modes and failure phenomena

[0036] In actual operation, according to the component assembly fault analysis, the component assembly fault data is entered. The entry schematic diagram of the fault function module is shown in Figure 4 .

[0037] (2) Multi-level signal flow chart: The multi-level signal flow chart is used to describe the signal transmission path and logical relationship between each component in the system; wherein, the logical relationship is shown in Figure 5 and Figure 6 , the switch mode is set, the defined mode can be added through the defined mode drop-down box, or the mode name to be added is input in the defined mode drop-down box; the AND gate needs to set the critical value. If the number of 1 / connection lines > critical value, the AND gate is turned on; if the number of 1 / connection lines ≤ critical value, the AND gate is not turned on.

[0038] When drawing the multi-level signal flow chart of the sensing system components of a complex product, first, understand the structure and working principle of the sensing system, and clarify the signal transmission relationship between each component. Take the sensing system of an unmanned off-road vehicle as an example, which mainly includes laser radar, optical sensor, millimeter wave radar, IMU (inertial measurement unit), communication link, data processing unit and other components.

[0039] The optical sensor is responsible for collecting visible light image information, and the output analog image signal is transmitted to the image signal conditioning circuit through a dedicated data transmission line. In the image signal conditioning circuit, the analog image signal is amplified, filtered and other preprocessing operations to convert it into a digital image signal suitable for subsequent processing, and then the digital image signal is transmitted to the data processing unit. The data processing unit uses image processing algorithms to analyze and process the digital image signal and extracts the target information in the image.

[0040] The laser radar measures the distance and position information of the target object by emitting laser beams and receiving reflected light. The signal processing process of the laser radar is relatively complex, the laser signal emitted by the laser radar is received by the laser radar receiving module after being reflected by the target, and then a series of signal processing and calculation are performed to obtain the distance, angle and other information of the target object. These information are transmitted to the data processing unit in the form of digital signal through the data transmission line, and are fused with the data of other sensors.

[0041] The signal transmission path is of significant guiding importance in test design. When determining test points, key nodes can be selected for testing based on the signal path. Data transmission line nodes are critical channels for signal transmission; testing them effectively verifies the integrity and accuracy of signal transmission. Faults in data transmission lines, such as short circuits, open circuits, or signal interference, can lead to signal loss or errors. By setting test points at these nodes, faults can be detected and located promptly. Testing signal conditioning circuit nodes verifies the effectiveness of signal preprocessing, ensuring that the signal input to the data processing unit meets requirements. Faults in the signal conditioning circuit may cause signal distortion or excessive noise, affecting the accuracy of data processing. Testing allows for timely detection and resolution of these problems.

[0042] Based on the above signal transmission relationships, the multi-level signal flow graph is drawn as follows: Figure 7 As shown.

[0043] In step S2 above, the fault propagation path is analyzed based on the multi-level signal flow graph to determine the candidate test point set. Specifically, the multi-level signal flow graph is traversed to analyze the signal transmission path between the components in the complex product perception system and to parse the logical relationship between the components. Based on the signal transmission path and logical relationship, nodes that meet the preset conditions are identified as candidate test points to form the candidate test point set. The preset conditions are that they can monitor signal integrity, characterize the functional status of the components, or are located on the fault propagation path.

[0044] In step S3 above, based on the "multi-objective optimization requirements" (maximizing fault coverage, minimizing test cost, and minimizing test time) generated by the perception system testability scheme, an improved genetic algorithm is selected as the core algorithm. This algorithm possesses the ability to balance global search and local optimization in combinatorial optimization problems and can adapt to the topological characteristics of multi-signal flow graphs through coding design. Based on the improved genetic algorithm, the candidate test point set is optimized according to component fault data and fault propagation paths to generate the optimal testability scheme; specifically including: S31. Based on the multi-signal flow graph and FMEA results of the sensing system, determine the candidate test point set, and randomly generate 50-100 hybrid-coded individuals to form the initial population; the population consists of multiple individuals, and each individual uses a hybrid coding method to represent the test point selection scheme and test sequence; S32. Based on component failure data and failure propagation paths, calculate the fitness value for each individual; specifically, the fitness value is expressed as: F = w1·F cover +w2·F cost +w3·F time +w4·F iso +w5·F robust Wherein, F represents fitness value; F cover represents fault coverage; w1 represents weight coefficient of F cover ; F cost represents test cost evaluation value; w2 represents weight coefficient of F cost ; F time represents test time evaluation value; w3 represents weight coefficient of F time ; F iso represents fault isolation capability evaluation value; w4 represents weight coefficient of F iso ; F robust represents robustness evaluation value; w5 represents weight coefficient of F robust . In the embodiment of the present application, values w1=0.3, w2=0.2, w3=0.1, w4=0.2, w5=0.2 can be set.

[0045] The fault coverage F cover is represented as: F cover =(∑ i ∑ j TP i ×M j ×C ij ) / (N fault ×N test ) Wherein, TP i represents whether the ith test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, and when TP i =1 is enabled; M j represents whether the jth test scheme is enabled, and M j ∈{0,1}, when M j =0 is disabled, and when M j =1 is enabled; C ij represents the number of faults that can be detected by the ith test point using the jth test scheme; N fault represents total number of faults; N test represents total number of test combinations, wherein, 1 test point and the test scheme selected by it constitute 1 test combination.

[0046] The test cost evaluation value F cost is represented as: F cost =1-(C actual / C max ) C actual =∑ i (TP i ×C TPi )+∑ j (Mj x C Mj ) wherein C actual represents the actual cost of the current test plan; C max represents the maximum allowed cost; TP i represents whether the ith test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i =1 is enabled; C TPi represents the cost of the ith test point; C Mj represents the cost of the jth test plan.

[0047] The above test time evaluation value F time is represented as: F time =1-(T actual / T max ) T actual =max j (∑ i TP i x t ij ) wherein T actual represents the actual test time of the current test plan; T max represents the maximum allowed time; TP i represents whether the ith test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i =1 is enabled; t ij represents the time of using the jth test plan at the ith test point.

[0048] The above fault isolation capability evaluation value F iso is represented as: F iso =(∑ k I k ) / N fault wherein I k represents whether the fault k can be isolated to the specified range, I k =0 represents that the fault k is not isolated to the specified range, I k =1 represents that the fault k is isolated to the specified range; Nfault represents the total number of faults.

[0049] The above robustness evaluation value F robust is represented as: F robust =1-(∑ i ∑j R ij ×TP i ×M j ) / (∑ i ∑ j TP i ×M j ) Among them, R ij Indicates the failure rate of the test combination (i,j); TP i This indicates whether the i-th test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i Enabled when =1; M j Indicates whether the j-th test plan is enabled, and M j ∈{0,1}, when M j It is disabled when M = 0, and disabled when M = 0. j Enabled when =1.

[0050] S33. Perform genetic operations based on fitness values ​​to generate a progeny population; these genetic operations include selection, crossover, and mutation. Compared to the basic genetic algorithm, the improved genetic algorithm proposed in this invention has the following improvements: (1) Selection operation: In this embodiment of the invention, the selection operation adopts a "roulette wheel selection + elite retention" strategy. The roulette wheel selection selects the parent generation according to the fitness value probability. At the same time, the elite retention improvement strategy can enable the top 10% of high fitness individuals to directly enter the offspring, avoiding the loss of excellent genes. (2) Cross operation: In this embodiment of the invention, the binary segment adopts "single-point crossover", randomly selecting crossover points to exchange test point selection information; the integer segment adopts an improved crossover strategy of "partial mapping crossover (PMX)", which reduces pattern destruction through mapping relationship, exchanges test sequence fragments and adjusts conflict numbers to ensure sequence legality; the crossover probability is set to 0.8. (3) Mutation operation: In this embodiment of the invention, the binary segment uses "bit flipping", randomly flipping 0 / 1 to adjust the selection of test points; the integer segment uses "adjacent swapping", randomly swapping the numbers of two test points to adjust the test sequence; the mutation probability is set to 0.01-0.05 to balance the diversity and stability of the search.

[0051] S34. Iterate through steps S32-S33 until the convergence condition is met, and output the test point set and test sequence corresponding to the individual with the highest fitness value as the optimal test scheme; wherein, the convergence condition can be set to the change of the optimal fitness value of the population being less than 0.01 for 10 consecutive generations, or the number of iterations reaching a preset value.

[0052] A schematic diagram of the optimal testability scheme generation is shown below. Figure 8 As shown, the optimal test point set is: test point 2 (laser emitter power detection), test point 7 (scanning motor current detection), test point 12 (data processing unit output delay detection), and test point 15 (signal receiver signal-to-noise ratio detection); the test sequence is: test point 2 → test point 7 → test point 15 → test point 12; the scheme indicators are: fault coverage of 95% (covering 19 / 20 faults), total test cost reduced by 32% (compared to the full test point scheme), and total test time shortened by 40% (total time 12 minutes).

[0053] The corresponding schematic diagram of the perception system test scheme report is as follows: Figure 9 As shown.

[0054] A complete formula system can systematically optimize equipment testability design schemes, find the best balance point among multiple objectives such as coverage, cost, and time, and adjust the weight coefficients and constraints according to the specific equipment type in practical applications.

[0055] In summary, this invention provides a heuristic generation method for complex product testability solutions based on digital twins. Combining the core advantages of heuristic genetic algorithms—strong global search capability and low dependence on specific problems—it can effectively handle complex and nonlinear problems. For the analysis and calculation of complex signal flow graphs with multiple signal transmissions in complex product structures, it has significant effects through iterative optimization via selection, crossover, and mutation. It can combine multiple optimization objectives to generate testability solutions with a fault coverage rate of 95% in a short time, shortening the solution design cycle to 1-2 days. It can achieve the target requirements that are difficult to achieve manually, rapidly iteratively optimize complex product designs, shorten development time, and improve product fault detection rate, isolation rate, and other indicators.

[0056] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0057] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A heuristic method for generating testable solutions for complex products based on digital twins, characterized in that, Includes the following steps: S1. Construct a digital twin model of a complex product perception system, wherein the digital twin model integrates component fault data and multi-level signal flow graphs; S2. Based on the multi-level signal flow graph, analyze the fault propagation path and determine the candidate test point set; S3. Using an improved genetic algorithm, optimize the candidate test point set based on the component failure data and the failure propagation path to generate the optimal testability scheme.

2. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 1, characterized in that, The component fault data includes the number of pins, repair time, repair cost, rectification time, rectification cost, reliability data, and failure rate.

3. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 1, characterized in that, S2 specifically includes: Traverse the multi-level signal flow graph, analyze the signal transmission paths between components in the complex product sensing system, and parse the logical relationships between components. Based on the signal transmission path and logical relationship, nodes that meet the preset conditions are identified as candidate test points, forming the candidate test point set.

4. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 2, characterized in that, S3 specifically includes: S31. Initialize the population, which consists of multiple individuals, each of which uses a hybrid encoding method to represent the test point selection scheme and the test sequence; S32. Based on the component failure data and the failure propagation path, calculate the fitness value of each individual; S33. Perform genetic operations based on the fitness value to generate a progeny population; S34. Iterate through steps S32-S33 until the convergence condition is met, and output the test point set and test sequence corresponding to the individual with the highest fitness value as the optimal testability scheme.

5. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 4, characterized in that, The fitness value is expressed as: F=w1·F cover +w2·F cost +w3·F time +w4·F iso +w5·F robust Where F represents the fitness value; F cover Indicates fault coverage; w1 represents F cover Weighting coefficients; F cost w2 represents the estimated test cost; w2 represents F cost Weighting coefficients; F time w3 represents the test time evaluation value; w3 represents F time Weighting coefficients; F iso w4 represents the fault isolation capability assessment value; iso Weighting coefficients; F robust w5 represents the robustness assessment value; w5 represents F robust The weighting coefficients.

6. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 5, characterized in that, The fault coverage F cover Represented as: F cover =(∑ i ∑ j TP i ×M j ×C ij ) / (N fault ×N test ) Among them, TP i This indicates whether the i-th test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i Enabled when =1; M j Indicates whether the j-th test plan is enabled, and M j ∈{0,1}, when M j It is disabled when M = 0, and disabled when M = 0. j Enabled when =1; C ij N represents the number of faults that can be detected at the i-th test point using the j-th test plan; fault N represents the total number of faults. test This represents the total number of test combinations, where one test point and its selected test plan constitute one test combination.

7. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 5, characterized in that, The test cost assessment value F cost Represented as: F cost =1-(C actual / C max ) C actual =∑ i (TP i ×C TPi )+∑ j (M j ×C Mj ) Among them, C actual Indicates the actual cost of the current testing plan; C max Indicates the maximum permissible cost; TP i This indicates whether the i-th test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i Enabled when =1; C TPi C represents the cost of the i-th test point; Mj This represents the cost of the j-th test plan.

8. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 5, characterized in that, The test time evaluation value F time Represented as: F time =1-(T actual / T max ) T actual =max j (∑ i TP i ×t ij ) Among them, T actual Indicates the actual test time of the current test plan; T max Indicates the maximum allowed time; TP i This indicates whether the i-th test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i Enabled when =1; t ij This represents the time taken to use the j-th test plan at the i-th test point.

9. The heuristic generation method for complex product testability solutions based on digital twins as described in claim 5, characterized in that, The fault isolation capability assessment value F iso Represented as: F iso =(∑ k I k ) / N fault Among them, I k Indicates whether fault k can be isolated to a specified range, I k =0 indicates that fault k was not isolated to the specified range, I k =1 indicates that fault k is isolated to a specified range; Nfault represents the total number of faults.

10. The heuristic generation method for testability solutions of complex products based on digital twins as described in claim 5, characterized in that, The robustness evaluation value F robust Represented as: F robust =1-(∑ i ∑ j R ij ×TP i ×M j ) / (∑ i ∑ j TP i ×M j ) Among them, R ij Indicates the failure rate of the test combination (i,j); TP i This indicates whether the i-th test point is enabled, and TP i ∈{0,1}, when TP i =0 is disabled, when TP i Enabled when =1; M j Indicates whether the j-th test plan is enabled, and M j ∈{0,1}, when M j It is disabled when M = 0, and disabled when M = 0. j Enabled when =1.

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