Method and system for compensating warping of glass substrate in advanced packaging

Abstract

The invention provides a warping compensation method and system for a glass substrate in advanced packaging. The method comprises the following steps: acquiring an initial design layout and an original interconnection node list of a chip; performing reverse geometric correction on the original interconnection node list according to the initial design layout of the chip and the warping distribution data of the substrate to obtain a compensated interconnection node list; according to the compensated interconnection node list, generating an intermediate state GDS layout containing a corrected interconnection node graph; and according to the compensated interconnection node list and the intermediate state GDS layout, performing automatic wiring adaptive to the substrate warping form. According to the method, through a'design left shift 'strategy, the interconnection node list is subjected to geometric correction in advance before the wiring stage, so that the designed glass substrate can be accurately aligned with the chip pins after being subjected to manufacturing warping, and the design efficiency and the packaging yield are remarkably improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit electronic design automation, and more specifically, to a method and system for compensating for glass substrate warpage in advanced packaging. Background Technology

[0002] With the development of semiconductor technology, 2.5D / 3D advanced packaging technology has become crucial for improving chip performance. Glass substrates, due to their excellent high-frequency electrical characteristics and dimensional stability, have attracted significant attention in adapter board applications. Through-glass vias (TGVs), vertical electrical interconnects that penetrate glass substrates, are a key technology for achieving three-dimensional integration on glass substrates, leading the transition of semiconductor packaging from the "silicon-based era" to the "glass-based era."

[0003] However, in actual manufacturing processes, glass substrates are prone to warping under high-temperature conditions due to factors such as mismatched coefficients of thermal expansion. In traditional chip back-end design flows, designers typically assume the substrate is an ideal plane and design bumps and redistribution layers according to ideal coordinates. During tape-out manufacturing, if physical warping occurs on the substrate, the actual manufactured bump positions will deviate from the designed positions, causing misalignment between chip pins and substrate pads. In severe cases, this can lead to connection failures and reduced yield.

[0004] Existing solutions typically involve process adjustments at the manufacturing stage or complex post-processing corrections after the design is completed. This not only increases the design iteration cycle but may also cause design rule checks to re-report errors. Therefore, there is an urgent need for a design methodology that can detect and compensate for warpage effects early in the design phase (i.e., "design left shift").

[0005] A search revealed a patent with publication number CN117790388A, which discloses a laser-assisted bonding method, system, and semiconductor equipment for chips. The method includes providing a database of previously bonded chips; acquiring the original MAP (Modular Map) image, a compensated MAP image, and the first parameters of the chip to be bonded; calculating the target MAP image of the chip to be bonded; determining whether the acquired first parameters of the chip to be bonded are consistent with the first parameters of previously bonded chips; if consistent, retrieving the illumination parameters and illumination mode from the original database; and bonding the chips to be bonded, which can perfectly improve the warpage problem during chip bonding. This technology mainly compensates for process deviations during the manufacturing (bonding) stage by adjusting equipment parameters (such as illumination parameters and illumination mode). This method is a "post-manufacturing" remedial measure. It heavily relies on the adjustment capability of the bonding equipment. If the substrate warpage deformation is large, exceeding the adjustment window of the process parameters, adjusting the illumination parameters alone is insufficient to completely correct alignment deviations. Furthermore, this method increases the complexity of manufacturing process debugging.

[0006] Furthermore, patent application CN120056359A discloses a packaging method for RF SOI chips. This method involves real-time monitoring and analysis of packaging data, combining edge detection algorithms and thermal gradient calculations to accurately identify warpage and stress concentration areas. The generated deformation model dynamically reflects the deformation distribution during the packaging process. By integrating the deformation model, process parameters, and historical packaging data, a compensation algorithm dynamically generates multiple compensation strategies, simulates and evaluates them, and selects the optimal solution, significantly improving packaging stability and adaptability. This technology focuses on real-time monitoring, analysis, and dynamic strategy generation during the packaging process. This method requires the introduction of complex edge detection and thermal gradient calculation systems on the production line, belonging to "online feedback control." This not only increases the time and equipment costs in the manufacturing process but also primarily addresses the thermal gradient problem of RF SOI chips. For hard and brittle materials like glass substrates, the real-time adjustment methods for overall geometric warpage occurring at large sizes are limited, making it difficult to fundamentally eliminate the misalignment between design coordinates and actual physical positions. Summary of the Invention

[0007] In view of one of the defects in the prior art, the purpose of this application is to provide a method and system for compensating for glass substrate warpage in advanced packaging.

[0008] According to a first aspect of this application, a method for compensating for glass substrate warpage in advanced packaging is provided, comprising: Obtain the initial chip design layout and original interconnect node list; Based on the initial chip design layout and substrate warpage distribution data, the original interconnect node list is subjected to reverse geometric correction to obtain a compensated interconnect node list. Based on the compensated interconnect node list, an intermediate GDS layout containing the corrected interconnect node graph is generated; Automatic routing is performed to adapt to the substrate warping morphology based on the compensated interconnect node list and the intermediate GDS layout.

[0009] Optionally, the initial chip design layout includes a list of initial bump locations in the original interconnect node list.

[0010] Optionally, the warpage distribution data of the substrate is warpage prediction data obtained based on finite element simulation, or warpage deformation data based on actual process measurements.

[0011] Optionally, the step of performing reverse geometric correction on the original interconnect node list based on the initial chip design layout and substrate warp distribution data to obtain a compensated interconnect node list includes: Based on the warpage distribution data of the substrate, a warpage deformation field model of the substrate is established. Traverse the coordinates of each node in the original interconnection node list and query the physical deformation displacement corresponding to the coordinates in the warping deformation field model; Based on the physical deformation displacement, pre-compensation coordinates are determined so that the warped substrate approximates the initial design coordinates in the original interconnect node list. Based on the pre-compensated coordinates, a list of compensated interconnected nodes is generated.

[0012] Optionally, generating an intermediate GDS layout containing the corrected interconnect node graph based on the compensated interconnect node list includes: Based on the corrected coordinates, hierarchy definitions, and graphical attributes in the compensated interconnection node list, reconstruct the physical graphical data of the interconnection nodes; The physical graphics data is exported as a GDSII format file, which serves as the intermediate GDS layout.

[0013] Optionally, after performing automatic routing to adapt to the substrate warpage morphology based on the compensated interconnect node list and the intermediate GDS layout, the process includes: Generate the final manufacturing layout data; The manufacturing layout data is subjected to design rule checks and layout-to-principle analysis. Figure 1 Consistency test.

[0014] According to a second aspect of this application, an advanced packaging glass substrate warpage compensation system is provided, comprising: The data interface module is used to obtain the initial chip design layout and the original interconnect node list; The compensation calculation module is used to perform reverse geometric correction on the original interconnect node list based on the chip initial design layout and substrate warp distribution data to obtain a compensated interconnect node list. The layout generation module is used to generate an intermediate GDS layout containing the corrected interconnect node pattern based on the compensated interconnect node list. An automatic routing module is used to perform automatic routing adapted to the substrate warping shape based on the compensated interconnect node list and the intermediate GDS layout.

[0015] Optionally, the compensation calculation module operates as a point tool independent of the electronic design automation system; the electronic design automation system and the compensation calculation module interact with each other through a standardized file interface.

[0016] According to a third aspect of this application, a terminal is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, can be used to perform the method described thereon.

[0017] According to a fourth aspect of this application, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can be used to perform the method described thereon.

[0018] The advanced packaging glass substrate warpage compensation method provided in this application employs a "design left shift" strategy to pre-correct the interconnect node list geometrically before the routing stage, ensuring that the designed glass substrate is precisely aligned with the chip pins after manufacturing warpage. This method effectively solves the alignment problem caused by warpage in glass substrate packaging, avoids cumbersome back-end repair processes, and significantly improves design efficiency and packaging yield.

[0019] Other technical effects resulting from the additional features will be further illustrated in the corresponding embodiments. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart illustrating a glass substrate warpage compensation method in advanced packaging according to an exemplary embodiment; Figure 2 This is a schematic diagram illustrating the structure of a glass substrate warpage compensation system in an advanced package according to an exemplary embodiment; Figure 3 This is a schematic diagram of an intermediate state GDS layout according to an exemplary embodiment; Figure 4 This is a schematic diagram illustrating adaptive routing according to an exemplary embodiment; Figure 5 Comparison of S21 simulation results under glass substrate warping. Detailed Implementation

[0021] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all fall within the protection scope of the present application. Parts not described in detail in the following embodiments can be implemented using existing technology.

[0022] The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or devices.

[0023] In existing advanced chip packaging technologies, substrate warpage leads to low chip packaging alignment accuracy and high compensation costs. To address these issues, this application provides a glass substrate warpage compensation method for advanced packaging, thereby resolving these problems.

[0024] Reference Figure 1 As shown in one embodiment of this application, a method for compensating for glass substrate warpage in advanced packaging includes the following steps: S1. Obtain the initial chip design layout and original interconnect node list; S2. Based on the initial chip design layout and substrate warpage distribution data, reverse geometric correction is performed on the original interconnect node list to obtain a compensated interconnect node list. S3. Based on the list of compensated interconnect nodes, generate an intermediate GDS layout containing the corrected interconnect node graph. S4. Based on the list of compensated interconnect nodes and the intermediate GDS layout, perform automatic routing to adapt to the substrate warping morphology.

[0025] Specifically, the substrate is a glass through-hole adapter board; in step S1, the design environment is configured in the Electronic Design Automation (EDA) system. The configuration of the design environment includes setting inter-chip spacing rules, linewidth and line spacing rules, and power and ground grid rules. The original interconnect node list specifically refers to a list file containing the coordinate positions, network attributes, and other information of all I / O contacts (bumps / pads) on the chip or interposer layer.

[0026] The embodiments described above employ a "design-left shift" glass substrate warpage compensation design method. This method pre-corrects the interconnect node list geometrically before the wiring stage, ensuring that the designed glass substrate is precisely aligned with the chip pins after manufacturing warpage. This application overcomes the limitations of traditional manufacturing-end compensation by employing a pre-compensation method for glass substrate warpage in advanced packaging. This effectively solves the alignment problem caused by warpage in glass substrate packaging, avoids cumbersome back-end repair processes, and significantly improves design efficiency and packaging yield.

[0027] In order to achieve data acquisition, in some specific embodiments of this application, the initial chip design layout includes an initial bump location list in the original interconnect node list.

[0028] Specifically, the initial interconnect node list includes the initial design coordinates of the I / O contacts under the assumption of an ideal plane. The initial bump position list is a core component of the initial interconnect node list, referring to the set of coordinates under the ideal design coordinates without compensation. Initial layout data and substrate parameter information for the chip to be designed are obtained. The substrate parameter information includes the geometric dimensions and material physical properties of the glass substrate. Substrate parameters (such as Young's modulus, coefficient of thermal expansion, and thickness) are mainly used for simulation and path prediction. If warpage data is obtained through finite element simulation, these physical parameters must be input to calculate the deformation field. The acquired data and information are then imported into the electronic design automation system.

[0029] In order to obtain warpage distribution data of the substrate, in some specific embodiments of this application, the warpage distribution data of the substrate is warpage prediction data obtained based on finite element simulation, or warpage deformation data based on actual process measurements.

[0030] Specifically, the data obtained through these two methods is essentially the same, but the preprocessing differs. Simulation data is typically gridded continuous data covering the entire plate, allowing for the direct establishment of a deformation field model or through simple interpolation. Measured data, on the other hand, usually consists of discrete sample points, with a smaller number of points. This method is adaptable to data sources in different scenarios and has good compatibility.

[0031] It should be noted that if measured data is used, when establishing the warping deformation field model, a fitting or interpolation algorithm (such as surface fitting) needs to be added to transform the discrete measured points into a continuous displacement field covering the entire substrate area, so as to query the displacement at any coordinate.

[0032] To achieve warpage information modeling and compensation calculation, in some specific embodiments of this application, based on the initial chip design layout and substrate warpage distribution data, the original interconnect node list is subjected to reverse geometric correction to obtain a compensated interconnect node list, including: S21. Based on the warp distribution data of the substrate, establish a warp deformation field model of the substrate; S22. Traverse the coordinates of each node in the original interconnection node list and query the physical deformation displacement corresponding to the coordinates in the warping deformation field model. S23. Determine the pre-compensation coordinates based on the physical deformation displacement, so that the substrate warps and approaches the initial design coordinates. S24. Based on the pre-compensated coordinates, generate a list of compensated interconnected nodes.

[0033] Specifically, in step S2, the reverse geometry correction is performed as follows: read the original coordinates; query the physical offset at that location in the model; calculate the pre-compensation coordinates (i.e., perform reverse subtraction); and write the pre-compensation coordinates as new design coordinates into the list.

[0034] In S21, the warping deformation field model of the substrate includes the spatial displacement vector corresponding to each coordinate point (x, y) on the substrate plane. x, y, The model is built by: reading the nodal displacement data table (CSV / TXT) exported by the simulation software; or reading the sampling point data of the actual measuring equipment; and constructing a mapping function through software, which can return the offset of any position in the plane after being subjected to force.

[0035] Specifically, the mapping function is constructed based on interpolation or fitting algorithms. For example, algorithms such as bilinear interpolation and cubic spline interpolation can be used to construct a continuous displacement field by interpolating discrete nodal displacement data; or algorithms such as polynomial surface fitting and least squares can be used to fit discrete sampling point data into a smooth mathematical surface equation. This mapping function ultimately returns the offset of any coordinate point in the plane after force is applied.

[0036] In S22, the coordinates of each node are the initial design coordinates. The system needs to traverse each ideal coordinate (x, y) in the original interconnect node list as the index value for querying the warp model, so that the coordinates with the preset offset will eventually fall back to the ideal position of the initial design after physical warping, thus achieving alignment. This step calculates the position that each I / O contact should be offset in advance based on the amount of substrate warping, and performs point-to-point correction on the coordinates of each node, so that it can return to the original design position after actual warping, resulting in high alignment accuracy.

[0037] The specific process for determining the pre-compensation coordinates is as follows: Using the initial design coordinates (x, y) in the original interconnect node list as an index, the corresponding physical deformation displacement (Δx, Δy) is queried in the warping deformation field model. Based on the principle of reverse geometric correction, the pre-compensation coordinates (x', y') are calculated using the formulas: x' = x - Δx, y' = y - Δy. The calculated (x', y') are then written into the list as the corrected coordinates to offset the positive physical displacement generated during the manufacturing process.

[0038] Each node coordinate (initial design coordinate) in the original interconnect node list is replaced with the calculated pre-compensated coordinates to obtain a compensated interconnect node list. The program will traverse each row of data in the list and perform the above "query-calculate-replace" operation for each coordinate point, finally generating a new list file.

[0039] In the above embodiments of this application, the compensation calculation module is invoked to read the original interconnect node list and obtain the warpage distribution data of the target glass substrate under preset process conditions. Using the warpage distribution data, the position offset corresponding to each bump in the initial bump position list is calculated based on the inverse compensation algorithm through the preset warpage compensation algorithm. The pre-compensated coordinates are written into the compensated interconnect node list and output to generate a compensated interconnect node list containing the corrected coordinates.

[0040] To achieve layout pre-compensation updates, in some specific embodiments of this application, an intermediate GDS layout containing the corrected interconnect node pattern is generated based on the compensated interconnect node list, including: S31. Based on the corrected coordinates, hierarchical definitions, and graphical attributes in the compensated interconnection node list, reconstruct the physical graphical data of the interconnection nodes. S32. Export the physical graphics data as a GDSII format file as an intermediate GDS layout.

[0041] Specifically, "pre-compensated coordinates" focus on the calculation process, that is, the values ​​calculated by the algorithm; "corrected coordinates" focus on the result, that is, the final values ​​written into the final file and used to generate the layout. Numerically, "corrected coordinates" and "pre-compensated coordinates" are the same coordinates.

[0042] Layer Definition: Refers to the metal layer (e.g., Top Metal or RDL layer) where the bump / pad resides. Shape Attributes: Refers to the geometry (e.g., circle, octagon) and dimensions (diameter, side length) of the bump. Physical Graphical Data: Refers to the binary data stream conforming to the GDSII standard format after combining the above coordinates, layers, and shapes.

[0043] The specific reconstruction process is as follows: The script reads the "compensated interconnect node list"; for each node in the list, it calls the API of the EDA tool (or uses libraries such as GDSPy); a new Cell is created in the GDS file, or in an existing Cell, a new graphic object is drawn according to the new coordinates, combined with the original shape and hierarchy information. Logical connection points represent the target locations that the autorouter logically believes signal lines "should" be connected to. Under normal circumstances, logical connection points should be in the same location as the interconnect nodes and the "physical graphics" in the GDS layout. In conventional designs, the logical coordinates coincide with the center of the physical graphics. However, in this embodiment, because the interconnect nodes have been manually modified, if the layout data is not updated, their graphic positions on the layout will not match the list data in the interconnect nodes, making it impossible to generate "logical connection points," and the router will malfunction.

[0044] Because the autorouter needs to determine the physical locations of the "start point" and "end point" before drawing lines, the intermediate GDS layout generated in this step provides real physical anchor points for autorouter. The router reads these anchor points that have already undergone position corrections and connects them, thus ensuring that the generated lines naturally adapt to warping without the need for subsequent manual intervention.

[0045] The reconstructed data retains the same hierarchical definitions, graphical attributes (such as the shape and size of bumps), and network connection logic as the initial chip design layout data. The reconstructed data updates the center physical coordinates of interconnect nodes from "ideal design coordinates" to "pre-compensation coordinates", thereby achieving a pre-offset position in the layout that can compensate for manufacturing warpage.

[0046] In the above embodiments of this application, the initial bump position list is corrected according to the position offset to generate a compensated bump position list and update the layout data to ensure that the bump position in the routing environment is consistent with the logical connection point position. Thus, the compensated interconnect node list and the intermediate GDS layout can be jointly loaded into the electronic design automation system, and automatic routing is performed with the corrected coordinates as anchor points. After the routing anchor points are pre-offset, they can be restored to the target alignment position after experiencing actual three-dimensional warping deformation.

[0047] To enable post-routing verification, in some specific embodiments of this application, after performing automatic routing adapted to the substrate warpage based on the compensated interconnect node list and intermediate GDS layout, the following steps are included: S51. Generate the final manufacturing layout data; S52. Perform Design Rule Check (DRC) and layout / schematic analysis on manufacturing layout data. Figure 1 LVS (Likelihood and Safety Check).

[0048] In the embodiments described above, the compensated bump position list and the updated layout data are imported into an EDA tool (such as a placement and routing tool), and automatic routing and physical verification of the adapter board are performed based on the corrected bump coordinates to ensure the reliability of the compensation effect.

[0049] The "design left shift" method provided in the above embodiments of this application ensures that after the final layout is fabricated and physically warped, the bump position can be precisely aligned with the pins of the chip or substrate through physical deformation, which greatly improves the packaging yield and avoids repeated iterations caused by discovering alignment problems only after wiring is completed.

[0050] This application adopts a "design left shift" strategy, which is fundamentally different from existing technologies such as CN117790388A and CN120056359A that seek solutions at the manufacturing end. Specifically, it is reflected in: (1) Overcoming the limitations of process adjustment through pre-emptive prevention: This application intervenes in the EDA design stage and performs reverse geometric correction on the layout design data (GDSII) and interconnect node list based on simulation or measured data. This means that the reverse deformation amount has been "pre-set" in the design drawings before manufacturing begins; (2) Lowering the manufacturing threshold and overcoming manufacturing complexity: Since the layout already contains compensation information, the manufacturing end does not need to change the standard process flow, nor does it need to rely on expensive real-time monitoring equipment or special laser parameter debugging. It only needs to be produced according to the standard process, and the warped substrate can be naturally and accurately aligned with the chip pins; (3) Higher alignment accuracy: This application performs point-to-point digital precision correction of the coordinates of each I / O node. Compared with macroscopic process parameter adjustment, it can achieve micron-level or even higher precision alignment, which significantly improves the final yield of advanced glass substrate packaging.

[0051] Based on the same concept, another embodiment of this application provides a glass substrate warpage compensation system 100 in advanced packaging, referring to... Figure 2 As shown, it includes: Data interface module 110 is used to obtain the initial chip design layout and the original interconnect node list; The compensation calculation module 120 is used to perform reverse geometric correction on the original interconnect node list based on the chip initial design layout and the warp distribution data of the substrate, so as to obtain a compensated interconnect node list. The layout generation module 130 is used to generate an intermediate GDS layout containing the corrected interconnect node graphics based on the compensated interconnect node list. Automatic routing module 140 is used to perform automatic routing adapted to the substrate warping shape based on the compensated interconnect node list and intermediate GDS layout.

[0052] In some specific embodiments of this application, the compensation calculation module operates as a point tool independent of the electronic design automation (EDA) system; the EDA system and the compensation calculation module interact with each other through a standardized file interface. Furthermore, the compensation calculation module is configured to be compatible with the interface specifications of various EDA system main tools, capable of parsing and outputting interconnection node list files and auxiliary description files defined in different formats.

[0053] Specifically, standardized file interfaces include common text exchange formats (such as CSV, XML) for transmitting lists of interconnect node coordinates; and electronic design automation industry standard physical design exchange formats (such as GDSII, DEF, LEF) for interactive layout layer-level information.

[0054] The auxiliary description file mainly contains metadata required for resolving coordinates, including: unit definition; coordinate system origin definition; process parameters such as scaling factor (used to correct linear scaling changes caused by thermal expansion); and a hierarchical mapping table defining the specific metal layer name where the interconnection node is located.

[0055] The specific implementation techniques of each module / unit in the above examples of this application can be referred to the steps of the glass substrate warpage compensation method in the advanced packaging in the above embodiments, and will not be repeated here.

[0056] The preferred features in the above embodiments can be used individually in any embodiment, or in any combination thereof, provided they do not conflict with each other. Furthermore, parts not described in detail in the embodiments can be implemented using existing technologies.

[0057] The following examples and comparative examples will be used to further illustrate this application in order to better understand the above-mentioned technical solutions. It should be understood that the following are only some examples and are not intended to limit this application.

[0058] This embodiment takes the design of a 2.5D glass through-hole encapsulation adapter board as an example.

[0059] This embodiment provides an advanced packaging adapter board warpage compensation design method based on left-shifting design. This method eliminates the impact of substrate manufacturing deformation on chip interconnect alignment by introducing a pre-compensation mechanism before the physical implementation process. The specific process is as follows: Figure 1 As shown, it includes the following steps: Step S1: Design Initialization and Acquisition of Raw Data S1-1 Environment Configuration: Create a design project in the EDA main system, configure the page-level information and design rules, including the spacing between cores, line width and line spacing, and power and ground grid rules.

[0060] S1-2 Data Import: Imports the initial design layout of the chip and the original list of interconnect nodes without any compensation. The original interconnect node list records the initial design coordinates of thousands of I / O contacts under the assumption of an ideal plane. Step S2: Warp Compensation Calculation and List Update S2-1 Data Interaction: By calling the independent compensation calculation module, the original interconnect node list in step S1 is read, and the warpage distribution data of the target glass substrate under a specific process is received.

[0061] S2-2 Algorithm Processing: The compensation calculation module establishes a deformation mapping model based on the warp distribution data and calculates the displacement vector of each node in the original interconnect node list in actual manufacturing; subsequently, based on the reverse compensation algorithm, it calculates the preset offset coordinates required for each node to offset the deformation.

[0062] S2-3 List Output: The compensation calculation module outputs a list of compensated interconnected nodes containing corrected coordinate information and related auxiliary description files.

[0063] Step S3: Compensation layout generation S3-1 Layout Reconstruction: The EDA main system or auxiliary script tool reads the compensated interconnect node list output in step S2, and automatically generates an intermediate GDS layout containing the corrected interconnect node graphics based on the corrected coordinates, layer definitions, and graphic attributes in the list. Figure 3 As shown. This step ensures that the bump locations in the layout of the subsequent routing environment are strictly consistent with the compensated interconnect node list (bumplist) data.

[0064] Step S4: Automated cabling S4-1 Joint Loading: The compensated interconnect node list and the intermediate GDS layout are simultaneously loaded into the EDA master system's autorouter environment. At this point, the router obtains both the physical layer graphical reference and the logical layer connection point coordinates.

[0065] S4-2 Adaptive Routing: Import netlist information and start the automatic routing engine. The router uses the corrected interconnect node coordinates as anchor points for path planning and routing. The generated RDL and other connections will naturally adapt to the physical warp of the substrate, requiring no post-processing manual compensation or modification. Figure 4 As shown.

[0066] Verification and Output: After routing is completed, the final manufacturing layout data is generated, and design rule checks and layout-schematic verification are performed. Figure 1 Consistency checks were performed to ensure that the design data met the manufacturer's process requirements. For the wiring of the GSG-type signal channel obtained using this warp compensation design method in the embodiment, full-wave simulation was performed using a multiphysics simulator to obtain its S-parameter performance. Figure 5 The simulation results of S21 under glass substrate warping are shown, comparing the S21 parameters under ideal, mismatched, and compensated conditions. This verifies that the design data after compensation using the method of this application meets the manufacturer's process requirements. Compared with the S-parameter performance obtained by traditional design methods, the insertion loss in this application embodiment is improved by more than 25%.

[0067] It should be noted that for glass substrates of various materials (such as quartz glass, borosilicate glass, etc.) and their corresponding 2.5D / 3D packaging structures, as long as the substrate has predictable or measurable physical warpage (elastic deformation) during the manufacturing process, the method described in the above embodiments of this application can be used to achieve substrate warpage compensation.

[0068] Based on the same technical concept, in other embodiments of this application, a terminal is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it can be used to perform the method in any of the above embodiments, or to run the system in any of the above embodiments.

[0069] Based on the same technical concept, in other embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, can be used to perform the methods in any of the above embodiments, or to run the system in any of the above embodiments.

[0070] Optionally, the memory is used to store programs; the memory may include volatile memory, such as random-access memory (RAM), such as static random-access memory (SRAM), double data rate synchronous dynamic random-access memory (DDR SDRAM), etc.; the memory may also include non-volatile memory, such as flash memory. The memory is used to store computer programs (such as application programs and functional modules that implement the above methods), computer instructions, etc., and the aforementioned computer programs and computer instructions can be partitioned and stored in one or more memories. Furthermore, the aforementioned computer programs, computer instructions, data, etc., can be accessed by the processor.

[0071] The aforementioned computer programs, computer instructions, etc., can be stored in partitions within one or more memory locations. Furthermore, the aforementioned computer programs, computer instructions, data, etc., can be accessed by a processor.

[0072] A processor is used to execute a computer program stored in memory to implement the various steps of the methods involved in the above embodiments. For details, please refer to the relevant descriptions in the preceding method embodiments.

[0073] The processor and memory can be separate structures or integrated structures. When the processor and memory are separate structures, they can be coupled together via a bus.

[0074] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0077] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0078] The foregoing has described some specific embodiments of this application. It should be understood that this application is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the substantive content of this application. The above-described preferred features can be used in any combination without conflict.

Claims

1. A method for compensating for glass substrate warpage in advanced packaging, characterized in that, include: Obtain the initial chip design layout and original interconnect node list; Based on the initial chip design layout and substrate warpage distribution data, the original interconnect node list is subjected to reverse geometric correction to obtain a compensated interconnect node list. Based on the compensated interconnect node list, an intermediate GDS layout containing the corrected interconnect node graph is generated; Automatic routing is performed to adapt to the substrate warping morphology based on the compensated interconnect node list and the intermediate GDS layout.

2. The glass substrate warpage compensation method in advanced packaging according to claim 1, characterized in that, The initial chip design layout includes a list of initial bump locations from the original interconnect node list.

3. The glass substrate warpage compensation method in advanced packaging according to claim 1, characterized in that, The warpage distribution data of the substrate is warpage prediction data obtained from finite element simulation, or warpage deformation data obtained from actual process measurements.

4. The glass substrate warpage compensation method in advanced packaging according to claim 1, characterized in that, The step involves performing reverse geometric correction on the original interconnect node list based on the initial chip design layout and substrate warp distribution data to obtain a compensated interconnect node list, including: Based on the warpage distribution data of the substrate, a warpage deformation field model of the substrate is established. Traverse the coordinates of each node in the original interconnection node list and query the physical deformation displacement corresponding to the coordinates in the warping deformation field model; Based on the physical deformation displacement, pre-compensation coordinates are determined so that the warped substrate approximates the initial design coordinates in the original interconnect node list. Based on the pre-compensated coordinates, a list of compensated interconnected nodes is generated.

5. The glass substrate warpage compensation method in advanced packaging according to claim 1, characterized in that, The step of generating an intermediate GDS layout containing the corrected interconnect node graph based on the compensated interconnect node list includes: Based on the corrected coordinates, hierarchy definitions, and graphical attributes in the compensated interconnection node list, reconstruct the physical graphical data of the interconnection nodes; The physical graphics data is exported as a GDSII format file, which serves as the intermediate GDS layout.

6. The glass substrate warpage compensation method in advanced packaging according to claim 1, characterized in that, After performing automatic routing to adapt to the substrate warpage morphology based on the compensated interconnect node list and the intermediate GDS layout, the process includes: Generate the final manufacturing layout data; The manufacturing layout data is subjected to design rule checks and consistency checks between the layout and the schematic diagram.

7. A glass substrate warpage compensation system for advanced packaging, characterized in that, include: The data interface module is used to obtain the initial chip design layout and the original interconnect node list; The compensation calculation module is used to perform reverse geometric correction on the original interconnect node list based on the chip initial design layout and substrate warp distribution data to obtain a compensated interconnect node list. The layout generation module is used to generate an intermediate GDS layout containing the corrected interconnect node pattern based on the compensated interconnect node list. An automatic routing module is used to perform automatic routing adapted to the substrate warping shape based on the compensated interconnect node list and the intermediate GDS layout.

8. The glass substrate warpage compensation system in advanced packaging according to claim 7, characterized in that, The compensation calculation module operates as a point tool independent of the electronic design automation system; the electronic design automation system and the compensation calculation module interact with each other through a standardized file interface.

9. A terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it can be used to perform the method of any one of claims 1-6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, this program can be used to perform the method of any one of claims 1-6.

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