A high-density BGA arc automatic routing method and device considering forbidden area constraint

Abstract

The application discloses a high-density BGA arc automatic wiring method and device considering forbidden area constraint, and relates to the technical field of printed circuit board wiring. The method comprises the following steps: acquiring wiring data of a printed circuit board, wherein the wiring data comprises netlist information, ball grid array pin information, design rules and forbidden area constraint; generating a point set and an edge set of a wiring graph to obtain a graph model; generating a preliminary wiring path by using a maze algorithm, and performing arc conversion processing; executing an optimization scheme to obtain final differential line layout data. The application realizes high-speed differential pair automatic arc wiring oriented to the forbidden area, and completely replaces the traditional mode of relying on manual piecewise adjustment.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board routing technology, and in particular to a high-density BGA arc-shaped automatic routing method and apparatus that takes into account the constraints of no-wiring areas. Background Technology

[0002] With the rapid development of 5G communication, AI accelerators, and high-performance computing systems, the data transmission rate of differential signals in ball grid array (BGA) packages has exceeded 56Gbps, placing stringent requirements on the signal integrity and electromagnetic compatibility of printed circuit board (PCB) wiring technology. Differential signals transmit complementary signals through a pair of copper wires, effectively suppressing noise and serving as a core solution for high-speed transmission.

[0003] Ball grid array (BGA) escape routing is a core aspect of printed circuit board (PCB) design. Its function is to guide signals from the BGA pins to the package boundaries, directly impacting the performance of high-speed systems. In BGA escape routing design, the placement of keep-out zones is a critical prerequisite for ensuring system performance. This is because high-speed differential signals have extremely high requirements for signal path integrity, reference plane continuity, and electromagnetic environment stability during transmission. Random routing in specific areas can easily lead to signal crosstalk, impedance abrupt changes, and signal reflection, severely compromising signal integrity. Therefore, keep-out zones are typically set up to physically isolate and prevent signal interference, ensuring the purity of differential signal transmission.

[0004] The existence of the cannibalization zone significantly increases the design difficulty of escape routing for ball grid arrays. Ball grid array packages already have extremely high pin density, and the available space for escape routing is already very limited. The cannibalization zone further compresses the routing channels, making already scarce routing resources even more limited. Designers often need to repeatedly adjust routing paths, and may even need to sacrifice some non-critical signal routing optimizations to avoid the cannibalization zone. This not only increases the design cycle but also places higher demands on the experience and technical skills of designers, further highlighting the adaptation bottleneck of existing mainstream routing technologies in ultra-high-speed scenarios. Summary of the Invention

[0005] To address the problems of existing technologies, such as signal issues arising from 45-degree zigzag paths and conflicts with no-go zones, as well as the low efficiency and error-prone nature of curved routing due to manual intervention, this invention provides a high-density BGA curved automatic routing method and apparatus that considers no-go zone constraints. The technical solution is as follows:

[0006] On the one hand, a high-density BGA arc-shaped automatic routing method considering no-load zone constraints is provided. This method is implemented by a high-density BGA arc-shaped automatic routing device considering no-load zone constraints, and includes an information module, a graph model module, a routing path module, and a routing scheme module. Its characteristic is that it includes: Information module: used to acquire wiring data of printed circuit boards, including netlist information, ball grid array pin information, design rules and no-hook constraints; Graph model module: used to generate a set of points and edges of the wiring diagram based on the positions of adjacent pins and the positions of the forbidden areas in the wiring data, thus obtaining a graph model; The routing path module is used to treat each differential pair as a single differential line of equivalent width based on the routing data and the graph model, determine the start and end nodes of the single differential line, generate a preliminary routing path using a maze algorithm, and perform arc transformation processing to transform the polylines in the preliminary routing path into arc-shaped traces, thereby obtaining an optimized routing scheme. Cabling scheme module: Based on the optimized cabling scheme, execute the optimization scheme to obtain the final differential line layout data.

[0007] Preferably, the information module includes: Obtain netlist information, ball grid array pins, design rules, and no-hook constraints to obtain the routing data for the printed circuit board; Physical layout information and wiring constraints of chip design are extracted from wiring data of printed circuit boards. Obtain information on process limitations and design requirements.

[0008] Preferably, the no-closing zone constraint includes: Based on the forbidden zone constraint, in the specific area where wiring needs to be avoided, the center pin and radius rk of each sub-region are defined, and the forbidden zone with a custom shape is drawn with the center pin as the reference point to obtain a set of forbidden zones. The sub-region is an independent forbidden zone geometric entity. Store the set of forbidden zones in a lookup table to obtain the forbidden zone index table.

[0009] Preferably, the graph model module includes: Set no-hide zone constraint rules. Based on the positions of adjacent pins and the no-hide zone index table, generate a point set for the wiring diagram according to the no-hide zone constraint rules. The no-hide zone constraint rules include setting the minimum distance between the path of the differential line corresponding to the center pin of the non-no-hide zone and the no-hide zone to be greater than or equal to 0 in order to prevent intrusion. At the same time, only differential lines originating from the center pin of the no-hide zone are allowed to overlap with the no-hide zone in the initial segment. The distance between the candidate path segment and the no-hide zone is checked in real time to eliminate illegal paths. Traverse the set of nodes. If two nodes share a common pin, add an undirected edge to connect the two nodes to obtain the edge set of the wiring graph. A graph model is constructed based on the set of points and edges in the wiring graph.

[0010] Preferably, the wiring path module includes: Based on the wiring data of the printed circuit board, each differential pair is regarded as a single differential line of equivalent width. The start node and the end node of the differential line are determined. The start node is set at the midpoint of two adjacent pins of the differential pair, and the end node is located on the escape boundary of the hexagonal diagram. Calculate the equivalent width of the difference line based on the difference pair parameters; Based on the equivalent width, start node, and end node of the differential line, the conversion from a differential pair to a single differential line is completed, resulting in the converted differential pair. Based on the wiring diagram model, forbidden zone constraint rules, and transformed differential pairs, a maze algorithm is used for path search. The optimization objective is to minimize the total wiring length, and the wiring path is obtained. The wiring path includes the polyline path of each differential line. By applying advanced conversion rules, an arc-shaped cabling scheme for a single wire network is obtained; Based on the arc-shaped cabling scheme of a single wire network, the single wire network is transformed into differential lines, resulting in an optimized cabling scheme that includes both straight lines and curves.

[0011] Preferably, the advanced conversion rules include: First, define the parameters, including the use of... d p The distance r represents the distance between two pins. k p represents the radius of the no-wiring zone. w This indicates the wire width when the difference pair is treated as a single wire; For scenarios where the restricted area is located at the center of the pin of the hexagonal subgraph to which the edge belongs, adjust the radius of the arc to r. k +p w / 2; For scenarios where the restricted area is located at a pin position corresponding to the edge, the edge is converted into a short straight line segment plus a 60-degree arc, and the radius of the arc is set to 3d. P / 2 - 2r k - p w ; For scenarios where the restricted area is located at the center of the two pins corresponding to the edge, adjust the radius of the arc to d. p -r k - p w / 2; For scenarios where the restricted area is located at the pin position corresponding to the edge, the edge is converted into a 60-degree curved trace with a short straight line, and the radius of the curved trace is set to 3d. P / 2 - 2r k - p w .

[0012] Preferably, the wiring scheme module includes: Determine the starting point of the differential line that can be directly connected to the target pin, calculate the straight path from the starting point to the first turning point, calculate and insert necessary transition arc segments to smooth the change in direction, and obtain the first part of the differential line path to prevent sudden impedance changes caused by abrupt turns. Identify the starting point of the differential line that is not directly connected to the target pin, add a wire at the starting point, and reliably connect it to the corresponding pin to obtain the second part of the differential line path; Merge the first part of the differential line path and the second part of the differential line path to obtain the entire differential line path; Based on the design rules, the entire differential line path was checked to confirm that there were no breaks or intersections between all straight line segments and transition arc segments; Based on the inspection results, repairs were carried out, the routing method at the starting position of the differential line was optimized, and the final differential line layout data was generated.

[0013] On the other hand, a high-density BGA arc automatic routing apparatus considering keep-out zone constraints is provided. This apparatus is applied to a high-density BGA arc automatic routing method considering keep-out zone constraints. The apparatus includes: Information module: used to acquire wiring data of printed circuit boards, including netlist information, ball grid array pin information, design rules and no-hook constraints; Graph model module: used to generate a set of points and edges of the wiring diagram based on the positions of adjacent pins and the positions of the forbidden areas in the wiring data, thus obtaining a graph model; The routing path module is used to treat each differential pair as a single differential line of equivalent width based on the routing data and the graph model, determine the start and end nodes of the single differential line, generate a preliminary routing path using a maze algorithm, and perform arc transformation processing to transform the polylines in the preliminary routing path into arc-shaped traces, thereby obtaining an optimized routing scheme. Cabling scheme module: Based on the optimized cabling scheme, execute the optimization scheme to obtain the final differential line layout data.

[0014] On the other hand, a high-density BGA arc-shaped automatic routing device considering no-cable zone constraints is provided. The high-density BGA arc-shaped automatic routing device considering no-cable zone constraints includes: a processor; a memory, the memory storing computer-readable instructions, which, when executed by the processor, implement the method described in any one of the above-described high-density BGA arc-shaped automatic routing methods considering no-cable zone constraints.

[0015] On the other hand, a computer-readable storage medium is provided, characterized in that the computer-readable storage medium stores program code, which can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

[0016] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: This system achieves automatic arc routing for high-speed differential pairs in no-route zones, completely replacing the traditional method that relies on manual segment-by-segment adjustments. It eliminates errors such as tangent discontinuities and uneven differential spacing that are easily caused by human operation, significantly improving the level of automation. Through dynamic parameter adjustment of advanced conversion rules from polygonal lines to arcs, it can adaptively avoid routing no-route zones around the pins of the ball grid array, achieving routing capability without any design rule violations. At the same time, the arc path effectively eliminates impedance abrupt changes caused by sharp corners, significantly reducing electromagnetic interference. The designed custom constraint graphical model can directly reuse existing escape routing algorithms without refactoring the core logic, demonstrating strong compatibility. It has excellent scalability, providing an efficient, reliable, and universally applicable technical solution for ultra-high-speed designs. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a high-density BGA arc-shaped automatic routing method considering no-catch zone constraints provided by an embodiment of the present invention; Figure 2 is a structural schematic diagram of an initial routing diagram model, preliminary polyline routing, advanced transformation rules, and routing results provided in an embodiment of the present invention. Figure 3 This is a block diagram of a high-density BGA arc-shaped automatic routing device considering no-cable zone constraints provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a high-density BGA arc-shaped automatic cabling device that takes into account the constraints of the no-cable zone, provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0020] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0021] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0022] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0023] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0024] This invention provides a high-density BGA arc-shaped automatic routing method that considers no-cable zone constraints. This method can be implemented using a high-density BGA arc-shaped automatic routing device that also considers no-cable zone constraints. This device can be a terminal or a server. Figure 1 The flowchart shown is for a high-density BGA arc-shaped automatic routing method that considers the constraints of the no-hook zone. The processing flow of this method may include the following steps:

[0025] Information module: used to acquire wiring data of printed circuit boards, including netlist information, ball grid array pin information, design rules and no-hook constraints; Preferably, the information module includes: Obtain netlist information, ball grid array pins, design rules, and no-hook constraints to obtain the routing data for the printed circuit board; Physical layout information and wiring constraints of chip design are extracted from wiring data of printed circuit boards. Obtain information on process limitations and design requirements.

[0026] Preferably, the no-closing zone constraint includes: Based on the forbidden zone constraint, in the specific area where wiring needs to be avoided, the center pin and radius rk of each sub-region are defined, and the forbidden zone with a custom shape is drawn with the center pin as the reference point to obtain a set of forbidden zones. The sub-region is an independent forbidden zone geometric entity. Store the set of forbidden zones in a lookup table to obtain the forbidden zone index table.

[0027] In some embodiments, acquiring detailed routing data can provide comprehensive and accurate basic information for subsequent routing processes. This comprehensive data collection can not only accurately reflect the physical layout of the chip design, but also provide the key constraints required during the routing process, ensuring that process limitations and design requirements are fully considered during routing, thereby optimizing the routing path and improving the success rate and design efficiency of routing.

[0028] It should be noted that the wire graph structure refers to abstracting the wiring problem into a graph. The nodes of the graph represent key locations in the circuit (such as the start point, end point, intermediate nodes, etc.), and read the forbidden area data (center pin, radius rk) to build a forbidden area index table.

[0029] Graph model module: used to generate a set of points and edges of the wiring diagram based on the positions of adjacent pins and the positions of the forbidden areas in the wiring data, thus obtaining a graph model; Preferably, the graph model module includes: Set no-hide zone constraint rules. Based on the positions of adjacent pins and the no-hide zone index table, generate a point set for the wiring diagram according to the no-hide zone constraint rules. The no-hide zone constraint rules include setting the minimum distance between the path of the differential line corresponding to the center pin of the non-no-hide zone and the no-hide zone to be greater than or equal to 0 in order to prevent intrusion. At the same time, only differential lines originating from the center pin of the no-hide zone are allowed to overlap with the no-hide zone in the initial segment. The distance between the candidate path segment and the no-hide zone is checked in real time to eliminate illegal paths. Traverse the set of nodes. If two nodes share a common pin, add an undirected edge to connect the two nodes to obtain the edge set of the wiring graph. A graph model is constructed based on the set of points and edges in the wiring graph.

[0030] In some embodiments, the node set is a set of locations of points that may be traversed during the wiring process, and it is obtained as follows: V ab = ( ( x a + x b ±(p s + 2 * w w )) / 2 , ( y a + y b ±(p s + 2 * w w )) / 2 ) Where V represents the set of nodes that the wiring path may pass through, a and b represent the ball grid array pins, and x a x b y a y b p represents the center coordinates of two adjacent ball grid array pins.s The difference between the two conductors is represented by w. w This is expressed as the width of a single wire.

[0031] It should be noted that for the pins of the ball grid array boundary, virtual pins are added (at positions equidistant from the boundary pins). The midpoint between the boundary pin and the virtual pin is calculated and added to the node set to ensure that each pin can form 6 nodes, satisfying the hexagonal subgraph structure. Due to the constraint of the forbidden zone in the routing, the line width is increased by half when obtaining the nodes of the forbidden zone pins for node setting.

[0032] It should be noted that generating the edge set requires traversing the node set. If two nodes correspond to a pin pair that shares a common pin, then an undirected edge is added to connect these two nodes. When adding undirected edges to boundary nodes and nodes corresponding to virtual pins, ensure that each edge belongs to only one hexagonal subgraph to avoid ambiguity in subsequent path transformations.

[0033] It should be further explained that, as shown in Figure 2, within the printed circuit board, wiring diagram nodes (dark gray prototype patterns) are added based on the given ball grid array pin information (black prototype pattern). These generated wiring diagram nodes are then connected together to create a hexagonal shape. Due to the presence of a keep-out area, the keep-out area is marked in light gray.

[0034] The routing path module is used to treat each differential pair as a single differential line of equivalent width based on the routing data and the graph model, determine the start and end nodes of the single differential line, generate a preliminary routing path using a maze algorithm, and perform arc transformation processing to transform the polylines in the preliminary routing path into arc-shaped traces, thereby obtaining an optimized routing scheme. Preferably, the wiring path module includes: Based on the wiring data of the printed circuit board, each differential pair is regarded as a single differential line of equivalent width. The start node and the end node of the differential line are determined. The start node is set at the midpoint of two adjacent pins of the differential pair, and the end node is located on the escape boundary of the hexagonal diagram. Calculate the equivalent width of the difference line based on the difference pair parameters; Based on the equivalent width, start node, and end node of the differential line, the conversion from a differential pair to a single differential line is completed, resulting in the converted differential pair. Based on the wiring diagram model, forbidden zone constraint rules, and transformed differential pairs, a maze algorithm is used for path search. The optimization objective is to minimize the total wiring length, and the wiring path is obtained. The wiring path includes the polyline path of each differential line. By applying advanced conversion rules, an arc-shaped cabling scheme for a single wire network is obtained; Based on the arc-shaped cabling scheme of a single wire network, the single wire network is transformed into differential lines, resulting in an optimized cabling scheme that includes both straight lines and curves.

[0035] In some embodiments, the differential pair parameters, including the single line width (w), must first be read. w ), difference interval (p s ), calculate the equivalent width of the difference line: p w = p s + 2 * w w Where, p w This represents the wire width when the differential pair is treated as a single wire.

[0036] It should be noted that transforming multiple constraints of difference pairs into single constraints simplifies path planning logic; and combining this with graphical modeling and reuse of traditional algorithms reduces technical difficulty; decreases path conflicts, and improves the routing feasibility of dense encapsulation; and provides a stable and efficient foundation for subsequent conversion from reflection to curves and avoidance of forbidden zones. Then, the start and end nodes of the difference line are determined. The start node is set at the intersection of the two adjacent pins of each difference pair. The end node is located on the escape boundary of the hexagonal graph.

[0037] As shown in Figure 2, a maze algorithm is used to generate wiring paths within the printed circuit board. The light gray area represents the no-wiring area, the black nodes are the intermediate nodes, which are the nodes that the path needs to pass through, the dark gray area represents the pin positions, and the black line segments represent the wiring paths generated by the maze algorithm.

[0038] Cabling scheme module: Based on the optimized cabling scheme, execute the optimization scheme to obtain the final differential line layout data.

[0039] Preferably, the advanced conversion rules include: First, define the parameters, including the use of... d p The distance r represents the distance between two pins. k p represents the radius of the no-wiring zone. w This indicates the wire width when the difference pair is treated as a single wire; For scenarios where the restricted area is located at the center of the pin of the hexagonal subgraph to which the edge belongs, adjust the radius of the arc to r. k +p w / 2; For scenarios where the restricted area is located at a pin position corresponding to the edge, the edge is converted into a short straight line segment plus a 60-degree arc, and the radius of the arc is set to 3d. P / 2 - 2r k - pw ; For scenarios where the restricted area is located at the center of the two pins corresponding to the edge, adjust the radius of the arc to d. p -r k - p w / 2; For scenarios where the restricted area is located at the pin position corresponding to the edge, the edge is converted into a 60-degree curved trace with a short straight line, and the radius of the curved trace is set to 3d. P / 2 - 2r k - p w .

[0040] Figure 2 shows the conversion rules from inverted lines to curves for three scenarios. The light gray area is the no-clip zone, the black nodes are the intermediate nodes that the path needs to pass through, the dark gray area represents the pin position, and the black arc-shaped trace represents the conversion result of a single line.

[0041] Figure 2 shows the differential line routing results after the line segment is converted into a curve or a curve plus a line segment after the advanced conversion rules are applied. The light gray area is the no-route area, the dark gray area represents the pin position, and the double arc represents the differential line routing result after conversion.

[0042] The above is an introduction to the method embodiments. The following describes the solution described in this application through device embodiments.

[0043] Figure 3 This is a block diagram illustrating an automatic routing apparatus for high-density BGA curved routing considering keep-out zone constraints, according to an exemplary embodiment. The apparatus is used in an automatic routing method for high-density BGA curved routing considering keep-out zone constraints. (Refer to...) Figure 3 The device includes an information module, a graphical model module, a cabling path module, and a cabling scheme module.

[0044] Information module: used to acquire wiring data of printed circuit boards, including netlist information, ball grid array pin information, design rules and no-hook constraints; Graph model module: used to generate a set of points and edges of the wiring diagram based on the positions of adjacent pins and the positions of the forbidden areas in the wiring data, thus obtaining a graph model; The routing path module is used to treat each differential pair as a single differential line of equivalent width based on the routing data and the graph model, determine the start and end nodes of the single differential line, generate a preliminary routing path using a maze algorithm, and perform arc transformation processing to transform the polylines in the preliminary routing path into arc-shaped traces, thereby obtaining an optimized routing scheme. Cabling scheme module: Based on the optimized cabling scheme, execute the optimization scheme to obtain the final differential line layout data.

[0045] A high-density BGA arc-shaped automatic routing device considering no-cable zone constraints, the high-density BGA arc-shaped automatic routing device considering no-cable zone constraints includes: a processor; a memory, the memory storing computer-readable instructions, when executed by the processor, implementing the method described in any one of the above-described high-density BGA arc-shaped automatic routing methods considering no-cable zone constraints.

[0046] A computer-readable storage medium, characterized in that the computer-readable storage medium stores program code, the program code being invoked by a processor to execute the method as described in any one of claims 1 to 7.

[0047] Figure 4 This is a schematic diagram of a high-density BGA arc-shaped automatic cabling device considering the constraints of the no-cable zone, as provided in an embodiment of the present invention. Figure 4 As shown, a high-density BGA curved automated routing device that considers no-cable zone constraints may include the above-mentioned Figure 3 The illustrated high-density BGA curved automatic routing apparatus takes into account keep-out zone constraints. Optionally, the high-density BGA curved automatic routing apparatus 410 taking into account keep-out zone constraints may include a first processor 2001.

[0048] Optionally, the high-density BGA arc automatic routing device 410, which takes into account no-wiring zone constraints, may also include a memory 2002 and a transceiver 2003.

[0049] The first processor 2001, memory 2002, and transceiver 2003 can be connected via a communication bus.

[0050] The following is combined with Figure 4 The components of the high-density BGA curved automatic cabling device 410, which takes into account no-cable zone constraints, are described in detail below: The first processor 2001 is the control center of the high-density BGA arc automatic routing device 410, which takes into account the constraints of the no-cable zone. It can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0051] Optionally, the first processor 2001 can perform various functions of the high-density BGA arc automatic routing device 410 that takes into account the constraints of the no-cable zone by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.

[0052] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, for example... Figure 4 CPU0 and CPU1 are shown in the diagram.

[0053] In a specific implementation, as one example, the high-density BGA arc-shaped automatic routing device 410, which considers the constraints of the no-cable zone, may also include multiple processors, for example... Figure 4 The first processor 2001 and the second processor 2004 are shown in the diagram. Each of these processors can be a single-core processor or a multi-core processor. Here, a processor can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0054] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0055] Optionally, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or may exist independently, and may be connected via the interface circuit of the high-density BGA arc automatic routing device 410 considering keep-out area constraints. Figure 4 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0056] The transceiver 2003 is used to communicate with network devices or with terminal devices.

[0057] Alternatively, transceiver 2003 may include a receiver and a transmitter. Figure 4 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0058] Alternatively, the transceiver 2003 can be integrated with the first processor 2001 or exist independently, and can be connected via the interface circuit of the high-density BGA arc-shaped automatic routing device 410, which takes into account the constraints of the no-wiring zone. Figure 4 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0059] It should be noted that, Figure 4 The structure of the high-density BGA arc-shaped automatic cabling device 410 shown in the figure, which takes into account the no-cable zone constraint, does not constitute a limitation on the router. Actual knowledge structure identification devices may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0060] Furthermore, the technical effects of the high-density BGA arc-shaped automatic routing device 410 considering the constraints of the no-hitch area can be referred to the technical effects of the high-density BGA arc-shaped automatic routing method considering the constraints of the no-hitch area described in the above method embodiments, and will not be repeated here.

[0061] It should be understood that the first processor 2001 in the embodiments of the present invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0062] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0063] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0064] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0065] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0066] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0067] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0068] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0069] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0070] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0072] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for automatic routing of high-density BGA arcs considering no-catch zones, characterized in that, A system for automatic routing of high-density BGA curved sections considering no-cable zone constraints, comprising: a graph model unit and a routing unit, wherein the graph model unit includes an information module and a graph model module, and the routing unit includes a routing path module and a routing scheme module, characterized in that it includes: Information module: used to acquire wiring data of printed circuit boards, including netlist information, ball grid array pin information, design rules and a no-hatch index table; Graph model module: used to generate a set of points and edges of the wiring diagram based on the positions of adjacent pins in the wiring data and the forbidden zone index table, thus obtaining a graph model; The routing path module is used to treat each differential pair as a single differential line of equivalent width based on the routing data and the graph model, determine the start and end nodes of the single differential line, generate a preliminary routing path using a maze algorithm, and perform arc transformation processing to transform the polylines in the preliminary routing path into arc-shaped traces, thereby obtaining an optimized routing scheme. Cabling scheme module: Based on the optimized cabling scheme, execute the optimization scheme to obtain the final differential line layout data.

2. The high-density BGA arc-shaped automatic routing method considering the no-hook zone constraint according to claim 1, characterized in that, The information module includes: Obtain netlist information, ball grid array pins, design rules, and no-hook constraints to obtain the routing data for the printed circuit board; Physical layout information and wiring constraints of chip design are extracted from wiring data of printed circuit boards. Obtain information on process limitations and design requirements.

3. The high-density BGA arc-shaped automatic routing method considering the no-hook zone constraint according to claim 2, characterized in that, The no-closing zone constraint includes: Based on the forbidden zone constraint, in the specific area where wiring needs to be avoided, the center pin and radius rk of each sub-region are defined, and the forbidden zone with a custom shape is drawn with the center pin as the reference point to obtain a set of forbidden zones. The sub-region is an independent forbidden zone geometric entity. Store the set of forbidden zones in a lookup table to obtain the forbidden zone index table.

4. The high-density BGA arc-shaped automatic routing method considering the no-hook zone constraint according to claim 1, characterized in that, The graph model module includes: Set no-hide zone constraint rules. Based on the positions of adjacent pins and the no-hide zone index table, generate a point set for the wiring diagram according to the no-hide zone constraint rules. The no-hide zone constraint rules include setting the minimum distance between the path of the differential line corresponding to the center pin of the non-no-hide zone and the no-hide zone to be greater than or equal to 0 in order to prevent intrusion. At the same time, only differential lines originating from the center pin of the no-hide zone are allowed to overlap with the no-hide zone in the initial segment. The distance between the candidate path segment and the no-hide zone is checked in real time to eliminate illegal paths. Traverse the set of nodes. If two nodes share a common pin, add an undirected edge to connect the two nodes to obtain the edge set of the wiring graph. A graph model is constructed based on the set of points and edges in the wiring graph.

5. The high-density BGA arc-shaped automatic routing method considering the no-hook zone constraint according to claim 1, characterized in that, The wiring path module includes: Based on the wiring data of the printed circuit board, each differential pair is regarded as a single differential line of equivalent width. The start node and the end node of the differential line are determined. The start node is set at the midpoint of two adjacent pins of the differential pair, and the end node is located on the escape boundary of the hexagonal diagram. Calculate the equivalent width of the difference line based on the difference pair parameters; Based on the equivalent width, start node, and end node of the differential line, the conversion from a differential pair to a single differential line is completed, resulting in the converted differential pair. Based on the wiring diagram model, forbidden zone constraint rules, and transformed differential pairs, a maze algorithm is used for path search. The optimization objective is to minimize the total wiring length, and the wiring path is obtained. The wiring path includes the polyline path of each differential line. By applying advanced conversion rules, an arc-shaped cabling scheme for a single wire network is obtained; Based on the arc-shaped cabling scheme of a single wire network, the single wire network is transformed into differential lines, resulting in an optimized cabling scheme that includes both straight lines and curves.

6. The high-density BGA arc-shaped automatic routing method considering the no-hook zone constraint according to claim 5, characterized in that, The advanced conversion rules include: First, define the parameters, including the use of... d p The distance r represents the distance between two pins. k p represents the radius of the no-wiring zone. w This indicates the wire width when the difference pair is treated as a single wire; For the scene that the forbidden zone is located at the pin center position of the edge belonging hexagon subgraph, adjust the radius of the circular arc to r k + p w / 2; For the scene that the forbidden zone is located at a pin position corresponding to an edge, the edge is converted into a short straight line segment plus a 60-degree arc line form, and the radius of the arc-shaped trace is set to 3d P / 2 - 2r k - p w ; For scenarios where the restricted area is located at the center of the two pins corresponding to the edge, adjust the radius of the arc to d. p -r k - p w / 2; For scenarios where the restricted area is located at the pin position corresponding to the edge, the edge is converted into a 60-degree curved trace with a short straight line, and the radius of the curved trace is set to 3d. P / 2 - 2r k - p w .

7. The high-density BGA arc-shaped automatic routing method considering the no-hook zone constraint according to claim 1, characterized in that, The cabling scheme module includes: Determine the starting point of the differential line that can be directly connected to the target pin, calculate the straight path from the starting point to the first turning point, calculate and insert necessary transition arc segments to smooth the direction change, and obtain the first part of the differential line path to prevent sudden impedance changes caused by abrupt turns; Identify the starting point of the differential line that is not directly connected to the target pin, add a wire at the starting point, and reliably connect it to the corresponding pin to obtain the second part of the differential line path; Merge the first part of the differential line path and the second part of the differential line path to obtain the entire differential line path; Based on the design rules, the entire differential line path was checked to confirm that there were no breaks or intersections between all straight line segments and transition arc segments; Based on the inspection results, repairs were carried out, the routing method at the starting position of the differential line was optimized, and the final differential line layout data was generated.

8. A high-density BGA arc-shaped automatic routing device considering keep-out zone constraints, wherein the high-density BGA arc-shaped automatic routing device considering keep-out zone constraints is used to implement the high-density BGA arc-shaped automatic routing method considering keep-out zone constraints as described in any one of claims 1-7, characterized in that, The device includes: Information module: used to acquire wiring data of printed circuit boards, including netlist information, ball grid array pin information, design rules and a no-hatch index table; Graph model module: used to generate a set of points and edges of the wiring diagram based on the positions of adjacent pins in the wiring data and the forbidden zone index table, thus obtaining a graph model; The routing path module is used to treat each differential pair as a single differential line of equivalent width based on the routing data and the graph model, determine the start and end nodes of the single differential line, generate a preliminary routing path using a maze algorithm, and perform arc transformation processing to transform the polylines in the preliminary routing path into arc-shaped traces, thereby obtaining an optimized routing scheme. Cabling scheme module: Based on the optimized cabling scheme, execute the optimization scheme to obtain the final differential line layout data.

9. A high-density BGA arc-shaped automatic cabling device considering no-cable zone constraints, characterized in that, The high-density BGA arc autorouting processor considering no-cable zone constraints; a memory storing computer-readable instructions, which, when executed by the processor, implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

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