A differential line arc automatic wiring method and device for high-density BGA

Abstract

The application discloses a differential line arc automatic wiring method and device for high-density BGA, and relates to the technical field of printed circuit board design. The method comprises the following steps: firstly, obtaining netlist, BGA pins and design rules and other wiring information, and constructing a graph model containing virtual pins based on the wiring information. Then, constraint-driven path search is performed based on the model to generate an initial polyline path, and the initial polyline path is optimized into a smooth circular arc path by using geometric rules. Subsequently, post-processing such as differential pair generation and tangent continuity check is performed to ensure signal integrity. Finally, through comprehensive wiring optimization and verification, the final wiring file is output. The application can complete the wiring task in a very short time when processing industrial high-density BGA layout, realizes thousands of times acceleration compared with manual wiring, and maintains a very high wiring rate and standard geometric shape.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board design technology, and in particular to a method and apparatus for automatic arc routing of differential lines for high-density BGA. Background Technology

[0002] With the rapid development of 5G communication, AI accelerators, and high-performance computing systems, the data transmission rate of BGA differential signals has exceeded 56Gb. Traditional 45-degree zigzag escape routing methods cause impedance discontinuities and electromagnetic interference in high-frequency scenarios, severely limiting system performance. In contrast, curved routing eliminates sharp corners, ensuring tangent continuity and providing smoother impedance transitions, lower electromagnetic radiation, and superior high-frequency performance, making it an ideal choice for high-speed differential pair routing. However, existing electronic design automation tools and academic research methods primarily focus on 90-degree / 45-degree zigzag routing, lacking support for automatic curved routing of differential pairs. Currently, engineers must rely on time-consuming and error-prone manual methods to adjust curved routing, which cannot meet the urgent needs of modern high-speed PCB design for efficiency and reliability. Summary of the Invention

[0003] To address the technical problem of the lack of an automatic, efficient, and smooth high-speed differential pair arc escape routing method in existing technologies, this invention provides a method and apparatus for automatic differential line arc escape routing for high-density BGAs. The technical solution is as follows:

[0004] On the one hand, a method for automatic differential line arc routing for high-density BGA is provided. This method is implemented by an automatic differential line arc routing device for high-density BGA, and includes: S1: Obtain the routing information of the chip, which includes processing netlist information, BGA pin information and design rule information; S2: Based on the routing information, a graph model is constructed, which includes generating virtual pins, a set of nodes, and a set of edges; S3: Based on the graph model, perform constraint-driven path search and routing to obtain the initial polyline path; S4: Optimize the initial polyline path to obtain a smooth circular arc path. The optimization includes converting the polyline path into a smooth circular arc path using basic geometric rules. S5: The post-processed path is obtained by performing routing post-processing based on a smooth arc path. The routing post-processing includes generating differential pairs and checking tangent continuity to ensure signal integrity. S6: Perform routing optimization and verification steps based on the post-processing path to obtain the final routing file.

[0005] Preferably, the step S1 involves acquiring the routing information of the chip, which includes processing netlist information, BGA pin information, and design rule information, including: S11: Process netlist information, the processing of netlist information includes obtaining a net set and a differential signal set, the net set containing several nets, the nets being pin-based. P i As the source point, the differential signal set consists of two adjacent pins connected. P a , P b Composed of wire mesh; S12: Process the BGA pin information to obtain the pin spacing. d p Pin radius r p The set of center coordinates of the pins, and the distribution pattern of the pins on the two-dimensional plane, wherein the distribution pattern of the pins on the two-dimensional plane is a hexagonal array; S13: Calculate the line width, minimum line spacing, differential pair internal spacing, and equivalent differential line width to obtain design rule information. The design rule information includes routing geometry parameters, high-speed signal electrical constraints, and network output order constraints. The high-speed signal electrical constraints include that the differential pair is completed from the pin to the escape boundary on a single layer and that intermediate vias are prohibited. The network output order constraints are the specified output order that each network follows on the escape boundary.

[0006] Preferably, step S2 involves constructing a graph model based on the routing information. The graph model construction includes generating virtual pins, a set of nodes, and a set of edges, including: S21: Based on netlist, BGA pin and design rule information, for any two BGA pins Pa and Pb that are physically adjacent, create a node at the midpoint of the line connecting their centers. The node coordinates are precisely calculated using the midpoint formula to obtain the node set. S22: Based on the spacing and layout pattern of BGA pins, calculate and create virtual pins outside the boundary pins. These virtual pins are located at the edge of the BGA array and are used to maintain the regularity and integrity of the graph model at the boundary. S23: Based on the node set, BGA pins and virtual pins, if the pin pairs corresponding to two nodes share a common BGA pin, then an undirected edge is established between the two nodes to ensure that each actual pin is surrounded by a regular hexagonal subgraph consisting of six nodes and six edges, thus obtaining the edge set; S24: Based on the node set and edge set, construct a hexagonal mesh graph model covering the entire BGA routing area. The hexagonal mesh graph model is used to ensure that each actual BGA pin is surrounded by a regular hexagonal subgraph consisting of six nodes and six edges, and each edge in the graph uniquely belongs to the hexagonal subgraph.

[0007] Preferably, step S3, based on the graph model, performs constraint-driven path search and routing to obtain an initial polyline path, including: S31: Based on the differential signal set and design rules, each differential pair is regarded as a single virtual wire with an equivalent width, and a virtual differential line model is constructed. The equivalent width is determined by the sum of the line width of the two signal lines and the differential spacing. S32: Determine the start node and the end node. The start node includes the graph node corresponding to the midpoint of the line connecting the centers of the two source pins of the differential pair. The end node includes the node on the boundary of the wiring area. S33: Set fan-out order constraints. Based on the preset relative position relationship between the two signal lines of the differential pair, restrict the selection direction of the first wiring edge of the starting node. The preset relative position relationship includes clockwise or counterclockwise arrangement to prevent crossover within the differential pair. S34: Based on the virtual difference line model and fan-out order constraints, search for the shortest polyline path from the starting node to the ending node on the hexagonal mesh graph model to obtain the initial polyline path. The shortest polyline path is generated based on a network flow or A* search algorithm. The initial polyline path is physically represented as a polyline segment connecting the center points of each mesh and having a preset topology. The preset topology avoids obstacles and satisfies the overall routing trend of the difference pair.

[0008] Preferably, step S4 optimizes the initial polyline path to obtain a smooth circular arc path. The optimization includes converting the polyline path into a smooth circular arc path using basic geometric rules, including: S41: Starting from the starting node, the angle formed by every three adjacent nodes is used to generate an arc with a central angle of 60 degrees, centered on the center pin of the hexagonal grid to which the middle node belongs, and with a radius of half the side length of the grid. S42: Based on the geometric symmetry of the hexagonal grid, the tangent directions of the first and second arc segments at the connection point are both perpendicular to the pin connection line, thus achieving tangent continuity between the two arc segments at the connection point. A smooth curve composed of multiple tangent arc segments and tangent segments replaces the initial polyline path, resulting in a smooth arc path.

[0009] Preferably, the post-processing path obtained by S5 based on the smooth arc path routing post-processing includes generating differential pairs and checking tangent continuity to ensure signal integrity, including: S51: Using the smooth circular arc path as the central axis, offset it equally to both sides of its normal direction to obtain differential pair traces. The offset distance is set based on the differential spacing in the design rules. S52: Based on differential pair routing, the transition correction at the pin connection is achieved by inserting a transition arc between the end of the signal line and the BGA pin to obtain a complete differential pair routing. The transition arc is tangent to the main path and extends smoothly to the center of the pin pad. S53: Perform integrity verification on the complete differential pair trace to obtain the post-processing path. The integrity verification includes tangent continuity check and design rule check. The tangent continuity check is used to ensure that the derivatives of all connection points are continuous. The design rule check is used to confirm that the line width, spacing and clearance distance meet the preset chip manufacturing process requirements.

[0010] Preferably, the routing optimization and verification step based on post-processing in S6, to obtain the final routing file, includes: S61: Integrate the post-processing path to generate a complete single-layer cabling topology; S62: Based on the complete single-layer routing topology, generate a complete pin connection sequence for each differential pair, which records the positions of all critical nodes from the BGA pin to the escape boundary; S63: Based on the complete single-layer wiring topology and complete pin connection sequence, perform geometric layout data mapping to obtain geometric layout data containing arc segments and straight line segments, wherein the geometric layout data meets the requirement of full tangent continuity; S64: Convert the geometric layout data into a standard layout data format to obtain the final routing file, which includes the geometric features of arc segments and straight line segments, their layer information, and topological connection relationships.

[0011] On the other hand, an automatic differential line arc routing apparatus for high-density BGA is provided. This apparatus is applied to the automatic differential line arc routing method for high-density BGA, and the apparatus includes: Information module: used to acquire the routing information of the chip, which includes processing netlist information, BGA pin information and design rule information; Graph model module: used to construct a graph model based on the routing information, wherein the graph model construction includes generating virtual pins, node sets, and edge sets; Initial polyline module: used to perform constraint-driven path search and routing based on the graph model to obtain the initial polyline path; Arc Path Module: Used to optimize the initial polyline path to obtain a smooth arc path. The optimization includes converting the polyline path into a smooth arc path using basic geometric rules. Post-processing module: used to perform routing post-processing based on a smooth arc path to obtain the post-processed path, the routing post-processing including generating differential pairs and checking tangent continuity to ensure signal integrity; Optimization module: Used to perform routing optimization and verification steps based on the post-processing path to obtain the final routing file.

[0012] On the other hand, a differential line arc automatic routing device for high-density BGA is provided, the differential line arc automatic routing device for high-density BGA includes: a processor; a memory, the memory storing computer-readable instructions, which, when executed by the processor, implement the method described in any one of the above-described differential line arc automatic routing methods for high-density BGA.

[0013] On the other hand, a computer-readable storage medium is provided, characterized in that the computer-readable storage medium stores program code, which can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

[0014] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: This invention, through an innovative hexagonal graph model and polygonal-circular arc conversion rule, achieves for the first time automatic, smooth arc escape routing for high-speed differential pairs, replacing the inefficient and error-prone manual design process and reducing routing time from weeks to seconds. Simultaneously, by ensuring the tangential continuity of the routing path, it significantly improves the integrity of high-speed signals, providing a reliable physical foundation for data transmission of 56Gb and above. The proposed method maintains 100% routing success while possessing linear time complexity (O(n)), ensuring excellent scalability when handling large-scale, high-density BGA packages. Ultimately, this invention provides a practical, production-ready solution, effectively bridging the gap between academic research and industrial practice in the field of high-speed PCB design. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1This is a flowchart of an automatic differential line arc routing method for high-density BGA provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a fan-out order constraint, polyline path, difference pair centerline and regular hexagonal array diagram model provided by an embodiment of the present invention; Figure 3 This is a block diagram of a differential line arc-shaped automatic routing device for high-density BGA provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a differential line arc-shaped automatic routing device for high-density BGA provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0018] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0019] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0020] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0021] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0022] This invention provides a method for automatic differential line arc routing for high-density BGAs. This method can be implemented using an automatic differential line arc routing device for high-density BGAs, which can be a terminal or a server. Figure 1 The flowchart shown is for an auto-routing method for differential lines in high-density BGAs. The processing flow of this method may include the following steps:

[0023] Obtain the routing information of the chip, which includes processing netlist information, BGA pin information and design rule information; Preferably, the routing information of the chip is obtained, the routing information including processing netlist information, BGA pin information and design rule information, including: Processing netlist information, the process including obtaining a net set and a differential signal set, wherein the net set contains several nets, and the nets are pin-based. P i As the source point, the differential signal set consists of two adjacent pins connected. P a , P b Composed of wire mesh; Process the BGA pin information to obtain the pin spacing. d p Pin radius r p The set of center coordinates of the pins, and the distribution pattern of the pins on the two-dimensional plane, wherein the distribution pattern of the pins on the two-dimensional plane is a hexagonal array; The design rule information is obtained by calculating the line width, minimum line spacing, differential pair internal spacing, and equivalent differential line width. The design rule information includes routing geometry parameters, high-speed signal electrical constraints, and network output order constraints. The high-speed signal electrical constraints include that the differential pair is completed from the pin to the escape boundary on a single layer and that intermediate vias are prohibited. The network output order constraints are the specified output order that each network follows on the escape boundary.

[0024] In some embodiments, the netlist information encompasses the basic structural features of the chip, including its physical dimensions, the total number of metal layers, and the component distribution on each layer. It also includes the dimensions of all components, their precise location coordinates on the PCB, and the specific metal layers they are connected to. Particularly important is the need to clearly define the connectivity relationships of all networks to be routed, including the pairing information of high-speed differential pairs (represented as sets). S={S i =(n a ,n b )} This is crucial. BGA pin information details the physical characteristics of the package, including the set of center coordinates for all pins. P={p i (x i ,y i )} Center-to-center spacing between adjacent pins d p The radius of the pin itselfr p The diagram also includes the specific pin distribution pattern on the two-dimensional plane (typically a hexagonal array), as well as virtual pin information introduced to handle boundary pins to ensure the integrity of the wiring diagram model.

[0025] It should be noted that the design rule information includes: line width. W W Minimum line spacing W S ; Differential pair internal spacing P S Equivalent difference linewidth P W =P S +2×W W .

[0026] It is important to note that comprehensively and accurately acquiring all the aforementioned routing information is the cornerstone of the successful implementation of the entire automated arc escape routing process. This information collectively forms the fundamental basis for subsequent graph model construction, path search algorithm selection, arc transformation rule application, and final design rule verification. Through the systematic integration and verification of this basic data, design errors caused by inconsistencies in information or missing key parameters can be avoided from the source, providing a reliable guarantee for generating a smooth arc routing scheme that meets all high-speed design constraints and possesses excellent signal integrity performance.

[0027] Based on the routing information, a graph model is constructed, which includes generating virtual pins, a set of nodes, and a set of edges, as shown in Figure 2. Preferably, based on the routing information, a graph model is constructed, wherein the graph model construction includes generating virtual pins, a set of nodes, and a set of edges, including: Based on netlist, BGA pin and design rule information, for any two BGA pins Pa and Pb that are physically adjacent, a node is created at the midpoint of the line connecting their centers. The node coordinates are precisely calculated using the midpoint formula to obtain the node set. Based on the spacing and layout pattern of BGA pins, virtual pins are calculated and created outside the boundary pins. These virtual pins are located at the edge of the BGA array and are used to maintain the regularity and integrity of the graph model at the boundary. Based on the node set, BGA pins, and virtual pins, if the pin pairs corresponding to two nodes share a common BGA pin, then an undirected edge is established between the two nodes to ensure that each actual pin is surrounded by a regular hexagonal subgraph consisting of six nodes and six edges, as shown in Figure 2, thus obtaining the edge set; Based on the node set and edge set, a hexagonal mesh graph model covering the entire BGA routing area is constructed. The hexagonal mesh graph model is used to ensure that each actual BGA pin is surrounded by a regular hexagonal subgraph consisting of six nodes and six edges, and each edge in the graph uniquely belongs to the hexagonal subgraph.

[0028] In some embodiments, an undirected graph G = (V, E) is constructed, where V is the set of all nodes and E is the set of all edges. This graph model provides the basic topology for subsequent path search and arc transformation, clarifies the rules for generating nodes and edges, and introduces the concept of virtual pins to handle boundary cases.

[0029] It should be noted that setting the node at the midpoint of an adjacent pin makes the node naturally located on the central axis of the differential pair wiring. This provides an ideal geometric start and end point for directly generating a smooth arc path that is symmetrical about the pin center, which is the basis for achieving tangent continuity.

[0030] It should be further explained that, for pins located at the edge of the BGA array, the concept of virtual pins is introduced to maintain the regularity and integrity of the graph model at the boundary. As shown in Figure 2, based on these virtual pins, corresponding nodes and edges are generated according to the corresponding rules.

[0031] It should be further clarified that this hexagonal graph model is not a general mesh, but a topology specifically designed for high-density BGA arc escape routing. Its regularity ensures the determinism and geometric consistency of the transformation from polyline paths to arc paths, allowing traditional and mature polyline escape routing algorithms to be directly reused. This efficiently transforms the complex arc routing problem into a classic graph search problem, greatly improving the practicality and computational efficiency of the method.

[0032] Based on the graph model, a constraint-driven path search and routing is performed to obtain an initial polyline path; Preferably, based on the graph model, constraint-driven path search and routing are performed to obtain an initial polyline path, including: Based on the differential signal set and design rules, each differential pair is regarded as a single virtual wire with an equivalent width, and a virtual differential line model is constructed. The equivalent width is determined by the sum of the line width of the two signal lines and the differential spacing. Determine the start node and the end node. The start node includes the graph node corresponding to the midpoint of the line connecting the centers of the two source pins of the differential pair. The end node includes the node on the boundary of the wiring area. Set fan-out order constraints and restrict the selection direction of the first wiring edge of the starting node according to the preset relative position relationship of the two signal lines of the differential pair. The preset relative position relationship includes clockwise arrangement or counterclockwise arrangement to prevent crossover inside the differential pair. Based on the virtual difference line model and fan-out order constraints, the shortest polyline path from the starting node to the ending node is searched on the hexagonal mesh graph model to obtain the initial polyline path. The shortest polyline path is generated based on a network flow or A* search algorithm. The initial polyline path is physically represented as a polyline segment connecting the center points of each mesh and having a preset topology. The preset topology avoids obstacles and satisfies the overall routing trend of the difference pair.

[0033] In some embodiments, because differential signals have strict requirements on parallel routing and spacing, the path search routing does not directly search the two independent signal lines, but instead uses a "virtual single-line model" for dimensionality reduction. Specifically, each pair of differential signals is regarded as a single virtual conductor with an equivalent width, which is equal to the line width of the two signal lines plus the differential spacing between them.

[0034] It should be noted that the generated path is represented in physical space as a broken line segment connecting the center points of each grid. Although a smooth curve has not yet been formed, its topology has avoided obstacles and satisfied the overall routing trend of the differential pair.

[0035] The initial polyline path is optimized to obtain a smooth circular arc path. The optimization includes converting the polyline path into a smooth circular arc path using basic geometric rules. Preferably, the initial polyline path is optimized to obtain a smooth circular arc path. The optimization includes converting the polyline path into a smooth circular arc path using basic geometric rules, including: As shown in Figure 2, starting from the starting node, the included angle formed by every three adjacent nodes is used to generate an arc with a central angle of 60 degrees, centered on the center pin of the hexagonal grid to which the middle node belongs, and with half the side length of the grid as the radius. Based on the geometric symmetry of the hexagonal grid, the tangent directions of the first and second arc segments at the connection point are both perpendicular to the pin connection line, thus achieving tangent continuity between the two arc segments at the connection point. A smooth curve composed of multiple tangent arc segments and tangent segments replaces the initial polyline path, resulting in a smooth arc path.

[0036] In some embodiments, since the starting point of the offset signal line may no longer be directly aligned with the pin center, a direct connection would result in a non-tangential bend at the pin. To address this, the system automatically inserts a tiny "transition arc" between the end of the signal line and the BGA pin. This transition arc is tangent to the main path and extends smoothly to the center of the pin pad, ensuring tangential continuity from the moment the signal is emitted from the pin and avoiding reflection noise at the starting point.

[0037] The post-processing path is obtained by performing routing post-processing based on a smooth circular arc path. The routing post-processing includes generating differential pairs and checking tangent continuity to ensure signal integrity. Preferably, the post-processed path is obtained by performing routing post-processing based on a smooth circular arc path. The routing post-processing includes generating differential pairs and checking tangent continuity to ensure signal integrity, including: Using a smooth circular arc path as the central axis, offset equally to both sides of its normal direction to obtain differential pair traces. The offset distance is set based on the differential spacing in the design rules. Based on differential pair routing, the transition correction at the pin connection is achieved by inserting a transition arc between the end of the signal line and the BGA pin to obtain a complete differential pair routing. The transition arc is tangent to the main path and extends smoothly to the center of the pin pad. The integrity of the complete differential pair trace is verified to obtain the post-processing path. The integrity verification includes tangent continuity check and design rule check. The tangent continuity check is used to ensure that the derivatives of all connection points are continuous. The design rule check is used to confirm that the line width, spacing and clearance distance meet the preset chip manufacturing process requirements.

[0038] The final routing file is obtained by performing routing optimization and verification steps based on the post-processing path.

[0039] Preferably, the routing optimization and verification steps are performed based on the post-processing path to obtain the final routing file, including: The integrated post-processing paths generate a complete single-layer cabling topology; Based on the complete single-layer routing topology, a complete pin connection sequence for each differential pair is generated, which records the locations of all critical nodes from the BGA pin to the escape boundary. Based on the complete single-layer wiring topology and complete pin connection sequence, geometric layout data mapping is performed to obtain geometric layout data containing arc segments and straight line segments. The geometric layout data meets the requirement of full tangent continuity. The geometric layout data is converted into a standard layout data format to obtain the final routing file, which includes the geometric features of arc segments and straight line segments, their layer information, and topological connections.

[0040] In some embodiments, through transformation, the originally rigid polygonal path is reconstructed into a smooth curve composed of multiple tangent arcs and tangent segments. This not only eliminates the impedance discontinuity problem caused by sharp corners, but also effectively solves the DRV problem commonly found in high-density BGA packages.

[0041] Optionally, the individual wire paths generated after post-processing of all differential pairs can be integrated to form a complete single-layer routing scheme. Based on the integrated routing result, a complete pin connection sequence from the BGA pin to the escape boundary for each differential pair is generated, which accurately records the locations of all critical nodes traversed by the routing path.

[0042] Preferably, the generated pin connection sequence is converted into an industry-standard layout data format (such as GDSII, OASIS, or a PCB design software compatible format). This output data fully preserves the mapping relationship from the pin sequence to the actual geometry, accurately describes the geometric features, layer information, and topological connections of all arc segments and straight lines, and can be directly delivered to PCB manufacturers or used for subsequent simulation verification and analysis.

[0043] The above is an introduction to the method embodiments. The following describes the solution described in this application through device embodiments.

[0044] Figure 3 This is a block diagram illustrating an automatic differential line arc routing apparatus for high-density BGAs, according to an exemplary embodiment. The apparatus is used in an automatic differential line arc routing method for high-density BGAs. (Refer to...) Figure 3 The device includes an information module, a graphical model module, an initial polyline module, an arc path module, a post-processing module, and an optimization module.

[0045] Information module: used to acquire the routing information of the chip, which includes processing netlist information, BGA pin information and design rule information; Graph model module: used to construct a graph model based on the routing information, wherein the graph model construction includes generating virtual pins, node sets, and edge sets; Initial polyline module: used to perform constraint-driven path search and routing based on the graph model to obtain the initial polyline path; Arc Path Module: Used to optimize the initial polyline path to obtain a smooth arc path. The optimization includes converting the polyline path into a smooth arc path using basic geometric rules. Post-processing module: used to perform routing post-processing based on a smooth arc path to obtain the post-processed path, the routing post-processing including generating differential pairs and checking tangent continuity to ensure signal integrity; Optimization module: Used to perform routing optimization and verification steps based on the post-processing path to obtain the final routing file.

[0046] An automated differential line routing device for high-density BGAs includes: a processor; and a memory storing computer-readable instructions. When executed by the processor, the computer-readable instructions implement any of the methods described above for automated differential line routing for high-density BGAs.

[0047] A computer-readable storage medium, characterized in that the computer-readable storage medium stores program code, the program code being invoked by a processor to execute the method as described in any one of claims 1 to 7.

[0048] Figure 4 This is a schematic diagram of a differential line arc-shaped automatic routing device for high-density BGA provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the differential line arc automatic routing equipment for high-density BGAs may include the above-mentioned Figure 3 The illustrated differential line arcing automatic routing apparatus for high-density BGA is shown. Optionally, the differential line arcing automatic routing apparatus 410 for high-density BGA may include a first processor 2001.

[0049] Optionally, the differential line arc automatic routing device 410 for high-density BGA may also include a memory 2002 and a transceiver 2003.

[0050] The first processor 2001, memory 2002, and transceiver 2003 can be connected via a communication bus.

[0051] The following is combined with Figure 4 The following is a detailed description of each component of the differential line arc automatic routing device 410 for high-density BGA: The first processor 2001 is the control center of the differential line arc automatic routing device 410 for high-density BGAs. It can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0052] Optionally, the first processor 2001 can perform various functions of the differential line arc automatic routing device 410 for high-density BGA by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.

[0053] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, for example... Figure 4 CPU0 and CPU1 are shown in the diagram.

[0054] In a specific implementation, as one example, the differential line arc automatic routing device 410 for high-density BGAs may also include multiple processors, for example... Figure 4 The first processor 2001 and the second processor 2004 are shown in the diagram. Each of these processors can be a single-core processor or a multi-core processor. Here, a processor can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0055] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0056] Optionally, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or may exist independently, and may be accessed via the interface circuit of the differential line arc automatic routing device 410 for high-density BGAs. Figure 4 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0057] The transceiver 2003 is used to communicate with network devices or with terminal devices.

[0058] Alternatively, transceiver 2003 may include a receiver and a transmitter. Figure 4 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0059] Alternatively, the transceiver 2003 can be integrated with the first processor 2001 or exist independently, and can be interfaced through the interface circuit of the differential line arc automatic routing device 410 for high-density BGA. Figure 4 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0060] It should be noted that, Figure 4 The structure of the differential line arc automatic routing device 410 for high-density BGA shown in the figure does not constitute a limitation on the router. Actual knowledge structure identification devices may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0061] Furthermore, the technical effects of the differential line arc automatic routing device 410 for high-density BGA can be referred to the technical effects of the differential line arc automatic routing method for high-density BGA described in the above method embodiments, and will not be repeated here.

[0062] It should be understood that the first processor 2001 in the embodiments of the present invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0063] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0064] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0065] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0066] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0067] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0068] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0069] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0070] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0071] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0072] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0073] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for automatic differential line arc routing for high-density BGA, characterized in that, The method includes: S1: Obtain the routing information of the chip, which includes processing netlist information, BGA pin information and design rule information; S2: Based on the routing information, a graph model is constructed, which includes generating virtual pins, a set of nodes, and a set of edges; S3: Based on the graph model, perform constraint-driven path search and routing to obtain the initial polyline path; S4: Optimize the initial polyline path to obtain a smooth circular arc path. The optimization includes converting the polyline path into a smooth circular arc path using basic geometric rules. S5: The post-processed path is obtained by performing routing post-processing based on a smooth arc path. The routing post-processing includes generating differential pairs and checking tangent continuity to ensure signal integrity. S6: Perform routing optimization and verification steps based on the post-processing path to obtain the final routing file.

2. The method for automatic differential line arc routing for high-density BGA according to claim 1, characterized in that, The step S1 acquires the routing information of the chip, which includes processing netlist information, BGA pin information, and design rule information, including: S11: Process netlist information, the processing of netlist information includes obtaining a net set and a differential signal set, the net set containing several nets, the nets being pin-based. P i As the source point, the differential signal set consists of two adjacent pins connected. P a , P b Composed of wire mesh; S12: Process the BGA pin information to obtain the pin spacing. d p Pin radius r p The set of center coordinates of the pins, and the distribution pattern of the pins on the two-dimensional plane, wherein the distribution pattern of the pins on the two-dimensional plane is a hexagonal array; S13: Calculate the line width, minimum line spacing, differential pair internal spacing, and equivalent differential line width to obtain design rule information. The design rule information includes routing geometry parameters, high-speed signal electrical constraints, and network output order constraints. The high-speed signal electrical constraints include that the differential pair is completed from the pin to the escape boundary on a single layer and that intermediate vias are prohibited. The network output order constraints are the specified output order that each network follows on the escape boundary.

3. The method for automatic differential line arc routing for high-density BGA according to claim 1, characterized in that, S2 constructs a graph model based on the routing information. The graph model construction includes generating virtual pins, a set of nodes, and a set of edges, including: S21: Based on netlist, BGA pin and design rule information, for any two BGA pins Pa and Pb that are physically adjacent, create a node at the midpoint of the line connecting their centers. The node coordinates are precisely calculated using the midpoint formula to obtain the node set. S22: Based on the spacing and layout pattern of BGA pins, calculate and create virtual pins outside the boundary pins. These virtual pins are located at the edge of the BGA array and are used to maintain the regularity and integrity of the graph model at the boundary. S23: Based on the node set, BGA pins and virtual pins, if the pin pairs corresponding to two nodes share a common BGA pin, then an undirected edge is established between the two nodes to ensure that each actual pin is surrounded by a regular hexagonal subgraph consisting of six nodes and six edges, thus obtaining the edge set; S24: Based on the node set and edge set, construct a hexagonal mesh graph model covering the entire BGA routing area. The hexagonal mesh graph model is used to ensure that each actual BGA pin is surrounded by a regular hexagonal subgraph consisting of six nodes and six edges, and each edge in the graph uniquely belongs to the hexagonal subgraph.

4. The method for automatic differential line arc routing for high-density BGA according to claim 1, characterized in that, S3, based on the graph model, performs constraint-driven path search and routing to obtain an initial polyline path, including: S31: Based on the differential signal set and design rules, each differential pair is regarded as a single virtual wire with an equivalent width, and a virtual differential line model is constructed. The equivalent width is determined by the sum of the line width of the two signal lines and the differential spacing. S32: Determine the start node and the end node. The start node includes the graph node corresponding to the midpoint of the line connecting the centers of the two source pins of the differential pair. The end node includes the node on the boundary of the wiring area. S33: Set fan-out order constraints. Based on the preset relative position relationship between the two signal lines of the differential pair, restrict the selection direction of the first wiring edge of the starting node. The preset relative position relationship includes clockwise or counterclockwise arrangement to prevent crossover within the differential pair. S34: Based on the virtual difference line model and fan-out order constraints, search for the shortest polyline path from the starting node to the ending node on the hexagonal mesh graph model to obtain the initial polyline path. The shortest polyline path is generated based on a network flow or A* search algorithm. The initial polyline path is physically represented as a polyline segment connecting the center points of each mesh and having a preset topology. The preset topology avoids obstacles and satisfies the overall routing trend of the difference pair.

5. The method for automatic differential line arc routing for high-density BGA according to claim 1, characterized in that, The optimization of the initial polyline path in step S4 to obtain a smooth circular arc path includes converting the polyline path into a smooth circular arc path using basic geometric rules, including: S41: Starting from the starting node, the angle formed by every three adjacent nodes is used to generate an arc with a central angle of 60 degrees, centered on the center pin of the hexagonal grid to which the middle node belongs, and with a radius of half the side length of the grid. S42: Based on the geometric symmetry of the hexagonal grid, the tangent directions of the first and second arc segments at the connection point are both perpendicular to the pin connection line, thus achieving tangent continuity between the two arc segments at the connection point. A smooth curve composed of multiple tangent arc segments and tangent segments replaces the initial polyline path, resulting in a smooth arc path.

6. The method for automatic differential line arc routing for high-density BGA according to claim 1, characterized in that, The post-processing path obtained by S5 based on the smooth arc path routing post-processing includes generating differential pairs and checking tangent continuity to ensure signal integrity, including: S51: Using the smooth circular arc path as the central axis, offset it equally to both sides of its normal direction to obtain differential pair traces. The offset distance is set based on the differential spacing in the design rules. S52: Based on differential pair routing, the transition correction at the pin connection is achieved by inserting a transition arc between the end of the signal line and the BGA pin to obtain a complete differential pair routing. The transition arc is tangent to the main path and extends smoothly to the center of the pin pad. S53: Perform integrity verification on the complete differential pair trace to obtain the post-processing path. The integrity verification includes tangent continuity check and design rule check. The tangent continuity check is used to ensure that the derivatives of all connection points are continuous. The design rule check is used to confirm that the line width, spacing and clearance distance meet the preset chip manufacturing process requirements.

7. The method for automatic differential line arc routing for high-density BGA according to claim 1, characterized in that, The S6 step, which involves routing optimization and verification based on post-processing, yields the final routing file, including: S61: Integrate the post-processing path to generate a complete single-layer cabling topology; S62: Based on the complete single-layer routing topology, generate a complete pin connection sequence for each differential pair, which records the positions of all critical nodes from the BGA pin to the escape boundary; S63: Based on the complete single-layer wiring topology and complete pin connection sequence, perform geometric layout data mapping to obtain geometric layout data containing arc segments and straight line segments, wherein the geometric layout data meets the requirement of full tangent continuity; S64: Convert the geometric layout data into a standard layout data format to obtain the final routing file, which includes the geometric features of arc segments and straight line segments, their layer information, and topological connection relationships.

8. A differential line arc-shaped automatic routing device for high-density BGA, wherein the differential line arc-shaped automatic routing device for high-density BGA is used to implement the differential line arc-shaped automatic routing method for high-density BGA as described in any one of claims 1-7, characterized in that, The device includes: Information module: used to acquire the routing information of the chip, which includes processing netlist information, BGA pin information and design rule information; Graph model module: used to construct a graph model based on the routing information, wherein the graph model construction includes generating virtual pins, node sets, and edge sets; Initial polyline module: used to perform constraint-driven path search and routing based on the graph model to obtain the initial polyline path; Arc Path Module: Used to optimize the initial polyline path to obtain a smooth arc path. The optimization includes converting the polyline path into a smooth arc path using basic geometric rules. Post-processing module: used to perform routing post-processing based on a smooth arc path to obtain the post-processed path, the routing post-processing including generating differential pairs and checking tangent continuity to ensure signal integrity; Optimization module: Used to perform routing optimization and verification steps based on the post-processing path to obtain the final routing file.

9. A differential line arc-shaped automatic routing device for high-density BGA, characterized in that, The differential line arc autorouting processor for high-density BGA; a memory storing computer-readable instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

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