Heterogeneous integration-based intelligent optimization method for power-storage-calculation three-dimensional packaging heat dissipation reliability

Abstract

The invention discloses an intelligent optimization method for power-memory-computing three-dimensional packaging heat dissipation reliability based on heterogeneous integration, and belongs to the technical field of advanced packaging and thermal management of integrated circuits. The method comprises the following steps: firstly, determining packaging structure parameters, and obtaining a sample data set through a mixed horizontal orthogonal test and finite element thermal simulation; secondly, on the basis of signal-to-noise ratio and range analysis, the influence weight of each parameter on the junction temperature is quantified, key parameters and secondary parameters are distinguished, the secondary parameters are fixed to the optimal level, the key parameters are determined, and the thermal simulation model is corrected; then training a random forest regression model based on all test data, and constructing an agent model; and finally, performing automatic collaborative optimization on the specific size of each layer of chip by adopting an NSGA-II multi-target genetic algorithm according to the proxy model, so as to minimize the highest junction temperature at the same time. According to the method, high-cost physical simulation is converted into an efficient intelligent optimization process, and the thermal reliability, the design efficiency and the product performance stability of packaging are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of advanced packaging and thermal management of integrated circuits, in particular to a power-memory-compute three-dimensional packaging heat dissipation reliability intelligent optimization method based on heterogeneous integration. BACKGROUND

[0002] With the rapid development of semiconductor technology, the functional density and performance requirements of integrated circuits are continuously increasing, and the traditional two-dimensional packaging method has been difficult to meet the heat dissipation and electrical performance requirements of high-performance chips. Three-dimensional integrated circuit (3D IC) packaging technology significantly improves the packaging density and performance by vertically stacking multiple chips (such as high-heat power chips, low-heat memory chips, and logic control chips). However, the thermal management and mechanical stress problems in the multi-layer chip stacking structure have become key factors restricting the development of 3D packaging technology, especially the high heat flux density of power chips will exacerbate the temperature rise of adjacent chips (such as memory chips), leading to performance degradation or even failure.

[0003] Existing research shows that when the total system power exceeds about 60 W or the power chip hotspot density is greater than 0.4 W mm -2 , the thermal coupling effect inside the three-dimensional stack will be dramatically amplified, and the junction temperature of the memory chip may rise by more than 15 °C, thereby triggering refresh frequency drift, logic chip clock frequency reduction, and early failure risk. Therefore, the industry generally limits the application boundary of three-dimensional "power-memory-compute" heterogeneous integration to low-to-medium power level scenarios, such as vehicle edge nodes, industrial distributed sensing, data center cold aisle power management modules, etc. Within the above-mentioned power range, chip materials, power chip location, chip-to-chip connection method, and chip size become the core variables that determine thermal performance. The conventional combination currently used in actual production - power chip located at the top of the stack, Si-based material, Epoxy Resin bonding - although the process is simple, but due to the low thermal conductivity coefficient of Epoxy Resin (≈0.2 W m -1 K -1 ), the thermal resistance is large, which hinders the downward conduction of heat, and the temperature rise of the memory chip is significant.

[0004] In summary, three-dimensional heterogeneous "power-memory-compute" integration has already been commercially viable in low-to-medium power scenarios, but there is an urgent need for a systematic design method to optimize the above-mentioned key parameters through thermal simulation and machine learning, thereby solving the heat dissipation contradiction when high-heat and low-heat chips coexist, and improving the packaging reliability and performance stability. SUMMARY

[0005] To address the above technical issues, this invention provides an intelligent optimization method for the thermal reliability of a three-dimensional power-storage-computing package based on heterogeneous integration. This method aims to achieve automated and global optimization of key package parameters (material, layout, connection, and size) through systematic experimental design, data-driven modeling, and multi-objective intelligent search, thereby significantly improving the thermal reliability of the integrated power-storage-computing package.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention provides an intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing, comprising the following steps:

[0008] Step S1: Determine the structural parameters of the three-dimensional heterogeneous integrated package; the structural parameters include the power chip material, the spatial position of the power chip in the stacked structure, the connection method between chips, and the size combination of each layer of chips; divide the structural parameters of the three-dimensional heterogeneous integrated package into different horizontal combinations and design orthogonal experiments based on the hybrid horizontal orthogonal method;

[0009] Step S2: Based on the parameter combinations of each group in the orthogonal experiment, establish the corresponding three-dimensional finite element thermal simulation model, perform thermal simulation analysis, and obtain the thermal performance indicators of each group; the thermal performance indicators include the junction temperature of each chip layer;

[0010] Step S3: Based on the chip junction temperature data obtained in Step S2, the Taguchi method is used to perform signal-to-noise ratio (SNR) analysis on the small-scale characteristics of the three-layer chip junction temperature. The highest junction temperature of the three-layer chip in each group of experiments is used as the representative value to calculate the corresponding SNR. Further, based on the mean SNR, the range analysis method is used to determine the degree of influence of each structural parameter on the chip junction temperature, and the key parameters that have a significant impact on the junction temperature and the minor parameters that have a smaller impact are distinguished accordingly.

[0011] Based on this, in order to achieve unified comparison of multiple factors and multiple indicators, weights are assigned according to the range of each factor, and a weighted comprehensive scoring model based on a percentage system is constructed to conduct intermediate evaluation of each orthogonal experimental combination; the comprehensive score is used to assist in the analysis of parameter importance and subsequent training and evaluation of machine learning models, and is not used as the final optimization target or the final output result.

[0012] Step S4: Based on the range analysis results of step S3, fix the secondary parameters at their optimal levels and conduct targeted comparative simulations on the key parameters to determine their optimal values; based on the determined optimal values ​​of all parameters, correct the three-dimensional finite element thermal simulation model to provide a unified simulation basis for subsequent machine learning modeling and size optimization.

[0013] Step S5: Using the dimensions of each chip layer as optimization parameters, and based on all data from the orthogonal experiment, using all combinations of structural parameters as input features and thermal performance indicators as output labels, train a random forest regression model to establish a proxy model between packaging parameters and thermal performance.

[0014] Step S6: Based on the trained random forest regression model, a multi-objective optimization algorithm is used to collaboratively optimize the size of each chip layer; the multi-objective optimization aims to minimize the highest junction temperature of the stacked chips.

[0015] Step S7: Using the modified three-dimensional finite element thermal simulation model, the optimized structural parameters are simulated to obtain the optimized junction temperature of each chip layer.

[0016] Furthermore, in step S1, the power chip materials include Si and SiC; the spatial positions of the power chips in the stacked structure include upper, middle, and lower layers; the inter-chip connection methods include SnAg bump+underfill, SnPb bump+underfill, Cu bump+underfill, and Epoxy Resin; and the chip sizes include stepped size combinations and uniform size combinations.

[0017] Further, in step S3, the signal-to-noise ratio is calculated based on the minimization characteristic, and the calculation formula is:

[0018]

[0019] in, This represents the highest junction temperature value among the three-layer chips in the i-th group of experiments.

[0020] Furthermore, in step S3, the range analysis method is used to calculate the mean signal-to-noise ratio of all experimental groups under the same structural parameters.

[0021] Furthermore, the key parameter mentioned in step S4 is the connection method between chips.

[0022] Furthermore, in step S5, when training the random forest regression model, a comprehensive score is used to assist in the analysis, a grid search method is used for hyperparameter tuning, and the optimal model configuration is determined through cross-validation; the comprehensive score is calculated by a percentage-weighted comprehensive score model constructed based on the range size, factor weights, and signal-to-noise ratio.

[0023] Furthermore, in step S6, the multi-objective optimization algorithm is the NSGA-II multi-objective genetic algorithm.

[0024] Furthermore, the implementation parameters of the NSGA-II algorithm include: a population size of 100, 50 iterations, simulated binary crossover and polynomial mutation, a crossover probability of 0.9, and a mutation probability of 0.1.

[0025] In a second aspect, the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method.

[0026] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method.

[0027] The present invention has the following beneficial effects:

[0028] (1) It realizes a paradigm shift from "experience-based trial and error" to "data-driven intelligent optimization". By constructing a random forest proxy model, the time-consuming high-fidelity physical simulation is transformed into millisecond-level performance prediction, making it possible to conduct efficient and global exploration of the vast design space, and shortening the optimization cycle from several days to hours or even minutes.

[0029] (2) This invention solves the problem of multi-variable and multi-objective collaborative optimization. It creatively distinguishes the influence weights of parameters, first fixing secondary variables through range analysis to simplify the problem dimensions, and then focusing on core variables to perform multi-objective optimization using the NSGA-II algorithm. This method systematically balances the often conflicting objectives of "reducing hotspot temperature" and "improving temperature uniformity," directly outputting a series of Pareto optimal solutions for designers to weigh, thus enhancing the scientific and systematic nature of the design.

[0030] (3) Significantly improved thermal reliability and design quality of the package. Examples show that the optimized three-dimensional packaging structure, achieved by the method of this invention, can significantly reduce the highest junction temperature of the chip from 136.56℃ to 107.97℃, a temperature reduction of over 28℃, while effectively controlling the temperature difference between layers within a very small range. This fundamentally alleviates the thermal coupling effect in the three-dimensional stack, providing a stable low-temperature operating environment for memory chips and logic chips, and greatly improving the long-term reliability of the product under harsh operating conditions.

[0031] (4) It has good engineering applicability and scalability. The method of this invention does not depend on a specific package model, and its "simulation-learning-optimization" framework can be flexibly applied to other types of advanced package thermal design problems. By adjusting the design variables and optimization objectives, this method can easily adapt to different application scenarios and technical requirements, and has broad industrial promotion value. Attached Figure Description

[0032] Figure 1This is a schematic diagram of the specific process of the present invention;

[0033] Figure 2 This is a three-dimensional packaging product chip stack-up structure diagram and side view according to an embodiment of the present invention;

[0034] Figure 3 This is a three-dimensional packaging product structure framework diagram according to an embodiment of the present invention;

[0035] Figure 4 This is a planar cloud diagram of the three-dimensional packaging temperature distribution before and after optimization in an embodiment of the present invention;

[0036] Figure 5 This is a flowchart illustrating the intelligent prediction logic of the machine learning combined with multi-objective parameter algorithm in an embodiment of the present invention.

[0037] Figure 6 This is an optimization result diagram of the machine learning combined with multi-objective parameter optimization algorithm provided in an embodiment of the present invention;

[0038] Figure 7 This is a comparison diagram of the three-dimensional packaging junction temperature before and after optimization in an embodiment of the present invention. Detailed Implementation

[0039] To make the present invention easier to understand, the present invention will be further described below with reference to specific embodiments and accompanying drawings. These embodiments and drawings are not intended to limit the present invention in any way. They are only used to illustrate the present invention and are not intended to limit the scope of the present invention. Any modifications or changes to the present invention that are easily implemented by those skilled in the art without departing from the technical solutions of the present invention will fall within the scope of the claims of the present invention.

[0040] like Figure 2 , 3 As shown, the three-dimensional packaging product structure in this embodiment includes: upper chip 1, middle chip 2, lower chip 3, chip-to-chip interconnects 4, LTCC substrate 5, substrate-to-substrate interconnects 6, and HTCC substrate 7. In this embodiment, the positions of the logic and memory chips are fixed, while the position of the power chip is set as a variable.

[0041] A smart optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing, such as... Figure 1 As shown, it includes the following steps:

[0042] S1 determines the three-dimensional packaging structure parameters of the chip and selects the power chip material types required for the orthogonal experiment, including Si and SiC; the power chip positions include top, middle, and bottom; the types of inter-chip connections include SnAg bump+underfill, SnPbbump+underfill, Cu bump+underfill, and Epoxy Resin; the chip size combinations include: Combination 1 (stepped dimensions): for example, bottom chip 7.2 mm × 7.2 mm × 0.15 mm, middle chip 5.4 mm × 5.4 mm × 0.15 mm, top chip 3.8 mm × 3.8 mm × 0.15 mm, or Combination 2 (uniform size): for example, all three chips are 5.4 mm × 5.4 mm × 0.15 mm. Based on the engineering sample data from actual production by the enterprise, different level combinations of various material process parameters are divided, as shown in Table 1.

[0043] Table 1 Experimental factors and levels

[0044]

[0045] S2 designed a hybrid horizontal orthogonal experiment and used Flotherm modeling software to create a finite element model. The power, storage, and logic chip operating power settings were configured for the finite element model (the power chip's operating power was required to be greater than that of the storage and logic chips; in this embodiment, the power chip's operating power was 2.5W, and the storage and logic chips' operating power was 1W). After setting the power of the established 3D packaged product finite element model, simulation was performed in Flotherm software. The simulation yielded quality indicators, which were set as the junction temperatures of the upper, middle, and lower chip layers. The signal-to-noise ratio of each quality indicator was calculated and statistically analyzed, as shown in Table 2.

[0046] Table 2. Mixed-level orthogonal experiment table

[0047] Table 2. Mixed-level orthogonal experiment table (continued)

[0048] This invention employs the Taguchi method to perform signal-to-noise ratio (SNR) analysis on the junction temperature characteristics of three-layer chips. Since each experiment includes three junction temperature parameters (top, middle, and bottom layers), and to obtain a single evaluation metric, and considering that the thermal reliability of the package is primarily determined by the highest junction temperature (a lower highest temperature better meets reliability requirements), this invention uses the "maximum junction temperature as a representative value" to calculate the SNR.

[0049] The formula for calculating the small characteristic is as follows:

[0050] in, This represents the highest junction temperature value among the three-layer chips in the i-th experimental group. A higher signal-to-noise ratio indicates a lower junction temperature and better heat dissipation performance for that experimental group.

[0051] After obtaining the signal-to-noise ratio (SNR), S3 performed range analysis on each factor according to the Taguchi method. First, based on Table 2, factors were grouped by level (e.g., power chip location divided into three groups (top, middle, and bottom); power chip material divided into two groups; inter-chip connection method divided into four groups; chip size combination divided into two groups), and the mean SNR of all experiments at the same level was calculated. Factors In the Mean signal-to-noise ratio at each level:

[0052]

[0053] in, As factors The number of experimental groups;

[0054] Range analysis was used to calculate the weight of each factor (power chip material, power chip location, inter-chip interconnection method, and chip size combination) on the signal-to-noise ratio (SNR). By calculating the mean SNR of each factor at different levels, the range (Delta value) was obtained. The larger the range, the greater the influence, thus determining the ranking of the factors' influence on the junction temperature.

[0055] The formula for calculating the range is:

[0056]

[0057] in, , As factors In the The mean maximum signal-to-noise ratio and the mean minimum signal-to-noise ratio at each level;

[0058] The results are shown in Table 3-6;

[0059] Table 3 Range analysis results of power chip location

[0060] Table 4 Range Analysis Results of Power Chip Materials

[0061] Table 5. Range analysis results of inter-chip connection methods

[0062] Table 6 Range Analysis Results of Chip Size Combinations

[0063] Weight calculation formula:

[0064]

[0065] As can be seen from Table 3-6, the chip-to-chip connection method (C) has the largest range, indicating that it has the most significant impact on junction temperature, followed by chip size combination (D).

[0066] To achieve unified evaluation across multiple indicators, this invention assigns factor weights based on the magnitude of the range and constructs a weighted comprehensive scoring model on a percentage basis. The comprehensive score for each experiment is calculated as follows:

[0067]

[0068] Among them, W i x is the overall score for the i-th group of experiments. k Weight of the kth factor

[0069] Let the first The weighted comprehensive evaluation value of the group experiment is Then its corresponding percentage-based comprehensive score Defined as:

[0070]

[0071] in:

[0072] For the first The weighted comprehensive evaluation value of the group experiments;

[0073] The maximum value of the weighted comprehensive evaluation value among all experimental groups;

[0074] It is the minimum weighted comprehensive evaluation value among all experimental groups.

[0075] The higher the overall score, the better the heat dissipation performance of the experimental group.

[0076] Table 7 Overall Scoring Results

[0077] According to the range analysis results, the inter-chip connection method (C) has the largest influence weight (0.59), far exceeding that of chip size combination (0.26), power chip location (0.12), and chip material (0.03). To ensure the effectiveness of the optimization, the optimal levels of the three secondary factors are first determined based on the average values ​​of factors in Tables 3-6, namely:

[0078] • The power chip is positioned on the lower layer (maximum S / N, lowest temperature);

[0079] • SiC was selected as the chip material (although the chip material has a relatively small weight in the range analysis, the mean signal-to-noise ratio results show that SiC material exhibits a lower junction temperature level in all combinations, therefore SiC was selected as the power chip material in subsequent optimizations).

[0080] • Chip size combination 1 is adopted (meets process constraints and has a larger heat dissipation area gradient, which is beneficial to heat diffusion). (Optimal average level of power chip position 3 (lower layer): -41.57, optimal average level of power chip material 1 (Si): -41.65, optimal average level of chip size combination 1; due to the influence of other factors on the average level of chip material, based on operating conditions and practical experience, SiC is selected as the chip material.)

[0081] After fixing the above three factors, we only conducted in-depth single-factor verification on the dominant factor, "inter-chip interconnection method." Comparative simulations were performed on four interconnection methods: SnAg+underfill, SnPb+underfill, Cu+underfill, and Epoxy Resin. The results show:

[0082] Cu bump+underfill exhibits the highest thermal conductivity, significantly reducing the maximum junction temperature of the three-layer chip, and boasts the highest signal-to-noise ratio (-41.07 dB), making it the optimal connection method. Subsequently, the finite element model was modified.

[0083] S4 uses the combined parameters (power chip location, chip material, inter-chip connection method, and chip size combination) obtained from the mixed-level orthogonal experiment as input features, junction temperature as the output label, and the comprehensive score for modeling and evaluation of random forest and optimization, constructing a random forest regression model. At this stage, the comprehensive score is used to assist in analyzing the influence weights of each factor and to provide an indirect reference for evaluating the subsequent model training effect; it is not directly used as the output label or optimization target of the machine learning model. The specific steps are as follows:

[0084] Data Preparation and Data Segmentation: Packaging parameter combinations were extracted from the orthogonal experimental design table as input features, including power chip location (top / middle / bottom), chip material (Si / SiC), inter-chip interconnection method (SnAg+underfill, SnPb+underfill, Cu+underfill, Epoxy Resin), and chip size combinations (Combination 1; Combination 2). The junction temperature of the three-layer chip corresponding to each parameter group was used as the output label. A stratified sampling method was used to divide the data into training and test sets in a 7:3 ratio to ensure a balanced distribution of various parameter combinations between the training and test sets.

[0085] Random Forest Model Training: Initialize the hyperparameters of the random forest: 100 decision trees, maximum depth of 10, and minimum number of leaf samples of 2. Randomly sample with replacement from the training set to construct multiple decision trees. For each decision tree, randomly select some features for optimal splitting at each node. Evaluate feature importance using the Gini coefficient to complete model training.

[0086] Model Evaluation and Optimization: Model performance was evaluated using a test set, and the mean squared error (MSE) between the predicted and actual junction temperatures was calculated. A grid search method was used to optimize hyperparameters, with the search range including the number of decision trees (50-200), maximum depth (5-20), and minimum number of leaf samples (1-5). The optimal parameter combination was selected through 5-fold cross-validation, ultimately determining the best model configuration as 150 decision trees, 15 maximum depth, and 3 minimum number of leaf samples.

[0087] After training and optimization, the random forest model can accurately predict the comprehensive score of different chip size parameters, providing a reliable basis for subsequent optimization.

[0088] To further optimize the package structure parameters, S5 employs NSGA-II (Non-dominated sorting genetic algorithm) for multi-objective optimization. The optimization objective is to minimize the junction temperature of the three-layer chip while considering the reliability of the package structure. The specific steps are as follows:

[0089] Key parameters were fixed: the power chip was positioned on the lower layer, SiC was selected as the chip material, and Cu+underfill was used for inter-chip connections. Chip size parameters were used as optimization variables.

[0090] Optimization objectives: Establish a multi-objective optimization problem: Objective 1 is to minimize the junction temperature of the upper chip, Objective 2 is to minimize the junction temperature of the middle chip, and Objective 3 is to minimize the junction temperature of the lower chip. Constraints include ensuring the total chip thickness does not exceed 1mm and that the dimensions of each chip layer meet manufacturing process requirements.

[0091] NSGA-II Algorithm Implementation: The initial population size is 100, and the number of iterations is 50. Simulated binary crossover (SBX) and a polynomial mutation operator are used, with a crossover probability of 0.9 and a mutation probability of 0.1. In each generation, non-dominated sorting and crowding distance calculation are performed, and Pareto front solutions are retained. After 50 iterations, the optimal solution is selected from the Pareto front: lower-layer chip 7.4×7.4×0.15mm, middle-layer chip 6.4mm×6.4mm×0.15mm, and upper-layer chip 3.8mm×3.8mm×0.15mm.

[0092] S6 uses the optimal parameter combination obtained from the joint optimization of random forest and NSGA-II: the chip material is SiC, the power chip is located in the lower layer, and the inter-chip connection method is Cu bump + underfill. The optimal chip size combination obtained in step 5 is then substituted into the finite element model for thermal simulation verification. Simulation results show:

[0093] The optimized packaging structure significantly reduces the chip junction temperature, improving heat dissipation performance and reliability.

[0094] S7 finally feeds back the key parameter combination of the 3D packaging structure: the chip material is SiC, the power chip is located in the lower layer, the chip connection method is Cu bump + underfill, and the chip size parameters are the optimal continuous size combination determined in step S5 (lower layer chip 7.4×7.4×0.15mm, middle layer chip 6.4mm×6.4mm×0.15mm, upper layer chip 3.8mm×3.8mm×0.15mm) to the industry. Using finite element simulation software and analyzing the post-processed simulation results is an indispensable part of actual production, improving the accuracy of obtaining the optimal process parameter combination and packaging reliability, reducing production costs, and addressing the hidden reliability issues of chip packaging that cannot be predicted in current production lines.

[0095] like Figure 4 As shown in the figure, the temperature gradients before and after optimization show that the junction temperature is significantly reduced.

[0096] In addition to the examples described above, this invention has other embodiments. All technical solutions formed by equivalent substitution or equivalent transformation fall within the protection scope claimed by this invention.

[0097] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. However, the above description is merely a specific embodiment of the present invention, and the technical features of the present invention are not limited thereto. Any other embodiments derived by those skilled in the art without departing from the technical solution of the present invention should be covered within the patent scope of the present invention.

Claims

1. A method for intelligent optimization of heat dissipation reliability in a three-dimensional package based on heterogeneous integration of power, storage, and computing, characterized in that, Includes the following steps: Step S1: Determine the structural parameters of the three-dimensional heterogeneous integrated package; the structural parameters include the power chip material, the spatial position of the power chip in the stacked structure, the connection method between chips, and the size combination of each layer of chips; divide the structural parameters of the three-dimensional heterogeneous integrated package into different horizontal combinations and design orthogonal experiments based on the hybrid horizontal orthogonal method; Step S2: Based on the parameter combinations of each group in the orthogonal experiment, establish the corresponding three-dimensional finite element thermal simulation model, perform thermal simulation analysis, and obtain the thermal performance indicators of each group; the thermal performance indicators include the junction temperature of each chip layer; Step S3: Based on the chip junction temperature data obtained in Step S2, the Taguchi method is used to perform signal-to-noise ratio analysis of the small-scale characteristics of the three-layer chip junction temperature. The highest junction temperature of the three-layer chip in each group of experiments is used as the representative value to calculate the corresponding signal-to-noise ratio. Further, based on the mean signal-to-noise ratio, the range analysis method is used to determine the degree of influence of each structural parameter on the chip junction temperature, and the key parameters and minor parameters that have a significant impact on the junction temperature are distinguished accordingly. Step S4: Based on the range analysis results of step S3, fix the minor parameters at the optimal level and conduct comparative simulations on the key parameters to determine their optimal values. Based on the determined optimal values ​​of all parameters, the three-dimensional finite element thermal simulation model is corrected. Step S5: Using the dimensions of each chip layer as optimization parameters, the data involving structural parameter combinations in the orthogonal experiment as the training set, and the thermal performance index as the output label, a random forest regression model is trained to establish a proxy model between packaging parameters and thermal performance. Step S6: Based on the trained random forest regression model, a multi-objective optimization algorithm is used to collaboratively optimize the size of each chip layer; The multi-objective optimization aims to minimize the highest junction temperature of the stacked chips. Step S7: Using the modified three-dimensional finite element thermal simulation model, the optimized structural parameters are simulated to obtain the optimized junction temperature of each chip layer.

2. The intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing as described in claim 1, is characterized in that, In step S1, the power chip materials include Si and SiC; the spatial positions of the power chips in the stacked structure include upper, middle and lower layers; the inter-chip connection methods include SnAg bump+underfill, SnPb bump+underfill, Cubump+underfill, and Epoxy Resin; and the chip size combinations include stepped size combinations and uniform size combinations.

3. The intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing as described in claim 1, is characterized in that... In step S3, the signal-to-noise ratio is calculated based on the minimization characteristic, and the calculation formula is as follows: ； in, This represents the highest junction temperature value among the three-layer chips in the i-th group of experiments.

4. The intelligent optimization method for heat dissipation reliability of three-dimensional packaging based on heterogeneous integration of power, storage, and computing as described in claim 1, is characterized in that, In step S3, the range analysis method is used to calculate the signal-to-noise ratio based on the mean of all experimental groups under the same structural parameters.

5. The intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing as described in claim 1, is characterized in that... The key parameter mentioned in step S4 is the connection method between chips.

6. The intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing as described in claim 1, is characterized in that... In step S5, when training the random forest regression model, a comprehensive score is used to assist in the analysis, a grid search method is used for hyperparameter tuning, and the optimal model configuration is determined through cross-validation. The comprehensive score is calculated by a percentage-weighted comprehensive score model constructed based on the range size, factor weights, and signal-to-noise ratio.

7. The intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing as described in claim 1, is characterized in that... In step S6, the multi-objective optimization algorithm is the NSGA-II multi-objective genetic algorithm.

8. The intelligent optimization method for heat dissipation reliability of a three-dimensional package based on heterogeneous integration of power, storage, and computing as described in claim 7, is characterized in that... The implementation parameters of the NSGA-II algorithm include: a population size of 100, 50 iterations, simulated binary crossover and polynomial mutation, a crossover probability of 0.9, and a mutation probability of 0.

1.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-8.

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