Switching power supply clamping undervoltage protection circuit

Abstract

The invention relates to a switching power supply clamping undervoltage protection circuit, which is characterized by comprising a voltage division circuit, a clamping circuit and a slow control circuit, the voltage division circuit is used for acquiring an input voltage sampling signal and generating a corresponding voltage value, and the voltage value is used for controlling the on-off of the PWM controller and the maximum pulse width duty ratio; the clamping circuit is used for stabilizing the UVLO end of the PWM controller at a clamping voltage value when the input voltage is increased to a set value; and the slow control circuit is used for setting time delay of starting and shutting off of the power supply. The whole circuit is only composed of the divider resistor, the voltage stabilizing diode, the capacitor and the PWM controller, the structure is simple and easy to understand, design and calculation are convenient and fast, complex components are not needed, hardware cost and assembly difficulty are reduced, meanwhile, fault points are reduced, and the reliability and stability of circuit operation are improved.

Description

Technical Field

[0001] This invention relates to the field of undervoltage protection technology for switching power supplies, and specifically to a clamping undervoltage protection circuit for switching power supplies. Background Technology

[0002] Undervoltage protection circuits are among the most commonly used circuits in the field of switching power supplies. This circuit can not only effectively protect the power module from damage caused by voltage drop or input-side abnormalities, but also effectively reduce the risk of power supply damage during the startup phase.

[0003] Currently, the recommended undervoltage protection scheme for commonly used PWM controllers such as the LM5032, LM5026, and LM5034 series consists of two voltage divider resistors. Although this scheme allows setting the undervoltage value and hysteresis window size through two voltage divider circuits, the undervoltage protection circuit affects the maximum output pulse width duty cycle, thereby directly limiting the usable range of the input voltage and making it difficult for such PWM controllers to fully utilize their functions.

[0004] In addition, another clamping undervoltage protection circuit is based on the dual voltage divider resistor scheme, with a precision voltage regulator reference connected in parallel across the lower voltage divider resistor. Although this design can control the maximum output duty cycle and widen the input voltage range of the PWM controller, it was found in actual debugging that the undervoltage point drift phenomenon is serious under different temperature environments, and it cannot be used in wide temperature range application scenarios.

[0005] Therefore, in order to address the shortcomings of existing undervoltage protection circuits, a switching power supply clamping undervoltage protection circuit is proposed. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a switching power supply clamping undervoltage protection circuit.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A switching power supply clamping undervoltage protection circuit includes a voltage divider circuit, a clamping circuit, and a buffer control circuit. The voltage divider circuit is used to acquire the input voltage sampling signal and generate the corresponding voltage value. The voltage value is used to control the on / off state of the PWM controller and the maximum pulse width duty cycle. The clamping circuit is used to stabilize the UVLO terminal of the PWM controller at the clamping voltage value when the input voltage increases to the set value. The delay control circuit is used to set the delay for power-on and power-off.

[0008] Furthermore, the voltage divider circuit includes voltage divider resistors R1, R2, and R3, and a PWM controller N1; the voltage divider resistors R1, R2, and R3 are connected in series between the positive input and the input ground, and the UVLO port of the PWM controller N1 is connected to the common terminal of the voltage divider resistors R2 and R3.

[0009] Furthermore, the clamping circuit includes a Zener diode V1; the cathode of the Zener diode V1 is connected to the common terminal of the voltage divider resistors R1 and R2, and the anode of the Zener diode V1 is connected to the input ground.

[0010] Furthermore, the buffer control circuit includes a capacitor C1; one end of the capacitor C1 is connected to the common terminal of the voltage divider resistors R1 and R2, and the other end is connected to the input ground.

[0011] Furthermore, the PWM controller N1 is an LM5032, LM5026 or LM5034 series device, with an undervoltage point of 1.25V at its UVLO port and an internal 20μA current source.

[0012] Furthermore, the resistance values ​​of the voltage divider resistors R1, R2, and R3 satisfy the following: R1 + R2 = V 迟滞窗口 / 20μA, R3=1.25V×(R1+R2) / (V 输入欠压点 -1.25V); Among them, V 迟滞窗口 To preset the undervoltage hysteresis voltage value, V 输入欠压点 To set the input undervoltage protection threshold.

[0013] Furthermore, the UVLO terminal clamping voltage V of the PWM controller N1 UVLO satisfy: V UVLO =V V1× R3 / (R2+R3); Among them, V V1 This is the reverse breakdown voltage of the Zener diode V1.

[0014] Compared with the prior art, the advantages of the present invention are: (1) Compared with the undervoltage scheme of dual voltage divider resistor recommended by chip manufacturers, the present invention stabilizes the UVLO terminal of PWM controller N1 at the preset clamping voltage value when the input voltage rises by cooperating with the voltage divider circuit and the clamping circuit. This can prevent the maximum pulse width duty cycle from continuously decreasing, thereby effectively expanding the applicable range of input voltage and adapting to scenarios such as wide input voltage range power supply and surge protection power supply.

[0015] (2) Compared with other clamping undervoltage circuit solutions, the present invention has the characteristics of accurate undervoltage point and small temperature drift, and is suitable for application fields with a wide operating temperature range. Compared with the clamping undervoltage circuit solution with a precision voltage regulator reference connected in parallel across the voltage divider resistors, the present invention uses a Zener diode V1 to form a clamping circuit, and with the precise design of the three-stage voltage divider resistors, the undervoltage point is more accurate and the temperature drift is small, which can meet the application requirements of a wide temperature range.

[0016] (3) Compared with the existing undervoltage scheme, the present invention adds a slow control circuit with a slow control capacitor C1. The delay control of power supply start-up and shutdown is realized through capacitor charging and discharging. It can be directly applied to circuits with multiple output timing control requirements, thus improving the adaptability of the circuit. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the switching power supply clamping undervoltage protection circuit in this invention.

[0018] in: 1. Voltage divider circuit; 2. Clamping circuit; 3. Buffer control circuit; 4. Clamping undervoltage protection circuit. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] like Figure 1 The circuit shown is a switching power supply clamping undervoltage protection circuit, which includes a voltage divider circuit, a clamping circuit, and a buffer control circuit.

[0021] The voltage divider circuit acquires the input voltage through the voltage divider resistor and generates a corresponding sampled voltage value. The level of this voltage value determines the on / off state of the PWM controller N1 and the maximum pulse width duty cycle.

[0022] The clamping circuit ensures that when the input voltage increases to a set value, the UVLO terminal of the PWM controller N1 is regulated at a preset clamping voltage value, so that the maximum duty cycle of the output pulse width of the PWM controller N1 no longer decreases. This solves the problem of insufficient duty cycle causing the output voltage to be unstable in high-voltage input scenarios and effectively broadens the applicable range of PWM input voltage.

[0023] The slow control circuit, through the slow control capacitor, sets the delay time when the power supply starts and shuts down, and is suitable for multi-output power supply scenarios with timing requirements.

[0024] As a further improvement to the above scheme, such as Figure 1 As shown, the voltage divider circuit 1 includes voltage divider resistors R1, R2, and R3, and a PWM controller N1. The voltage divider resistors R1, R2, and R3 are connected in series between the input positive and input ground. The UVLO port of the PWM controller N1 is connected to the common terminal of the voltage divider resistors R2 and R3. The voltage division result of the voltage divider resistors R1, R2, and R3 is the undervoltage sampling signal voltage value input to the UVLO port of the PWM controller N1. Furthermore, the UVLO port internally provides a current source with a hysteresis window of 20μA. The size of the hysteresis window is determined by the total resistance of the voltage divider resistors R1 and R2. With proper selection of the voltage divider resistors, precise setting of the input voltage undervoltage point can be achieved. The voltage divider circuit 1 samples the input voltage through each voltage divider resistor and converts it into a corresponding voltage value. The level of this voltage value directly determines the on / off state of the PWM controller N1 and plays a crucial role in controlling its maximum pulse width duty cycle.

[0025] As a further improvement to the above scheme, such as Figure 1 As shown, the clamping circuit 2 includes a Zener diode V1. The cathode of the Zener diode V1 is connected to the common terminal of the voltage divider resistors R1 and R2, and the anode of the Zener diode V1 is connected to the input ground. As the input voltage increases, when the voltage division value of the voltage divider resistors exceeds the reverse breakdown voltage of the Zener diode V1, the Zener diode V1 in the clamping circuit starts to work, stabilizing the UVLO port at the design value, thereby controlling the maximum duty cycle of the PWM controller to no longer decrease, thus ensuring that the output voltage will not fail to stabilize due to insufficient duty cycle.

[0026] As a further improvement to the above scheme, such as Figure 1 As shown, the buffer control circuit 3 includes a capacitor C1. One end of the capacitor C1 is connected to the common terminal of voltage divider resistors R1 and R2, and the other end is connected to the input ground. By charging and discharging the capacitor C1, the sampling of the input voltage at the UVLO port is delayed, thereby allowing the power supply output voltage to start and shut down with a delay. This scheme can also be used for timing design of multi-output power supplies with output timing requirements.

[0027] As a further improvement to the above technical solution, the PWM controller N1 adopts a series of PWM controllers such as LM5032, LM5026, and LM5034. This PWM controller uses the UVLO port for undervoltage sampling, and the undervoltage point of the UVLO port is 1.25V. In the voltage divider circuit, by reasonably designing the resistance values ​​of the voltage divider resistors, the undervoltage of the input voltage is proportionally divided to 1.25V. At the same time, a 20μA current source is set inside the chip to provide a hysteresis voltage window. The design value of the voltage divider resistors R1, R2, and R3 in the voltage divider circuit is R1 + R2 = V. 迟滞窗口 / 20μA, R3=1.25V×(R1+R2) / (V 输入欠压点 -1.25V). In the clamping circuit, the clamping voltage V at the undervoltage UVLO port of the PWM controller is... UVLO The design value is: V UVLO =V V1 ×R3 / (R2+R3), where V V1 This is the reverse breakdown voltage of the Zener diode V1; in the buffer control circuit, the larger the capacitance of C1, the longer the circuit delay.

[0028] The circuit includes multiple voltage divider resistors, a clamping Zener diode, and a buffer capacitor. The DC voltage signal sets the undervoltage protection point and undervoltage window size in the PWM controller through the resistance values ​​of the upper and lower voltage divider resistors. Simultaneously, the clamping Zener diode and multi-stage voltage divider resistors allow for clamping voltage settings on the sampled voltage, limiting the reduction in the maximum output pulse width duty cycle of the PWM controller. Furthermore, the buffer capacitor allows for flexible setting of the sampling signal delay time. Through a simple design using multiple resistors and Zener diodes, the clamping undervoltage protection circuit solves the problem in applications requiring wide input voltage and surge voltage resistance, where the maximum output duty cycle of PWM controllers such as LM5032, LM5026, and LM5034 series cannot be output normally due to the undervoltage protection circuit limiting the maximum output duty cycle. This circuit features a novel design concept, simple structure, flexibility, ease of calculation, high reliability, low undervoltage point temperature drift, and a wide range of applications.

[0029] In summary, this invention achieves undervoltage protection, undervoltage window, maximum duty cycle, and delay setting through the cooperation of voltage divider circuit, clamping circuit, and buffer control circuit. It solves the problems of undervoltage protection and incompatibility with wide input voltage in PWM controllers such as LM5032, LM5026, and LM5034. It is simple and convenient to calculate and has a wide range of applications.

[0030] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A switching power supply clamping undervoltage protection circuit, characterized in that, Includes voltage divider circuit, clamping circuit and buffer control circuit; The voltage divider circuit is used to acquire the input voltage sampling signal and generate the corresponding voltage value. The voltage value is used to control the on / off state of the PWM controller and the maximum pulse width duty cycle. The clamping circuit is used to stabilize the UVLO terminal of the PWM controller at the clamping voltage value when the input voltage increases to the set value. The delay control circuit is used to set the delay for power-on and power-off.

2. The switching power supply clamping undervoltage protection circuit according to claim 1, characterized in that, The voltage divider circuit includes voltage divider resistors R1, R2, and R3, and a PWM controller N1; The voltage divider resistors R1, R2, and R3 are connected in series between the input positive and the input ground in sequence, and the UVLO port of the PWM controller N1 is connected to the common terminal of the voltage divider resistors R2 and R3.

3. The switching power supply clamping undervoltage protection circuit according to claim 1, characterized in that, The clamping circuit includes a Zener diode V1; the cathode of the Zener diode V1 is connected to the common terminal of the voltage divider resistors R1 and R2, and the anode of the Zener diode V1 is connected to the input ground.

4. The switching power supply clamping undervoltage protection circuit according to claim 1, characterized in that, The buffer control circuit includes a capacitor C1; one end of the capacitor C1 is connected to the common terminal of the voltage divider resistors R1 and R2, and the other end is connected to the input ground.

5. The switching power supply clamping undervoltage protection circuit according to claim 2, characterized in that, The PWM controller N1 is an LM5032, LM5026 or LM5034 series device, with an undervoltage point of 1.25V at its UVLO port and an internal 20μA current source.

6. The switching power supply clamping undervoltage protection circuit according to claim 2, characterized in that, The resistance values ​​of the voltage divider resistors R1, R2, and R3 satisfy the following: R1+R2=V 迟滞窗口 / 20μA,R3=1.25V×(R1+R2) / (V 输入欠压点 -1.25V); Among them, V 迟滞窗口 To preset the undervoltage hysteresis voltage value, V 输入欠压点 To set the input undervoltage protection threshold.

7. The switching power supply clamping undervoltage protection circuit according to claim 3, characterized in that, The UVLO terminal clamping voltage V of the PWM controller N1 UVLO satisfy: In UVLO =V V1× R3 / (R2+R3); Among them, V V1 This is the reverse breakdown voltage of the Zener diode V1.

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