A low voltage power high voltage charge pump switching circuit and control method

Abstract

The application discloses a low-voltage power high-voltage charge pump switch circuit and a control method. The circuit comprises an NMOS transistor N3 as a switch tube, a single charge pump capacitor C, a charging branch and a switch driving module. The charging branch is connected between a power supply and the ground and is used for charging the capacitor; and the switch driving module is coupled between the capacitor, an input node and a gate of the switch tube and is used for driving the switch tube. The two modules are alternately controlled by a pair of opposite non-overlapping clock signals S1 and S2: the capacitor is charged in a charging stage, and the capacitor is connected with an input signal in a driving stage; and a high-voltage driving signal is generated at the gate of the switch tube by using the stored voltage to turn on the switch tube. The scheme only uses one capacitor, the circuit structure is simple, there is no static current in the off stage of the switch tube, the fast and stable work of the charge pump switch at a megahertz high frequency is realized, and the chip area is significantly saved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a charge pump circuit. Background Technology

[0002] Currently, there are two main types of switches with charge pumps, but they generally suffer from the following drawbacks:

[0003] First, many traditional charge pump designs employ relatively complex circuit structures and control logic to achieve stable and reliable voltage boosting. This complexity not only increases design difficulty and chip area, but more importantly, it directly leads to longer charge pump startup and voltage settling times. When switching needs to be performed at high frequencies (e.g., megahertz), these types of switches cannot meet the requirements of high-speed applications.

[0004] Secondly, to address the aforementioned speed issue, solutions have emerged that increase speed by increasing the number of components, such as requiring multiple capacitors to achieve charge transfer and voltage boosting. In integrated circuits, capacitors are among the main components occupying chip area. Using multiple capacitors not only significantly increases chip manufacturing and packaging costs but also negatively impacts the overall performance and stability of the circuit.

[0005] Therefore, existing technologies face an intractable dilemma when designing high-voltage switches for low-voltage power supply control: on the one hand, in order to ensure the boost effect and stability, the circuit structure tends to be complex, resulting in limited switching speed and inability to adapt to high-frequency application scenarios; on the other hand, solutions that attempt to simplify the circuit to improve speed rely on a larger number of components, which brings significant area and cost burdens. Summary of the Invention

[0006] This application provides a low-voltage power supply high-voltage charge pump switching circuit and control method, aiming to solve the technical problem that the traditional charge pump switch has a limited operating frequency due to its complex circuit structure, while the simplified solution relies on more components, thereby increasing the chip area and cost.

[0007] In one aspect, a low-voltage power supply high-voltage charge pump switching circuit is provided, comprising: a switching transistor N3, a charge pump capacitor C, a charging branch, and a switching drive module.

[0008] Switch N3 is an NMOS transistor, with its source coupled to the input signal node INPUT and its drain coupled to the output node OUT.

[0009] The charge pump capacitor C has a first terminal and a second terminal.

[0010] The charging branch is connected between the power supply voltage Vcc and ground GND, and coupled to the first and second terminals of the charge pump capacitor C; it is used to charge the charge pump capacitor C in response to the first control signal S1 and the second control signal S2.

[0011] A switch driving module has a first port coupled to the first end of the charge pump capacitor C, a second port coupled to the second end of the charge pump capacitor C, a third port coupled to the input signal node INPUT, and a drive output port coupled to the gate of the switch transistor N3. In response to the first control signal S1 and the second control signal S2, when the charging branch is turned off, it pulls the second end of the charge pump capacitor C to the voltage of the input signal node INPUT, and uses the voltage stored on the charge pump capacitor C to generate a drive voltage on the gate of the switch transistor N3.

[0012] Wherein, the first control signal S1 and the second control signal S2 are inverted, non-overlapping clock signals, used to enable the charging branch and turn off the switch drive module during the charging phase, and to enable the switch drive module and turn off the charging branch during the driving phase.

[0013] When both the switch driver module and the charging branch are turned off, the switching circuit has no static current sustaining path from the power supply voltage Vcc to ground GND.

[0014] Optionally, in the above scheme, the charging branch includes: a first NMOS transistor N1, a second NMOS transistor N2, a second PMOS transistor P2, and a third PMOS transistor P3.

[0015] The first NMOS transistor N1 has its gate coupled to the second control signal S2, its source coupled to ground GND, and its drain coupled to the second terminal of the charge pump capacitor C.

[0016] The second NMOS transistor N2 has its gate coupled to the second control signal S2, its source coupled to ground GND, and its drain coupled to the second node.

[0017] The second PMOS transistor P2 has its source coupled to the power supply voltage terminal, its gate coupled to the first control signal S1, and its drain coupled to the first node.

[0018] The third PMOS transistor P3 has its source coupled to the power supply voltage terminal, its gate coupled to the second node, and its drain coupled to the first terminal of the charge pump capacitor C.

[0019] Wherein, the low level of the first control signal S1 enables the second PMOS transistor P2, and the high level of the second control signal S2 enables the first NMOS transistor N1 and the second NMOS transistor N2 to charge the charge pump capacitor C.

[0020] In the above scheme, optionally, the switch driving module includes: a fifth NMOS transistor N5, a fourth NMOS transistor N4, a sixth NMOS transistor N6, and a first PMOS transistor P1.

[0021] The fifth NMOS transistor N5 has its gate coupled to the first control signal S1, its source coupled to the second terminal of the charge pump capacitor C, and its drain coupled to the first node.

[0022] The fourth NMOS transistor N4 has its gate coupled to the drain of the first PMOS transistor P1, its source coupled to the second terminal of the charge pump capacitor C, and its drain coupled to the first node.

[0023] The sixth NMOS transistor N6 has its gate coupled to the gate of the fourth NMOS transistor N4, its source coupled to the source of the switching transistor N3, and its drain coupled to the second terminal of the charge pump capacitor C.

[0024] The first PMOS transistor P1 has its source coupled to the first terminal of the charge pump capacitor C, its gate coupled to the first node, and its drain coupled to the gate of the fourth NMOS transistor N4.

[0025] Specifically, the high level of the first control signal S1 enables the fifth NMOS transistor N5, thereby reducing the voltage of the first node and enabling the first PMOS transistor P1, thereby enabling the fourth NMOS transistor N4 and the sixth NMOS transistor N6 to apply a boost voltage to the gate and source terminals of the switching transistor N3.

[0026] In the above scheme, optionally, the first node is a multiplexed node, which is pulled up to the power supply voltage through the second PMOS transistor P2 during the charging phase and pulled down through the fifth NMOS transistor N5 during the driving phase.

[0027] In the above scheme, optionally, the second node is a multiplexed node, which is pulled down by the second NMOS transistor N2 during the charging phase to control the third PMOS transistor P3, and pulled up by the first PMOS transistor P1 during the driving phase to drive the switch N3, the fourth NMOS transistor N4 and the sixth NMOS transistor N6.

[0028] Optionally, in the above scheme, the charge stored in the charge pump capacitor C after the end of the driving phase is used to assist in establishing the charging voltage at the beginning of the next charging phase.

[0029] In the above scheme, optionally, the first control signal S1 and the second control signal S2 are clock signals with frequencies at the megahertz level that alternate and are synchronized with the sampling system clock.

[0030] In the above scheme, optionally, the charge pump capacitor C is an integrated capacitor or a discrete capacitor.

[0031] In a second aspect, a control method for a low-voltage power supply high-voltage charge pump switching circuit is provided, for controlling the circuit as described in any of the preceding claims, including: a charging phase and a driving phase.

[0032] Charging phase: Provide the first control signal S1 and the second control signal S2 as inverted, non-overlapping clock signals, and when the first control signal S1 and the second control signal S2 are in a first level combination, enable the charging branch to charge the charge pump capacitor C to the power supply voltage Vcc, and at the same time turn off the switch drive module.

[0033] Driving phase: When the first control signal S1 and the second control signal S2 switch to the second level combination, the switch driving module is enabled, and one end of the charge pump capacitor C is coupled to the input signal node INPUT to generate a boost driving voltage at the gate of the switch transistor N3 and turn on the switch transistor N3, while turning off the charging branch.

[0034] During the charging and driving / conduction phases, both the charging branch and the switch driving module are in an off state to avoid static current.

[0035] In the above scheme, optionally, the first control signal S1 and the second control signal S2 are inverted clock signals with a frequency of 32MHz.

[0036] Compared with the prior art, this application has at least the following beneficial effects.

[0037] Based on further analysis and research of existing technical problems, this application recognizes a fundamental contradiction between pursuing high speed and saving area in traditional solutions. The root cause lies in the failure to combine the timing control of high-frequency switching with the ultimate reuse of capacitor resources. This application achieves the following effects by using a single charge pump capacitor C and designing an alternating conduction charging branch and switch driver module precisely controlled by a pair of inverted, non-overlapping clock signals (S1, S2): Firstly, it simplifies the circuit structure and control logic, significantly shortening the voltage settling time and enabling stable operation of the switch at megahertz-level high frequencies; secondly, it completely eliminates the need for multi-capacitor schemes, using only one capacitor to complete charge pumping and switch driving, significantly saving chip area and cost; simultaneously, by ensuring that the charging branch and driver module are turned off during non-operational phases, it fundamentally eliminates the static current path and reduces overall power consumption. Attached Figure Description

[0038] Figure 1 This is a circuit block diagram of a low-voltage power supply high-voltage charge pump switch provided in one embodiment of this application.

[0039] Figure 2 A circuit diagram of a low-voltage power supply high-voltage charge pump switch provided in one embodiment of this application.

[0040] Figure 3 This is a schematic diagram of the circuit topology of a low-voltage power supply high-voltage charge pump switch for one embodiment of this application.

[0041] Figure 4 This is a schematic diagram of the circuit topology of a switch drive module for a low-voltage power supply high-voltage charge pump switch, provided as an embodiment of this application.

[0042] Figure 5 A flowchart illustrating a control method for a low-voltage power supply high-voltage charge pump switch, provided as an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] In the description of this application: unless otherwise stated, "a plurality of" means two or more. The terms "first," "second," "third," etc., in this application are intended to distinguish the objects referred to and do not have any special meaning in terms of technical connotation (e.g., they should not be construed as an emphasis on importance or order). Expressions such as "including," "comprising," and "having" also mean "not limited to" (certain units, components, materials, steps, etc.).

[0045] In one embodiment, reference Figure 1 and Figure 2 A low-voltage power supply high-voltage charge pump switching circuit is provided, including: a switching transistor N3, a charge pump capacitor C, a charging branch, and a switch driving module.

[0046] Switch N3 is an NMOS transistor, with its source coupled to the input signal node INPUT and its drain coupled to the output node OUT.

[0047] The charge pump capacitor C has a first terminal and a second terminal.

[0048] The charging branch is connected between the power supply voltage Vcc and ground GND, and coupled to the first and second terminals of the charge pump capacitor C; it is used to charge the charge pump capacitor C in response to the first control signal S1 and the second control signal S2.

[0049] A switch driving module has a first port coupled to the first end of the charge pump capacitor C, a second port coupled to the second end of the charge pump capacitor C, a third port coupled to the input signal node INPUT, and a drive output port coupled to the gate of the switch transistor N3. In response to the first control signal S1 and the second control signal S2, when the charging branch is turned off, it pulls the second end of the charge pump capacitor C to the voltage of the input signal node INPUT, and uses the voltage stored on the charge pump capacitor C to generate a drive voltage on the gate of the switch transistor N3.

[0050] Wherein, the first control signal S1 and the second control signal S2 are inverted, non-overlapping clock signals, used to enable the charging branch and turn off the switch drive module during the charging phase, and to enable the switch drive module and turn off the charging branch during the driving phase.

[0051] When both the switch driver module and the charging branch are turned off, the switching circuit has no static current sustaining path from the power supply voltage Vcc to ground GND.

[0052] This application provides a circuit for a low-voltage power supply high-voltage charge pump switch. This method can solve the problem that existing charge pump switches cannot adapt to high-frequency operation, and reduces the circuit area by using only one capacitor.

[0053] like Figure 2 As shown, this application proposes a circuit for a low-voltage power supply high-voltage charge pump switch, including: a switching transistor N3, a charge pump capacitor C, a charging branch, and a switch driving module.

[0054] The source of the switching transistor N3 is coupled to the input signal node INPUT, and the drain is coupled to the output node OUT.

[0055] The charge pump capacitor C has a first terminal and a second terminal, wherein the voltage at the first terminal is higher than the voltage at the second terminal.

[0056] The charging branch charges the charge pump capacitor C to the power supply voltage Vcc when the second control signal S2 is high and the first control signal S1 is low.

[0057] The switch driving module, when the second control signal S2 is low and the first control signal S1 is high, couples the second terminal of the charge pump capacitor C to the input signal node INPUT, thereby generating a boost voltage equal to the sum of the voltage of the input signal node INPUT and the power supply voltage Vcc at the first terminal of the charge pump capacitor C based on the power supply voltage Vcc stored on the charge pump capacitor C, and applies the boost voltage to the gate of the switch transistor N3 to turn on the switch transistor N3.

[0058] The circuit uses only one charge pump capacitor C, and there is no static current sustaining path during the turn-off phase of the switch N3.

[0059] This circuit can be applied between the analog input of the AFE front end and the sampling system, and is mostly used in capacitor sampling systems. Turning on the switching transistor ensures a sufficiently low impedance, allowing the input signal to quickly charge the sampling capacitor; turning off the switching transistor ensures a sufficiently high impedance, guaranteeing very low leakage current between the input and the sampling capacitor, without affecting application performance.

[0060] In one embodiment, such as Figure 3 As shown, the charging branch includes: a first NMOS transistor N1, a second NMOS transistor N2, a second PMOS transistor P2, and a third PMOS transistor P3.

[0061] The first NMOS transistor N1 has its gate coupled to the second control signal S2, its source coupled to ground GND, and its drain coupled to the second terminal of the charge pump capacitor C.

[0062] The second NMOS transistor N2 has its gate coupled to the second control signal S2, its source coupled to ground GND, and its drain coupled to the second node 2; the second node 2 is a common node that connects the drain of N2, the gate of N4, the drain of P1, and the gate of P3.

[0063] The second PMOS transistor P2 has its source coupled to the power supply voltage terminal, its gate coupled to the first control signal S1, and its drain coupled to the first node 1. Here, the first node 1 is a common node that connects the drain of P2, the drain of N5, the drain of N4, and the gate of P1.

[0064] The third PMOS transistor P3 has its source coupled to the power supply voltage terminal, its gate coupled to the second node 2, and its drain coupled to the first terminal of the charge pump capacitor C.

[0065] Wherein, the low level of the first control signal S1 enables the second PMOS transistor P2, and the high level of the second control signal S2 enables the first NMOS transistor N1 and the second NMOS transistor N2 to charge the charge pump capacitor C.

[0066] In this embodiment, the red-lined device indicates that the device is disconnected. When the capacitor is being charged in the charging branch, the second control signal S2 is set to a high level and the first control signal S1 is set to a low level. The first NMOS transistor N1 and the second NMOS transistor N2 are turned on, the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, the first PMOS transistor P1 is turned off, and the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are turned off. Among them, N1 and N2 are enabled to conduct by the high level of S2, and the drain voltage is close to the source voltage, i.e., GND. At this time, the "-" terminal of the capacitor in the figure is connected to the drain of N1; P2 is enabled by the high level of S2. When P1 is turned on by a low-level signal, the drain voltage approaches the source voltage, pulling the gate voltage of P1 close to Vcc, thus turning P1 off. The gate of P3 is connected to the drain of N2, so P3 approaches GND and turns on. After P3 turns on, the drain voltage approaches the source voltage Vcc. The drain of P3 is connected to the "+" terminal of the capacitor in the diagram, thus creating a voltage difference across the charge pump capacitor C (right side positive, left side negative). This charges the charge pump capacitor C to the power supply voltage Vcc, completing the charging process. In this embodiment, when P3 is on, its drain voltage Vcc is transmitted to the positive terminal of the capacitor through a wire, preventing this node from decreasing due to external interference or circuit fluctuations, ensuring the stability of capacitor charging. Simultaneously, when N2 is on, the gate voltage of P3 is stabilized at GND, further consolidating the on-state of P3 and preventing P3 from turning off due to voltage fluctuations, achieving clean and reliable charging of the charge pump capacitor.

[0067] In the further described circuit, such as Figure 4 As shown, the switch driving module includes: a fifth NMOS transistor N5, a fourth NMOS transistor N4, a sixth NMOS transistor N6, and a first PMOS transistor P1.

[0068] The fifth NMOS transistor N5 has its gate coupled to the first control signal S1, its source coupled to the second terminal of the charge pump capacitor C, and its drain coupled to the first node 1.

[0069] The fourth NMOS transistor N4 has its gate coupled to the drain of the first PMOS transistor P1, its source coupled to the second terminal of the charge pump capacitor C, and its drain coupled to the first node 1.

[0070] The sixth NMOS transistor N6 has its gate coupled to the gate of the fourth NMOS transistor N4, its source coupled to the source of the switching transistor N3, and its drain coupled to the second terminal of the charge pump capacitor C.

[0071] The first PMOS transistor P1 has its source coupled to the first terminal of the charge pump capacitor C, its gate coupled to the first node 1, and its drain coupled to the gate of the fourth NMOS transistor N4.

[0072] Specifically, the high level of the first control signal S1 enables the fifth NMOS transistor N5, thereby reducing the voltage of the first node 1 and enabling the first PMOS transistor P1, thereby enabling the fourth NMOS transistor N4 and the sixth NMOS transistor N6 to apply the boost voltage to the gate and source terminals of the switching transistor N3.

[0073] In this embodiment, the red-lined device indicates that the device is off. When the switch driving module is turned on, the second control signal S2 is set to low level and the first control signal S1 is set to high level. At this time, the first PMOS transistor P1 is turned on, and the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are turned on; the first NMOS transistor N1 and the second NMOS transistor N2 are turned off, and the second PMOS transistor P2 and the third PMOS transistor P3 are turned off. At this time, N1 and N2 are enabled and turned off by the low level of S2, and P2 is enabled and turned off by the high level of S1. When S1 is high level, the gate of N5 is high level and turned on, and the source is connected to the negative terminal of the charge pump capacitor C. After N5 is turned on, it pulls the voltage of the first node 1 to the voltage of the negative terminal of the charge pump capacitor. The source of P1 is connected to the positive terminal of the charge pump capacitor C, and the voltage is input + Vcc. The gate voltage of P1 is much lower than the source voltage, and P1 is turned on. After P1 is turned on, the voltage of its drain is pulled up to be close to the voltage of the positive terminal of the charge pump capacitor C. Therefore, the gate voltage of N4 is input + Vcc. With Vcc at the source and the negative terminal of charge pump capacitor C connected, N4 is turned on. N6: The gate voltage is also input + Vcc, and the source is connected to INPUT, satisfying the turn-on condition, so N6 is turned on. The gate of N3 is connected to N4, and the gate voltage is input + Vcc, so N3 is turned on. After N6 is turned on, its source INPUT and the negative terminal of the drain capacitor are short-circuited. Therefore, the voltage at the negative terminal of charge pump capacitor C is clamped to the INPUT voltage.

[0074] During the previous charging phase, S2 was high and S1 was low, and the charge pump capacitor C had already been charged, with a voltage difference of Vcc across its terminals. In the current phase, with S2 low and S1 high, the switch driver module connects the negative terminal of the capacitor from its original 0VGND to the INPUT node via N6. Since the voltage difference across the charge pump capacitor C cannot change abruptly, the positive terminal voltage of the charge pump capacitor C needs to be boosted to maintain the original Vcc voltage difference. Therefore, the positive terminal voltage of the charge pump capacitor C equals input + Vcc. At this time, the gate voltage of N3 is: input + capacitor voltage = input voltage + power supply voltage.

[0075] However, in actual integrated circuit implementations, due to the inherent on-resistance of P3 and N1, the charging current will generate a small voltage drop across these resistors. Therefore, the voltage that the charge pump capacitor C eventually charges to will be slightly lower than Vcc. This small voltage drop can conceptually be equivalent to a "diode voltage drop," but the scope of this invention should not be limited by this specific physical phenomenon. Any method that enables the capacitor voltage to reach or approach Vcc through the charging branch falls within the scope of this invention.

[0076] In one embodiment, the first node is a multiplexed node, which is pulled up to the power supply voltage through the second PMOS transistor P2 during the charging phase and pulled down through the fifth NMOS transistor N5 during the driving phase.

[0077] In one embodiment, the second node is a multiplexed node, which is pulled down by the second NMOS transistor N2 during the charging phase to control the third PMOS transistor P3, and pulled up by the first PMOS transistor P1 during the driving phase to drive the switching transistor N3, the fourth NMOS transistor N4 and the sixth NMOS transistor N6.

[0078] In one embodiment, the charge stored in the charge pump capacitor C after the end of the driving phase is used to assist in establishing the charging voltage at the start of the next charging phase.

[0079] In the further described circuit, during the turn-off phase of the switch N3, the charge in the charge pump capacitor C is not discharged, allowing for rapid establishment of a boost voltage in the next conduction cycle. When the circuit returns to the charging phase, the drive module is disconnected, and the charge in capacitor C is retained, quickly preparing for the next cycle.

[0080] In one embodiment, the first control signal S1 and the second control signal S2 are clock signals with frequencies in the megahertz range that alternate and are synchronized with the sampling system clock.

[0081] Furthermore, in the circuit described above, the first control signal S1 and the second control signal S2 are inverses of each other and alternately switch at a frequency of 32MHz, and are synchronized with the sampling system clock.

[0082] In one embodiment, the charge pump capacitor C is an integrated capacitor or a discrete capacitor.

[0083] In one embodiment, a control method for a low-voltage power supply high-voltage charge pump switching circuit is provided for controlling the circuit as described in any of the preceding embodiments, including: a charging phase and a driving phase.

[0084] Charging phase: Provide the first control signal S1 and the second control signal S2 as inverted, non-overlapping clock signals, and when the first control signal S1 and the second control signal S2 are in a first level combination, enable the charging branch to charge the charge pump capacitor C to the power supply voltage Vcc, and at the same time turn off the switch drive module.

[0085] Driving phase: When the first control signal S1 and the second control signal S2 switch to the second level combination, the switch driving module is enabled, and one end of the charge pump capacitor C is coupled to the input signal node INPUT to generate a boost driving voltage at the gate of the switch transistor N3 and turn on the switch transistor N3, while turning off the charging branch.

[0086] During the charging and driving / conduction phases, both the charging branch and the switch driving module are in an off state to avoid static current.

[0087] In this embodiment, combined with Figure 5 The control method is further described as including steps S101-S104.

[0088] S101, when the second control signal S2 is high and the first control signal S1 is low, the only charge pump capacitor C is charged through the charging branch so that the voltage across its terminals reaches the power supply voltage Vcc.

[0089] S102, when the second control signal S2 is low and the first control signal S1 is high, the second terminal of the charge pump capacitor C is coupled to the input signal node INPUT through the switch driving module.

[0090] S103, based on the power supply voltage Vcc stored on the charge pump capacitor C, a boost voltage equal to the sum of the voltage of the input signal node INPUT and the power supply voltage Vcc is generated at the first terminal of the charge pump capacitor C.

[0091] S104, the boost voltage is then applied to the gate of the switch N3 to turn on the switch N3, so that a low-impedance path is formed between the input signal node INPUT and the output node OUT.

[0092] During the turn-off phase of the switch N3, all static current sustaining paths are disconnected, so that the circuit only has dynamic power consumption.

[0093] In a further embodiment of the method, the first control signal S1 and the second control signal S2 alternate at a frequency of 32MHz and are synchronized with the sampling system clock.

[0094] This application provides a circuit and control method for a low-voltage power supply high-voltage charge pump switch. The circuit includes: a switching transistor connected between an input signal node and an output node; a charge pump capacitor having a first terminal and a second terminal; a charging branch that charges the charge pump capacitor to the power supply voltage when a second control signal is high and a first control signal is low; and a switch driving module that generates a boost voltage at the first terminal of the charge pump capacitor and turns on the switching transistor when the second control signal is low and the first control signal is high. The circuit uses only one charge pump capacitor, and there is no quiescent current sustaining path during the switch transistor's turn-off phase. This invention requires only a small capacitor to achieve fast and stable operation of the charge pump switch at high frequencies. The core advantages of this solution are: the capacitor charge pump structure enables rapid voltage establishment, making it suitable for high-speed switching applications; it replaces the traditional dual-capacitor or multi-capacitor design with only one capacitor, significantly saving chip area; and it completely eliminates quiescent current during the turn-off phase, effectively reducing power consumption in standby mode.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A low-voltage power supply high-voltage charge pump switching circuit, characterized in that, include: Switch N3 is an NMOS transistor, with its source coupled to the input signal node INPUT and its drain coupled to the output node OUT. The charge pump capacitor C has a first terminal and a second terminal; The charging branch is connected between the power supply voltage Vcc and ground GND, and couples the first and second terminals of the charge pump capacitor C. Used to charge the charge pump capacitor C in response to the first control signal S1 and the second control signal S2; A switch driving module has a first port coupled to the first end of the charge pump capacitor C, a second port coupled to the second end of the charge pump capacitor C, a third port coupled to the input signal node INPUT, and a drive output port coupled to the gate of the switch transistor N3. It is used to pull the second end of the charge pump capacitor C to the voltage of the input signal node INPUT when the charging branch is turned off in response to the first control signal S1 and the second control signal S2, and to generate a drive voltage on the gate of the switch transistor N3 using the voltage stored on the charge pump capacitor C. Wherein, the first control signal S1 and the second control signal S2 are inverted non-overlapping clock signals, used to enable the charging branch and turn off the switch driving module during the charging phase, and to enable the switch driving module and turn off the charging branch during the driving phase. When both the switch drive module and the charging branch are turned off, there is no static current sustaining path from the power supply voltage Vcc to ground GND in the switching circuit. The charging branch includes: The first NMOS transistor N1 has its gate coupled to the second control signal S2, its source coupled to ground GND, and its drain coupled to the second terminal of the charge pump capacitor C. The second NMOS transistor N2 has its gate coupled to the second control signal S2, its source coupled to ground GND, and its drain coupled to the second node; The second PMOS transistor P2 has its source coupled to the power supply voltage terminal, its gate coupled to the first control signal S1, and its drain coupled to the first node. The third PMOS transistor P3 has its source coupled to the power supply voltage terminal, its gate coupled to the second node, and its drain coupled to the first terminal of the charge pump capacitor C. Wherein, the low level of the first control signal S1 enables the second PMOS transistor P2, and the high level of the second control signal S2 enables the first NMOS transistor N1 and the second NMOS transistor N2 to charge the charge pump capacitor C. The switch driving module includes: The fifth NMOS transistor N5 has its gate coupled to the first control signal S1, its source coupled to the second terminal of the charge pump capacitor C, and its drain coupled to the first node; The fourth NMOS transistor N4 has its gate coupled to the drain of the first PMOS transistor P1, its source coupled to the second terminal of the charge pump capacitor C, and its drain coupled to the first node; The sixth NMOS transistor N6 has its gate coupled to the gate of the fourth NMOS transistor N4, its source coupled to the source of the switching transistor N3, and its drain coupled to the second terminal of the charge pump capacitor C. The first PMOS transistor P1 has its source coupled to the first terminal of the charge pump capacitor C, its gate coupled to the first node, and its drain coupled to the gate of the fourth NMOS transistor N4. Specifically, the high level of the first control signal S1 enables the fifth NMOS transistor N5, thereby reducing the voltage of the first node and enabling the first PMOS transistor P1, thereby enabling the fourth NMOS transistor N4 and the sixth NMOS transistor N6 to apply a boost voltage to the gate and source terminals of the switching transistor N3.

2. The circuit according to claim 1, characterized in that, The first node is a multiplexed node. During the charging phase, it is pulled up to the power supply voltage through the second PMOS transistor P2, and during the driving phase, it is pulled down through the fifth NMOS transistor N5.

3. The circuit according to claim 1, characterized in that, The second node is a multiplexed node. During the charging phase, it is pulled down by the second NMOS transistor N2 to control the third PMOS transistor P3. During the driving phase, it is pulled up by the first PMOS transistor P1 to drive the switching transistor N3, the fourth NMOS transistor N4, and the sixth NMOS transistor N6.

4. The circuit according to claim 1, characterized in that, The charge stored in the charge pump capacitor C after the end of the driving phase is used to help establish the charging voltage at the beginning of the next charging phase.

5. The circuit according to any one of claims 1 to 2, characterized in that, The first control signal S1 and the second control signal S2 are clock signals with frequencies in the megahertz range that alternate and are synchronized with the sampling system clock.

6. The circuit according to any one of claims 1 to 2, characterized in that, The charge pump capacitor C is an integrated capacitor or a discrete capacitor.

7. A control method for a low-voltage power supply high-voltage charge pump switching circuit, used to control the circuit as described in any one of claims 1 to 6, characterized in that, include: Charging phase: Provide the first control signal S1 and the second control signal S2 as inverted non-overlapping clock signals, and when the first control signal S1 and the second control signal S2 are in the first level combination, enable the charging branch to charge the charge pump capacitor C to the power supply voltage Vcc, and at the same time turn off the switch drive module. Driving phase: When the first control signal S1 and the second control signal S2 switch to the second level combination, the switch driving module is enabled, and one end of the charge pump capacitor C is coupled to the input signal node INPUT to generate a boost driving voltage at the gate of the switch transistor N3 and turn on the switch transistor N3, while turning off the charging branch. Outside of the charging and driving phases, both the charging branch and the switch driving module are in an off state to avoid static current.

8. The method according to claim 7, characterized in that, The first control signal S1 and the second control signal S2 are inverted clock signals with a frequency of 32MHz.

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