Crystal oscillator circuit and quick starting method thereof, electronic equipment and storage medium

Abstract

The invention provides a crystal oscillator circuit and a quick starting method thereof. The crystal oscillator circuit comprises a crystal oscillator core circuit, an RC oscillation circuit and a logic control circuit, the crystal oscillator core circuit comprises a driving module and an auxiliary control module; the RC oscillating circuit is used for generating a first clock signal; the driving module is used for driving the crystal oscillator to work and generating a second clock signal. According to the working principle, after the circuit is enabled, the logic control circuit drives the auxiliary control module to be in short circuit with input and output of the crystal oscillator, so that a compensation capacitor of the crystal oscillator is rapidly charged; disconnecting the compensation capacitor from the input end of the driving module, controlling the RC oscillating circuit to output a first clock signal, and inputting the first clock signal into the input end of the driving module; and after a certain time is delayed, the input of the first clock signal to the driving module is stopped, the compensation capacitor is reconnected with the input end of the driving module, and a second clock signal is output. By utilizing the scheme of the invention, the crystal oscillator can be quickly started efficiently.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a crystal oscillator circuit and its fast start-up method, electronic devices, and storage media. Background Technology

[0002] A crystal oscillator is an electronic component that utilizes the piezoelectric effect of quartz crystals to provide frequency stabilization and selection. Its primary function in electronic devices is to provide a stable clock signal, forming the cornerstone of the normal operation of many electronic devices. Crystal oscillators have a high quality factor, providing low phase noise and high frequency accuracy clock signals, and are widely used in the communications field. Currently, various applications increasingly demand low power consumption, requiring chips to frequently switch between sleep and operating states. Traditional crystal oscillator circuits have long start-up times, typically in the millisecond range. Excessive start-up time increases system power consumption and reduces product competitiveness. Summary of the Invention

[0003] This application provides a crystal oscillator circuit and its fast startup method, electronic device and storage medium to solve the problem of long startup time of traditional crystal oscillators.

[0004] On one hand, embodiments of this application provide a crystal oscillator circuit, the circuit including: a crystal core circuit, an RC oscillation circuit, and a logic control circuit; the logic control circuit is coupled to the crystal core circuit and the RC oscillation circuit respectively; the crystal core circuit includes a driving module and an auxiliary control module;

[0005] The RC oscillation circuit is used to generate a first clock signal with a frequency close to that of the crystal oscillator;

[0006] The driving module is used to drive the crystal oscillator to work and generate a second clock signal;

[0007] The logic control circuit is used to control the operation of the RC oscillation circuit and to drive the drive module through the auxiliary control module.

[0008] When the circuit is enabled, the auxiliary control module drives the drive module to start working. The logic control circuit drives the auxiliary control module to short-circuit the input and output of the crystal oscillator to quickly charge the compensation capacitor of the crystal oscillator. At the same time, it controls the RC oscillation circuit to output the first clock signal. After the compensation capacitor is fully charged, the connection between the compensation capacitor and the input terminal of the drive module is disconnected, and the first clock signal is output as the system clock signal and input to the input terminal of the drive module. After a certain delay, the input of the first clock signal to the drive module is stopped, and the compensation capacitor is reconnected to the input terminal of the drive module, so that the drive module drives the crystal oscillator to output the second clock signal. After the second clock signal stabilizes, the system clock signal is switched from the first clock signal to the second clock signal.

[0009] Optionally, the driving module includes: an inverting amplifier, and a feedback resistor connected between the input and output terminals of the inverting amplifier;

[0010] The auxiliary control module includes: a control switch; the control switch includes: a first switch, a second switch, and a third switch;

[0011] The first terminal of the first switch is connected to the input terminal of the crystal oscillator, and the second terminal of the first switch is connected to the input terminal of the inverting amplifier;

[0012] The first end of the second switch is connected to the signal excitation port of the logic control circuit, and the second end of the second switch is connected to the input terminal of the inverting amplifier;

[0013] The first end of the third switch is connected to the input end of the inverting amplifier, and the second end of the third switch is connected to the output end of the inverting amplifier.

[0014] The control terminals of the first switch, the second switch, and the third switch are respectively controlled by the logic control signal output by the logic control circuit.

[0015] Optionally, the auxiliary control module further includes:

[0016] The power gate switch, controlled by the output of the logic control circuit, is used to control the drive module to turn on or off the working power.

[0017] Optionally, the logic control circuit includes: a register module, a state machine, and a counter module;

[0018] The counter module is used to count pulses of the first clock signal and the second clock signal;

[0019] The state machine is used to switch states based on the count value of the counter module and the set and written values ​​in the register module; and to select to output the first clock signal or the second clock signal based on the current state.

[0020] Optionally, the counter module includes: a first counter, a second counter, and a third counter;

[0021] The first counter and the second counter are used to count pulses of the first clock signal;

[0022] The third counter is used to count pulses of the second clock signal.

[0023] Optionally, the state includes:

[0024] ST1, off state;

[0025] ST2, DC operating point established state;

[0026] ST3, similar frequency injection traction state;

[0027] ST4, the crystal oscillator frequency is gradually stabilizing;

[0028] ST5, normal operating state;

[0029] The register module includes: three read-only registers and four read-write registers;

[0030] The three read-only registers include a first read-only register, a second read-only register, and a third read-only register;

[0031] The first read-only register is used to store the set duration of the ST2 state, the second read-only register is used to store the set duration of the ST3 state, and the third read-only register is used to store the set duration of the first clock signal;

[0032] The four readable and writable registers are used to store the pulse values ​​of the second clock signal recorded by the third counter.

[0033] Optionally, the state machine includes:

[0034] Clock output port, used to output clock signal;

[0035] A clock indicator port is used to indicate whether the clock signal output by the clock output port is the first clock signal from the RC oscillation circuit or the second clock signal from the crystal oscillator.

[0036] Optionally, the circuit further includes: an electrostatic discharge (ESD) protection circuit for providing ESD protection; the ESD protection circuit includes: a first branch connected to the input terminal of the crystal oscillator and a second branch connected to the output terminal of the crystal oscillator;

[0037] The first branch includes a first diode and a second diode. The anode of the first diode is grounded, and the cathode of the first diode and the anode of the second diode are connected to the input terminal of the crystal oscillator. The cathode of the second diode is connected to the power supply.

[0038] The second branch includes a third diode and a fourth diode. The anode of the third diode is grounded, and the cathode of the third diode and the anode of the fourth diode are connected to the output terminal of the crystal oscillator. The cathode of the fourth diode is connected to the power supply.

[0039] On the other hand, embodiments of this application also provide a fast startup method for a crystal oscillator circuit, the method comprising:

[0040] After power-on, the current circuit is enabled, and the crystal oscillator's drive module starts working, shorting the input and output terminals of the crystal oscillator to quickly charge the crystal oscillator's compensation capacitor, while controlling the RC oscillation circuit to output the first clock signal.

[0041] After the compensation capacitor has finished charging, disconnect the compensation capacitor from the input terminal of the drive module.

[0042] The first clock signal is output as the system clock signal, and the first clock signal is input to the input terminal of the drive module.

[0043] After a certain delay, the input of the first clock signal to the driving module is stopped, and the compensation capacitor is reconnected to the input terminal of the driving module, so that the driving module drives the crystal oscillator to output the second clock signal.

[0044] After the second clock signal stabilizes, the system clock signal is switched from the first clock signal to the second clock signal.

[0045] Optionally, the method further includes:

[0046] The connection control between the crystal oscillator and the drive module is realized by using a state machine and logic operations, and the control of the RC oscillation circuit and the drive module is also realized.

[0047] Using the first clock signal, the state machine and the logic operation realize stable detection of the second clock signal.

[0048] Optionally, the method further includes: using a state machine and logic operations to control the connection between the crystal oscillator and the driving module, and to control the RC oscillation circuit and the driving module; using the first clock signal, the state machine and the logic operations to detect the stability of the second clock signal.

[0049] On the other hand, embodiments of this application also provide an electronic device, including the aforementioned crystal oscillator circuit.

[0050] On the other hand, embodiments of this application also provide a computer-readable and writable storage medium storing a computer program thereon, wherein the computer program is executed by a computer to perform the steps of the fast startup method of the crystal oscillator circuit.

[0051] The crystal oscillator circuit and its fast startup method provided in this application embodiment, when the circuit is enabled, the auxiliary control module drives the drive module to start working, and the logic control circuit drives the auxiliary control module to short-circuit the input and output of the crystal oscillator, thereby quickly charging the input compensation capacitor and output compensation capacitor of the crystal oscillator, reducing the initial charging time of the compensation capacitor, and simultaneously controlling the RC oscillation circuit to generate a first clock signal close to the crystal oscillator frequency; after the compensation capacitor is fully charged, the connection between the input compensation capacitor of the compensation crystal oscillator and the input terminal of the drive module is disconnected, and the first clock signal is output as the system clock signal and input to the input terminal of the drive module, accelerating the crystal oscillator startup through frequency traction. After a period of frequency traction, the oscillation waveforms on the input and output compensation capacitors of the crystal oscillator gradually stabilize, the input of the first clock signal to the drive module stops, and the input terminal of the drive module is reconnected to the input compensation capacitor of the crystal oscillator. At this time, the crystal oscillator loop is established, and the frequency is gradually fine-tuned to the actual frequency of the crystal oscillator. The solution of this application effectively reduces the initial charging time of the compensation capacitor of the crystal oscillator through the initial capacitor charging structure, and accelerates the crystal oscillator startup time through the near-frequency injection traction method, which can shorten the crystal oscillator startup time from a few milliseconds to about a few hundred microseconds. Furthermore, in this application, the stability of the crystal oscillator clock is tested to ensure that the output is only performed after the crystal oscillator clock has stabilized. Moreover, the RC clock signal is output within tens of microseconds after the circuit is enabled, and the output clock switches to the crystal oscillator clock after the crystal oscillator clock stabilizes. This overcomes the shortcoming of traditional systems that cannot provide a clock before the crystal oscillator is stable, and can speed up the initialization process of the subsequent system. Attached Figure Description

[0052] The accompanying drawings are provided to offer a clearer understanding of this application and form part of the specification. They, together with the embodiments of this application, serve to explain the application and do not constitute a limitation thereof. In the drawings:

[0053] Figure 1 This is a schematic block diagram of the crystal oscillator circuit provided in the embodiments of this application;

[0054] Figure 2 This is a schematic diagram of a specific structure of the crystal oscillator circuit provided in an embodiment of this application;

[0055] Figure 3 This is a schematic diagram of the logic control circuit in one embodiment of this application;

[0056] Figure 4 This is a schematic diagram of the state transition of the state machine in an embodiment of this application;

[0057] Figure 5 This is a waveform diagram of the crystal oscillator circuit provided in the embodiments of this application;

[0058] Figure 6 This is a flowchart illustrating the state transition process implemented using state machine logic control in the crystal oscillator circuit provided in this application embodiment;

[0059] Figure 7 This is another schematic diagram of the crystal oscillator circuit provided in the embodiments of this application;

[0060] Figure 8 This is a flowchart of a fast startup method for a crystal oscillator circuit provided in an embodiment of this application. Detailed Implementation

[0061] To make the above-mentioned objectives, features and beneficial effects of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0062] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0063] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0064] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0065] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0066] Passive crystal oscillators require an external oscillation circuit to generate an oscillation signal. Traditional crystal oscillation circuits typically connect the crystal to the two ends of an inverting amplifier, with a capacitor connected to each end of the crystal, and the other end of each capacitor grounded. Traditional crystal oscillation circuits have a long start-up time, mainly due to two reasons: First, the charging current of the compensation capacitor for the quartz crystal in traditional crystal oscillation circuits needs to pass through a feedback resistor. When the feedback resistor is large, the time required to charge the capacitor to a specific common-mode level (e.g., VCC / 2, where VCC is the circuit operating voltage) is long. While a smaller feedback resistor shortens the capacitor charging time, it increases the power consumption during operation and makes starting the crystal oscillation more difficult. Second, traditional crystal oscillators rely on noise for startup; that is, at the moment of power-on, thermal noise and transient noise exist in the circuit, providing initial energy excitation for the crystal oscillator. These noises include transient pulse noise when the crystal oscillator module is enabled and thermal noise from various components in the circuit. These noises contain multiple frequency components. The transient pulse noise during enable is relatively large but only lasts for a moment. Although the subsequent thermal noise continues to exist, its amplitude is very small, resulting in a long time required to gradually increase the amplitude of the oscillator signal to a steady state through noise-driven oscillation.

[0067] To address this, this application provides a crystal oscillator circuit and its fast startup method, achieving rapid crystal oscillation startup through initial capacitor charging and frequency injection traction. Specifically, after the circuit is enabled, the input and output of the crystal oscillator are shorted to quickly charge the compensation capacitor, thereby reducing the initial charging time of the capacitor. Then, the input terminal of the drive module is disconnected from the compensation capacitor, and a first clock signal close to the crystal oscillator frequency is generated by an RC oscillation circuit. This first clock signal is input to the input terminal of the drive module, accelerating the crystal oscillator startup through frequency traction. After a period of frequency traction, the oscillation waveform on the compensation capacitor gradually stabilizes, the input of the first clock signal to the drive module is stopped, and the input terminal of the drive module is reconnected to the compensation capacitor. At this point, the crystal oscillator loop is established, and the frequency is gradually fine-tuned to the actual crystal oscillator frequency.

[0068] like Figure 1 The diagram shown is a schematic block diagram of the crystal oscillator circuit provided in an embodiment of this application.

[0069] The crystal oscillator circuit 100 includes a crystal core circuit 101, an RC oscillation circuit 102, and a logic control circuit 103. The input enable pin EN is the system enable pin. The logic control circuit 103 is coupled to both the crystal core circuit 101 and the RC oscillation circuit 102. The crystal core circuit 101 includes a drive module 111 and an auxiliary control module 112.

[0070] Crystal oscillator 10 includes input terminal XI and output terminal XO;

[0071] The RC oscillation circuit 102 is used to generate a first clock signal CLK1 with a frequency close to that of the crystal oscillator 10, and its enable terminal RCEN is connected to the logic control circuit 103.

[0072] The driving module 111 is used to drive the crystal oscillator 10 to work. Based on the logic control signal output by the logic control circuit 103 and the signal at the input terminal XI, it generates a second clock signal CLK2 and outputs it to the output terminal XO of the crystal oscillator 10 and the logic control circuit 103. The logic control signal may include: excitation signal CKO1, power gating signal MP2GC, and switch control signals K1EN, K2EN, and K3EN, which will be described in detail later.

[0073] In this embodiment of the invention, when the frequency of the crystal oscillator 10 is not yet stable, the system clock uses the clock provided by the RC oscillation circuit 102, that is, outputting the first clock signal CLK1. The logic control circuit 103 and the crystal core circuit 101 can use the first clock signal CLK1 to complete initialization and other operations, effectively improving the crystal oscillator startup efficiency. When the frequency of the crystal oscillator 10 is stable, the system clock switches from the clock provided by the RC oscillation circuit 102 to the clock provided by the crystal oscillator, that is, outputting the second clock signal CLK2. Furthermore, after outputting the second clock signal CLK2, the RC oscillation circuit 102 can also be turned off simultaneously through the RCEN control signal to reduce system power consumption.

[0074] like Figure 2 The diagram shown is a specific structural schematic of a crystal oscillator circuit provided in an embodiment of this application.

[0075] Figure 2 In the illustrated embodiment, the crystal oscillator 10 includes a quartz crystal XT1. The grounding capacitors C1 and C2 connected to the two ends of the quartz crystal XT1 are compensation capacitors for the quartz crystal. The values ​​of C1 and C2 are generally configured according to the capacitance values ​​provided by the quartz crystal manufacturer that match the quartz crystal. XI and XO are the input and output terminals of the crystal oscillator 10, respectively.

[0076] Simultaneously refer to Figure 1 and Figure 2 The drive module 111 includes: an inverting amplifier, and a feedback resistor R connected between the input and output terminals of the inverting amplifier. FA non-limiting embodiment of the inverting amplifier may consist of MOS transistors, including a first PMOS transistor MP1 and a first NMOS transistor MN1. The source of MP1 is typically connected to the power supply VCC, and in some embodiments may also be connected to the drain of a switch MP2, which serves as a gated power supply. The source of MN1 is grounded. The gates of MP1 and MN1 are connected as the input terminal of the inverting amplifier, designated XII for ease of description. This input terminal XII is also the input terminal of the drive module 111. The drains of MP1 and MN1 are connected as the output terminal of the inverting amplifier, connected to the output terminal XO of the crystal oscillator 10. This output terminal is also the output terminal of the drive module 111 and is connected to the input terminal of the logic control circuit 103, outputting a second clock signal CLK2 to the logic control circuit 103.

[0077] The auxiliary control module 112 includes three control switches: a first switch K1, a second switch K2, and a third switch K3.

[0078] The three control switches described above each include a first terminal, a second terminal, and a control terminal. The first and second terminals are the signal ports of the control switches, and the control terminal is the enable control port. When the control terminal is high, the control switch is closed; when the control terminal is low, the control switch is open. The specific connection relationship is as follows:

[0079] The first terminal of the first switch K1 is connected to the input terminal XI of the crystal oscillator 10, and the second terminal of the first switch K1 is connected to the input terminal XII of the inverting amplifier.

[0080] The first end of the second switch K2 is connected to the signal excitation port CKO1 of the logic control circuit 103. This signal excitation port is used to output the excitation signal CKO1. The second end of the second switch K2 is connected to the input terminal XII of the inverting amplifier.

[0081] The first end of the third switch K3 is connected to the input terminal XII of the inverting amplifier, and the second end of the third switch K3 is connected to the output terminal of the inverting amplifier, namely the output terminal XO of the crystal oscillator 10.

[0082] It should be noted that, in this embodiment of the invention, the first switch K1, the second switch K2, and the third switch K3 are respectively controlled by the switch control signals K1EN, K2EN, and K3EN output from the control ports K1EN, K2EN, and K3EN of the logic control circuit 103.

[0083] In some embodiments, the auxiliary control module 112 may further include: a power gating switch, controlled by the power gating signal MP2GC output by the logic control circuit 103, used to control the drive module 111 to turn on or off the operating power supply VCC. Figure 2As shown, in one non-limiting embodiment, the power gate switch can be implemented using a second PMOS transistor MP2. Of course, it can also be implemented using switching devices such as NMOS transistors. The specific position of the power gate switch needs to be adjusted accordingly based on different switching devices, but this embodiment of the invention does not limit this.

[0084] In this embodiment of the invention, the output frequency of the RC oscillation circuit 102 is designed to be close to the frequency of the crystal oscillator 10. The accuracy requirement is not high, and no calibration is required. For example, the frequency deviation between the RC oscillator and the crystal oscillator is less than ±20%, which can be achieved at low cost.

[0085] The RC oscillation circuit 102 includes an input port RCEI and an output port CLKO. The input port RCEI is an enable signal input port, used to receive the enable signal RCEN output by the logic control circuit 103; CLKO is a clock signal output port, used to output the first clock signal CLK1.

[0086] When RCEN=0, CLKO outputs a low level, i.e., CLK1=0; when RCEN=1, CLKO outputs the first clock signal CLK1, which is close to the crystal oscillator frequency.

[0087] When MP2GC=0, MP2 is off, and the VPX node output voltage is zero. When MP2GC=1, MP2 is on, and the VPX node output voltage is the power supply VCC.

[0088] When K1EN=1, switch K1 is on, and XI and XII are connected; when K1EN=0, switch K1 is off, and XI and XII are disconnected.

[0089] When K2EN=1, switch K2 is on, and CKO1 is connected to XII; when K2EN=0, switch K2 is off, and CKO1 is disconnected from XII.

[0090] When K3EN=1, switch K3 is on, and XI is connected to XO; when K3EN=0, switch K3 is off, and XI is disconnected from XO.

[0091] It should be noted that, for ease of description and consistency, in the following description, some ports and their input or output signals will be represented by the same symbol, such as port A1 output signal A1, port A2 output signal A2, etc. Registers and their values ​​will be represented by the same symbol, such as the value of register REG1 REG1, etc. The contextual description will not cause confusion or ambiguity.

[0092] like Figure 3 The diagram shown is a structural schematic of the logic control circuit 103 in an embodiment of this application.

[0093] The logic control circuit 103 includes: a register module 131, a state machine 132, and a counter module 133. See also the following... Figure 2 Explain the specific structure of each module.

[0094] Figure 3 In the illustrated embodiment, register module 131 includes three read-only registers: REG1, REG2 and REG3, and four read-write registers REGX<3:0>.

[0095] In addition to the aforementioned register input / output interfaces, register module 131 also includes five input ports, namely:

[0096] CKIN1 is its clock input port;

[0097] LEN is its enable input port;

[0098] LRST is its reset input port;

[0099] W<3:0> is the write enable port, corresponding to the write control of the read / write register REGX<3:0>;

[0100] R<6:0> is the read enable port, corresponding to the read / write register REGX<3:0> and the read-only registers REG1, REG2, and REG3 for read control. The specific order is as follows: R <0> Corresponding REGX <0> R <1> Corresponding REGX <1> R <2> Corresponding REGX <2> R <3> Corresponding REGX <3> R <4> Corresponding to REG1, R <5> Corresponding to REG2, R <6> Corresponding to REG3.

[0101] It should be noted that registers cannot be read or written when LRST=1, but can be read and written when LRST=0 and LEN=1.

[0102] Figure 3 In the illustrated embodiment, in addition to the input / output interfaces connected to the register module 131, the state machine 132 also includes six input ports: CKIN1, CKIN2, EN, NUM1, NUM2, and NUM3. Wherein:

[0103] EN is the system enable input port, used to input the system enable signal. When EN=0, the system remains in the off state, and when EN=1, the system starts working.

[0104] The input port CKIN1 is connected to the output port CLKO of the RC oscillation circuit 102 to receive the first clock signal CLK1 output by the RC oscillation circuit 102; CKIN2 is connected to the output terminal XO of the drive module 111 to receive the second clock signal CLK2 output by the drive module 111.

[0105] NUM1 is the count value output of the first counter A in counter module 133, NUM2 is the count value output of the second counter B in counter module 133, and NUM3 is the count value output of the third counter C in counter module 133.

[0106] In addition to the input / output interfaces with register module 131 and counter module 133, state machine 132 includes 12 output ports, specifically: an enable signal output port RCEO; three state transition indicator ports: T1, T2, and T3, outputting state machine indicator signals T1, T2, and T3 respectively; three control switch control ports: K1EN, K2EN, and K3EN, outputting switch control signals K1EN, K2EN, and K3EN respectively; a power gating switch control port MP2GC, outputting the power gating signal MP2GC; two clock indicator ports: CK1OK and CK2OK, outputting clock indicator signals CK1OK and CK2OK respectively; a clock output port CLKOUT, outputting the system clock CLKOUT; and a signal excitation port CKO1, outputting the excitation signal CKO1. A detailed description of the connections and output signals of each output port is as follows:

[0107] The enable signal output port RCEO is connected to the input port RCEI of the RC oscillation circuit 102 and is used to output the enable signal RCEN to the RC oscillation circuit 102.

[0108] Clock indicator signals T1, T2, and T3 are used to indicate the state of state machine 132.

[0109] Control port K1EN is connected to the third terminal of the first switch K1, which is the enable control terminal, used to output the switch control signal K1EN to control the first switch to close or open; control port K2EN is connected to the third terminal of the second switch K2, which is the enable control terminal, used to output the switch control signal K2EN to control the second switch to close or open; control port K3EN is connected to the third terminal of the third switch K3, which is the enable control terminal, used to output the switch control signal K3EN to control the third switch to close or open. These three switches are closed when the switch control signal is high and open when the signal is low.

[0110] The control port MP2GC is connected to the gate of the second PMOS transistor MP2 and is used to output the power gating signal MP2GC to control MP2 to turn on or off.

[0111] The clock indicator ports CK1OK and CK2OK are used to output clock indicator signals CK1OK and CK2OK to indicate whether the system clock signal CLKOUT comes from the first clock signal CLK1 of the RC oscillator circuit 102 or the second clock signal CLK2 of the crystal oscillator. When CK1OK=1 and CK2OK=0, it indicates that the system clock signal CLKOUT comes from the first clock signal CLK1 of the RC oscillator circuit 102. When CK1OK=0 and CK2OK=1, it indicates that the system clock signal CLKOUT comes from the second clock signal CLK2 of the crystal oscillator. When CK1OK=0 and CK2OK=0, it indicates that the system clock signal CLKOUT has no clock output.

[0112] Figure 3 In the illustrated embodiment, the counter module 133 includes three counters: a first counter A, a second counter B, and a third counter C. Wherein:

[0113] The first counter A, the second counter B, and the third counter C each contain three input ports: CK, CEN, and ZERO, and one output port NUM. Wherein:

[0114] CK is the clock input port of the counter, which receives the clock signal used for counting; among them, the counting clock of the first counter A and the second counter B is CKIN1, and the counting clock of the third counter C is CKIN2.

[0115] CEN is the enable input port for the counter.

[0116] ZERO is the reset input port for the counter.

[0117] NUM is the output port for the counter's count value.

[0118] When ZERO=0 and CEN=0, the counter stops counting;

[0119] When ZERO=0 and CEN=1, the counter counts on each rising edge of CK, and the corresponding count value NUM is incremented by 1.

[0120] When ZERO=1, the value of NUM is cleared to zero.

[0121] In this embodiment of the invention, the state machine 132 reads the values ​​of read-only registers REG1, REG2 and REG3 in the register module 131 through the corresponding data read ports, and reads and writes the values ​​of read-write registers REGX<3:0> in the register module 131 through the data read-write ports.

[0122] In this embodiment of the invention, the state machine 132 performs read and write operations on the read and write register REGX<3:0> based on the count values ​​NUM1, NUM2, and NUM3 output by the three counters, and switches the state according to the historical signal sequence.

[0123] The following reference Figure 4 The switching process between different states of state machine 132 in this embodiment of the invention is described in detail.

[0124] like Figure 4 The diagram shown is a schematic diagram of the state transition of state machine 132 in an embodiment of this application.

[0125] The states of state machine 132 are as follows:

[0126] ST1, off state;

[0127] ST2, DC operating point established state;

[0128] ST3, similar frequency injection traction state;

[0129] ST4, the crystal oscillator frequency is gradually stabilizing;

[0130] ST5, normal operating state.

[0131] In ST1 state, when EN=0, ST1 state is maintained;

[0132] In state ST1, when EN=1, the state transitions to state ST2;

[0133] When transitioning from ST2 state to ST3 state, the state transition indicator signal T1 changes from 0 to 1;

[0134] When transitioning from ST3 to ST4, the state transition indicator signal T2 changes from 0 to 1;

[0135] When transitioning from ST4 to ST5, the state transition indicator signal T3 changes from 0 to 1;

[0136] In states ST2, ST3, ST4, and ST5, when EN=0, the state transitions to state ST1.

[0137] Reference Figure 4 In this embodiment of the invention, the state machine 132 realizes the state switching from ST2 (DC operating point establishment state) to ST3 (similar frequency injection traction state) and ST3 to ST4 (crystal oscillator frequency gradually stabilized state) according to the count value NUM1 output by the first counter A, and realizes the state switching from ST4 to ST5 (normal operating state) according to the count values ​​NUM2 and NUM3 output by the second counter B and the third counter C.

[0138] It should be noted that the four read / write registers REGX<3:0> store the four historical pulse values ​​of the second clock signal respectively. That is, it is necessary to collect the four historical pulse values ​​of the second clock signal to determine whether it has reached a stable state.

[0139] In some embodiments, the number of historical pulse values ​​of the second clock signal collected is not limited to the above four, but may be two to five. Correspondingly, the read / write register also needs to be adaptively adjusted according to the number of historical pulse values ​​of the second clock signal to be collected. This embodiment of the invention does not limit this.

[0140] In other embodiments, a FIFO memory can be used instead of the aforementioned read / write register REGX<3:0> to achieve the same functionality.

[0141] Figure 5 The following diagram illustrates the operating waveforms of the crystal oscillator circuit provided in an embodiment of this application. Figure 2 , Figure 3 , Figure 4 and Figure 5 Provide a detailed explanation of each of the above states and the transition process between different states.

[0142] (1) ST1 state is a turn-off state:

[0143] After power-on, the system enable signal EN=0, and the other signals are in the reset state.

[0144] The enable signal RCEN output by the logic control circuit 103 to the RC oscillation circuit 102 remains at a low level, and the RC oscillation circuit 102 does not work.

[0145] When the control port MP2GC of the logic control circuit 103 is high, the second PMOS transistor MP2 is turned off, and the drain terminal VPX of the second PMOS transistor MP2 is low.

[0146] The control ports K1EN, K2EN and K3EN of the logic control circuit 103 are all at low level, which makes the three switches K1, K2 and K3 open. The input terminal XI of the crystal oscillator 10, as well as the input terminal XII and the output terminal XO of the drive module 111, are all kept at low level.

[0147] The clock indicator ports CK1OK and CK2OK, the signal excitation port CKO1, and the clock output port CLKOUT of the logic control circuit 103 all output low levels, and the state transition indicator signals T1, T2, and T3 are all low levels.

[0148] (2) ST2 state is the DC operating point establishment state, that is, the state in which the compensation capacitors C1 and C2 of the crystal oscillator are charged:

[0149] The system enable signal EN switches from low level to high level.

[0150] The enable signal RCEN output by the logic control circuit 103 to the RC oscillation circuit 102 also switches from low level to high level, the RC oscillation circuit 102 starts oscillating, and outputs the first clock signal CLK1. CLK1 will generally remain stable in frequency after a few oscillation cycles.

[0151] When the control port MP2GC of the logic control circuit 103 switches from high level to low level, the second PMOS transistor MP2 switches from the off state to the on state, and the drain terminal VPX of the second PMOS transistor MP2 switches from low level to high level.

[0152] The control port K2EN of the logic control circuit 103 remains at a low level, while the control ports K1EN and K3EN switch from low to high levels, closing the first switch K1 and the third switch K3 and opening the second switch K2. This shorts the input terminal XI of the crystal oscillator 10 with the input terminal XII of the drive module 111, and shorts the input terminal XII of the drive module 111 with the output terminal XO, effectively shorting both ends of the crystal oscillator 10. At this time, the output of the output terminal XO of the drive module 111 gradually rises from 0V to VCC / 2. Since the on-resistance of the switch is very small, the compensation capacitors C1 and C2 of the crystal oscillator 10 can be quickly charged through the output terminal XO of the drive module 111. Correspondingly, the voltages at the input terminals XI and XII of the crystal oscillator 10 and the drive module 111 also quickly rise to VCC / 2, thereby accelerating the charging speed of the compensation capacitors C1 and C2.

[0153] The output ports CK1OK, CK2OK, CKO1, and CLKOUT of the logic control circuit 103 all output low levels, and the status indication signals T1, T2, and T3 are all low levels.

[0154] (3) ST3 state is the near-frequency injection traction state, that is, the process of traction for the crystal oscillator 10 to start oscillation through the input terminal of the near-frequency injection drive module 111 output by the RC oscillation circuit 102:

[0155] The system enable signal EN and the enable signal RCEN of the RC oscillation circuit 102 are kept at a high level.

[0156] The control port MP2GC of the logic control circuit 103 remains at a low level, while the drain terminal VPX of the second PMOS transistor MP2 remains at a high level.

[0157] When the control ports K1EN and K3EN of the logic control circuit 103 switch from high level to low level, the first switch K1 opens, thereby disconnecting the input terminal XII of the drive module 111 from the input terminal XI of the crystal oscillator 10; the third switch K3 opens, thereby disconnecting the XII of the drive module 111 from the output terminal XO. When the control port K2EN switches from low level to high level, the second switch K2 closes, thereby connecting the signal excitation port CKO1 to the input terminal XII of the drive module 111.

[0158] The first clock signal CLK1 output by the RC oscillation circuit 102 is in a stable state. The signal excitation port CKO1 of the logic control circuit 103 outputs an excitation signal consistent with the first clock signal CLK1. This excitation signal is output to the input terminal XII of the drive module 111. The phase of the output signal at the output terminal XO of the drive module 111 is opposite to the phase of the input signal at the input terminal XII. The input terminal XI of the crystal oscillator 10 is connected to the compensation capacitor C1. The crystal oscillator 10 is driven by the output terminal XO of the drive module 111 connected in series. As time goes by, the amplitude gradually increases. After the amplitude increases to a certain value, it will tend to saturate and enter a stable state.

[0159] The clock signal output by the clock output port CLKOUT of the logic control circuit 103 is the first clock signal CLK1. CK1OK switches from low to high, indicating that the clock of the RC oscillation circuit 102 is stable and available. The status indicator signal T1 is high, while T2 and T3 are both low.

[0160] (4) ST4 state is the state in which the crystal oscillator frequency gradually stabilizes:

[0161] The crystal oscillator pulse count is calculated n times (e.g., n=4) within a specific time period (determined by a certain value counted by the RC oscillation circuit 102). When the difference between the maximum and minimum pulse counts calculated in the past n times is less than or equal to ±1, it indicates that the crystal oscillator frequency is stable and enters the next state, namely ST5 state.

[0162] The system enable signal EN and the enable signal RCEN of the RC oscillation circuit 102 are kept at a high level.

[0163] The control port MP2GC of the logic control circuit 103 remains at a low level, while the drain terminal VPX of the second PMOS transistor MP2 remains at a high level.

[0164] The clock signal output by the clock output port CLKOUT of the logic control circuit 103 remains unchanged, and is the first clock signal CLK1 output by the RC oscillation circuit 102. The clock indicator port CK1OK remains at a high level.

[0165] The control port K3EN of the logic control circuit 103 remains at a low level; when the control port K1EN switches from a low level to a high level, the first switch K1 closes, thereby connecting the input terminal XII of the drive module 111 to the input terminal XI of the crystal oscillator 10; when the control port K2EN switches from a high level to a low level, the second switch K2 opens, thereby disconnecting the signal excitation port CKO1 from the input terminal XII of the drive module 111, and the signal excitation port CKO1 stops inputting excitation signals to the input terminal of the drive module 111.

[0166] After XI and XII are connected, their signals are identical, both being sine waves. The phase of the output signal at the output terminal XO of the drive module 111 is opposite to the phase of the input signal XI of the crystal oscillator 10. The crystal oscillator loop is established, and the frequency of the output signal at the output terminal XO of the drive module 111 gradually changes to the actual frequency of the crystal oscillator 10. The state machine internally detects whether the frequency of the crystal oscillator 10 is stable. After the frequency of the crystal oscillator 10 stabilizes, it sends out a state transition indication signal to allow the system to enter the next state. The specific detection process can be found later. Figure 6 Steps 619 to 631 in the process.

[0167] Correspondingly, status indication signals T1 and T2 are at high level, and T3 is at low level.

[0168] (5) ST5 is the normal operating state:

[0169] The system enable signal EN remains high.

[0170] The control port MP2GC of the logic control circuit 103 remains at a low level, while the drain terminal VPX of the second PMOS transistor MP2 remains at a high level.

[0171] When the enable signal RCEN of the RC oscillation circuit 102 switches from high level to low level, the RC oscillation circuit 102 is turned off, and the output of the first clock signal CLK1 is stopped.

[0172] The control ports K2EN and K3EN of the logic control circuit 103 are kept at a low level, while the control port K1EN is kept at a high level.

[0173] The status indication signals T1 and T2 output by the logic control circuit 103 remain at a high level. The status indication signal T3 switches from a low level to a high level.

[0174] When the clock indicator port CK1OK of the logic control circuit 103 switches from high to low, it indicates that the RC oscillator circuit 102 is off, and the output port of the RC oscillator circuit 102 remains low, with no clock signal output. When the clock indicator port CK2OK switches from low to high, it indicates that the crystal oscillator frequency is stable and available. The clock signal output by the clock output port CLKOUT is switched from the first clock signal CLK1 output by the output port of the RC oscillator circuit to the second clock signal output by the output terminal XO of the driver module 111.

[0175] It should be noted that, to prevent metastability during clock switching, a glitch-free dynamic clock switching circuit can be used. During clock switching, the dynamic clock switching circuit ensures a clean, glitch-free clock after switching by synchronously processing the selection signal and using a "handshake" mechanism. For example, using a two-stage synchronous glitch-free structure, the other clock can only be turned on when one clock is turned off to 0, thus avoiding periodic glitches in the output.

[0176] Figure 6 The flowchart of state transition using state machine logic control in the crystal oscillator circuit provided in this application embodiment is shown.

[0177] In this example, the duration of the ST2 state is pre-stored in the read-only register REG1, i.e. Figure 5 The duration from t0 to t1 is denoted as T2' for ease of description; the duration of state ST3 is pre-stored in read-only register REG2, i.e. Figure 5 The duration from t1 to t2 is denoted as T3' for ease of description. The read-only register REG3 stores the preset duration of the first clock signal CLK1 output by the RC oscillation circuit 102, denoted as TP1 for ease of description. This duration TP1 serves as the time base, and the third counter C records the pulse count value of the second clock signal CLK2 within the TP1 time period. The values ​​of T2', T3', and TP1 can be set according to the frequency parameters of the crystal oscillator and the device parameters of the RC oscillation circuit 102 used in the crystal oscillator circuit 100.

[0178] In this embodiment, the first counter A and the second counter B count the pulses of the first clock signal CLK1 output by the RC oscillation circuit 102, and the count values ​​are recorded as NUM1 and NUM2, respectively; the third counter C counts the pulses of the second clock signal CLK2 output by the output terminal XO of the drive module 111, and writes the count values ​​into four read / write registers REGX<3:0> in sequence.

[0179] State machine 132 makes judgments based on the count values ​​of each counter and the values ​​in each register, and performs state transitions based on the judgment results.

[0180] The following also refers to Figures 2 to 6 The state transition process of the state machine 132 described above is explained in detail.

[0181] After power-on, state machine 132 enters ST1 state (i.e., the off state).

[0182] Accordingly, in step 601, state machine 132 determines whether the system enable signal is high, i.e. whether EN=1; if so, the state transitions to ST2 state and step 602 is executed; otherwise, it continues to wait in ST1 state.

[0183] After the system is enabled, state machine 132 enters ST2 state (i.e., the state of charging the compensation capacitors C1 and C2 of the crystal oscillator), reads the value REG1 from the read-only register REG1 in register module 131, and the first counter A starts counting. When the count value NUM1 of the first counter A > REG1, the state indication signal T1 = 1, and state machine 132 transitions from ST2 state to ST3 state. The specific process is as follows:

[0184] In step 602, state machine 132 outputs a high level (LEN=1) to the enable input port of register module 131 and a low level (LRST=0) to its reset port, thereby releasing the reset and enabling each register. Accordingly, the read / write enable ports for each register are as follows: R <0> =0, R <1> =0, R <2> =0, R <3> =0, R <4> =1 (corresponding to the first read-only register REG1), R <5> =0 (corresponding to the second read-only register REG2), R <6> =0 (corresponding to the third read-only register REG3), W <0> =0, W <1> =0, W <2> =0, W <3> =0.

[0185] Simultaneously, state machine 132 outputs a low level to the clear input port of each of the first counters A and a high level to its enable input port, that is: ZEROA=0, CENA=1, and the first counter A enters the enabled state; it outputs a high level to the clear input port of the second counter B and the third counter C and a low level to their enable input port, that is: ZEROB=1, ZEROC=1, CENB=0, CENC=0, and the second counter B and the third counter C enter the disabled state, and their count values ​​remain zero.

[0186] At the same time, the control port of state machine 132 outputs corresponding control signals, including: MP2GC=0, K1EN=1, K2EN=0, K3EN=1.

[0187] At this time, the output port states of state machine 132 are as follows: T1=0, T2=0, T3=0, CK1OK=0, CK2OK=0, CLKOUT=0. CENA=1, ZEROA=0, and counter A is working.

[0188] In step 603, at each rising edge of the counting clock CKIN1, the first counter A counts, and the corresponding count value NUM1 is incremented by 1 at the rising edge of the counting clock CKIN1.

[0189] In step 604, it is determined whether the count value NUM1 is greater than the value of the first read-only register REG1; if so, the state transitions to ST3 and step 605 is executed; otherwise, it continues to wait in ST2.

[0190] After state machine 132 enters ST3 state (i.e., near-frequency injection traction state), it reads the value REG2 from the read-only register REG2 in register module 131. When the count value NUM1 of the first counter A > REG2, the state indication signal T2 = 1, and state machine 132 transitions from ST3 state to ST4 state. The specific process is as follows:

[0191] In step 605, the control port of state machine 132 outputs corresponding control signals, including: K1EN=0, K2EN=1, K3EN=0.

[0192] Accordingly, CK1OK=1, the signal excitation port CKO1 and the clock output port CLKOUT output the first clock signal CLK1, T1=1.

[0193] In step 606, the register read / write enable port is as follows: R <4> =0, R <5> =1, read the value of the second read-only register REG2.

[0194] In step 607, the first counter A counts, that is, the count value NUM1 of the first counter A is incremented by 1 on the rising edge of the counting clock CKIN1. At this time, CENA=1, ZEROA=0, the first counter A is working, and on each rising edge of the counting clock CKIN1, the first counter A counts, and the corresponding count value NUM1 is incremented by 1 on the rising edge of the counting clock CKIN1.

[0195] In step 608, it is determined whether the count value NUM1 of the first counter A is greater than the value of the second register REG2; if so, the state transitions to ST4 and step 609 is executed; otherwise, it continues to wait in ST3.

[0196] After state machine 132 enters ST4 state (i.e., the crystal oscillator frequency gradually stabilizes), it calculates the number of pulses of crystal oscillator 10 within a specific time period n times consecutively (e.g., n=4). When the difference between the maximum and minimum values ​​of the historical n calculated pulse counts is less than or equal to ±1, it indicates that the frequency of crystal oscillator 10 is stable, the state indication signal T3=1, and state machine 132 transitions from ST4 state to ST5 state. The specific process is as follows:

[0197] In step 609, the control port of state machine 132 outputs corresponding control signals: K1EN=1, K2EN=0, causing the first switch K1 to close and the second switch K2 to open, and the signal excitation port CKO1 of state machine 132 to stop outputting the clock signal. Read the enable signal R. <5> =0, R <6> =1. And record the address of the read / write register written to: write_num=0. write_num is used to represent the address of the read / write register REGX, that is, write_num=0, 1, 2, 3 respectively represent REGX. <0> REGX <1> REGX <2> REGX <3> The address; at the same time, read the third read-only register REG3.

[0198] At the same time, state machine 132 outputs a low level to the enable input of the first counter A, i.e., CENA=0, and the first counter A stops counting.

[0199] State transition indicator port of state machine 132: T2=1.

[0200] In step 610, the register read / write enable port is as follows: R <6> =0.

[0201] In step 611, state machine 132 outputs a low level to the clear input port of the second counter B and the third counter C, and outputs a high level to their enable input port, i.e. ZEROB=0, CENB=1, ZEROC=0, CENC=1, and the second counter B and the third counter C enter the enable state.

[0202] In step 612, the second counter B and the third counter C count, i.e., CENB=1, ZEROB=0, the second counter B operates, counting on each rising edge of the counting clock CKIN1, and the corresponding count value NUM2 is incremented by 1 on the rising edge of the counting clock CKIN1. Simultaneously, CENC=1, ZEROC=0, the third counter C operates, counting on each rising edge of the counting clock CKIN2, and the corresponding count value NUM3 is incremented by 1 on the rising edge of the counting clock CKIN2.

[0203] In step 613, it is determined whether the count value NUM2 of the second counter B is greater than the value of the third read-only register REG3. That is, it is determined whether the pulse counting time of the first clock signal CLK1 output by the RC oscillation circuit has reached the set counting time. If yes, step 614 is executed; otherwise, counting continues.

[0204] In step 614, state machine 132 outputs a low level to the enable input ports of the second counter B and the third counter, i.e., CENB=0, CENC=0, and the second counter B and the third counter C stop counting.

[0205] In step 615, W<write_num> =1, which determines the current write address of the read / write register, and writes the count value NUM3 of the third counter C into the read / write register REGX.<write_num> .

[0206] In step 616, `write_num = write_num + 1` updates the write address of the read / write register.<write_num-1> =0, disables the write address of the previous readable and writable register.

[0207] In step 617, state machine 132 outputs a high level to the reset input ports of the second counter B and the third counter, that is, ZEROB=1, ZEROC=1, and the count values ​​of the second counter B and the third counter C are reset to zero.

[0208] In step 618, it is determined whether the write address value write_num of the read-write register is equal to 4; if so, step 619 is executed; otherwise, step 611 is executed, that is, state machine 132 outputs a low level to the clear input port of the second counter B and the third counter C, and outputs a high level to their enable input port, that is, ZEROB=0, CENB=1, ZEROC=0, CENC=1, and the second counter B and the third counter C enter the enable state.

[0209] In step 619, R <1> =1, read REGX <1> Save it as a .reg file.

[0210] In step 620, R <1> =0, W <0> =1, write reg to REGX <0> .

[0211] In step 621, W <0> =0, R <2> =1, read REGX <2> Save it as a .reg file.

[0212] In step 622, R <2> =0, W <1> =1, write reg to REGX <1> .

[0213] In step 623, W <1> =0, R <3> =1, read REGX <3> Save it as a .reg file.

[0214] In step 624, R <3> =0, W <2> =1, write reg to REGX <2> .

[0215] The process from steps 619 to 624 above is similar to the FIFO (First In First Out) write process of a register. In this example, the value stored in the least significant bit of the read-write register REGX<3:0> is deleted, and then the stored value of each subsequent address is moved to the previous address in sequence.

[0216] In step 625, W <2> =0, state machine 132 outputs a low level to the clear input port of the second counter B and the third counter, and outputs a high level to their enable input port, that is: ZEROB=0, CENB=1, ZEROC=0, CENC=1, the second counter B and the third counter C count, that is: the count value NUM2 of the second counter B is incremented by 1 on the rising edge of the counting clock CKIN1, and the count value NUM3 of the third counter C is incremented by 1 on the rising edge of the counting clock CKIN2.

[0217] In step 626, it is determined whether the count value NUM2 of the second counter B is greater than the value of the third read-only register REG3; if so, step 627 is executed; otherwise, step 625 is returned, that is, the second counter B and the third counter C count, and correspondingly, the count value NUM2 is incremented by 1 on the rising edge of the counting clock CKIN1, and the count value NUM3 is incremented by 1 on the rising edge of the counting clock CKIN2.

[0218] In step 627, state machine 132 outputs a low level to the enable input ports of the second counter B and the third counter C, i.e., CENB=0, CENC=0, stopping the counting of the second counter B and the third counter C.

[0219] In step 628, read / write register REGX <3> Write enable signal W <3> =1, write the count value NUM3 of the third counter C into the read / write register REGX. <3> .

[0220] In step 629, read / write register REGX <3> Write enable signal W <3> =0; State machine 132 outputs a high level to the clear input ports of the second counter B and the third counter C, that is, ZEROB=1, ZEROC=1, and the count values ​​of the second counter B and the third counter C are cleared to zero.

[0221] In step 630, determine whether |Max(REGX<3:0>)-min(REGX<3:0>)| is less than or equal to 1, where Max(REGX<3:0>) represents the maximum value among the four values ​​of REGX<3:0>, and min(REGX<3:0>) represents the minimum value among the four values ​​of REGX<3:0>. That is, determine whether the maximum error of the pulse value of the second clock signal output by the output terminal XO of the four drive modules 111 recorded in REGX<3:0> is less than or equal to 1. If yes, it means that the crystal oscillator clock signal CLK2 has reached stability, and step 631 is executed; otherwise, step 619 is executed to continue recording the pulse value of the second clock signal output by the output terminal XO of the drive module 111.

[0222] In step 631, the enable signal output port RCEO of state machine 132 outputs a low level, i.e., RCEO=0, causing the RC oscillation circuit 102 to stop working. The output port states of state machine 132 are as follows: T3=1, CK1OK=0, CK2OK=1, the clock signal output port CLKOUT outputs the second clock signal, and state machine 132 transitions from ST4 state to ST5 state.

[0223] As can be seen, the crystal oscillator circuit provided in this application effectively reduces the initial charging time of the crystal oscillator's compensation capacitor through the initial capacitor charging structure, accelerates the crystal oscillator's start-up time through the near-frequency injection traction method, and has a simple circuit structure that is easy to implement.

[0224] In practical implementation, the output frequency of the RC oscillator circuit 102 is designed to be close to the crystal oscillator frequency. It can adopt any architecture, has low precision requirements, and does not need to be calibrated. For example, its frequency can be designed to deviate from the crystal oscillator frequency by less than ±20%, which can be achieved at low cost.

[0225] like Figure 7 The diagram shown is a schematic diagram of another structure of the crystal oscillator circuit provided in an embodiment of this application.

[0226] and Figure 2 The difference in the illustrated embodiment is that, Figure 7 The crystal oscillator circuit in the illustrated embodiment may further include: an electrostatic discharge (ESD) protection circuit 104, used to provide ESD protection to prevent damage to internal components. A non-limiting embodiment of the ESD protection circuit 104 may include: a first branch connected to the input terminal X1 of the crystal oscillator 10, and a second branch connected to the output terminal X0 of the crystal oscillator 10. Wherein:

[0227] The first branch includes a first diode D1 and a second diode D2 connected in series between ground and the operating power supply VCC. The anode of the first diode D1 is grounded, the cathode of the first diode D1 and the anode of the second diode D2 are connected to the input terminal XI of the crystal oscillator 10, and the cathode of the second diode D2 is connected to the power supply VCC.

[0228] The second branch includes a third diode D3 and a fourth diode D4 connected in series between ground and the operating power supply VCC. The anode of the third diode D3 is grounded, the cathode of the third diode D3 and the anode of the fourth diode D4 are connected to the output terminal XO of the crystal oscillator 10, and the cathode of the fourth diode D4 is connected to the power supply VCC.

[0229] The diodes mentioned above can be electrostatic discharge (ESD) diodes, which operate using the avalanche breakdown effect of semiconductors. Under normal operating conditions, ESD diodes exhibit high impedance, having a negligible impact on the circuit. However, in the event of a transient overvoltage event such as electrostatic discharge, they can quickly switch to a low impedance state, limiting the overvoltage to a safe range and thus protecting downstream circuitry from damage.

[0230] The electrostatic discharge protection circuit 104 described above can provide an electrostatic protection barrier for the circuit, preventing circuit damage or performance degradation caused by electrostatic discharge events.

[0231] Accordingly, this application also provides an electronic device including the crystal oscillator circuit described in the preceding embodiments.

[0232] Accordingly, embodiments of this application also provide a fast startup method for the above-described crystal oscillator circuit, wherein... Figure 8 The diagram shown is a flowchart of this method, which includes the following steps:

[0233] Step 801: After power-on, enable the current circuit, the crystal oscillator drive module starts working, short-circuit the input and output of the crystal oscillator to charge the compensation capacitor of the crystal oscillator quickly, and control the RC oscillator to output the first clock signal.

[0234] Step 802: After the compensation capacitor has finished charging, disconnect the compensation capacitor from the input terminal of the drive module.

[0235] Step 803: Output the first clock signal as the system clock signal and input the first clock signal into the input terminal of the drive module;

[0236] Step 804: After a certain delay, stop inputting the first clock signal to the driving module and reconnect the compensation capacitor to the input terminal of the driving module, so that the driving module drives the crystal oscillator to output the second clock signal.

[0237] Step 805: After the second clock signal stabilizes, the system clock signal is switched from the first clock signal to the second clock signal.

[0238] In some embodiments, state machines and logic operations can be used to control the connection between the crystal oscillator and the drive module, and to control the RC oscillation circuit and the drive module. The specific control process can be found in the description of the crystal oscillator circuit embodiments in the previous application, and will not be repeated here.

[0239] This application embodiment also provides a storage medium, which is a computer-readable storage medium storing a computer program thereon, the computer program being executable during runtime. Figure 6 or Figure 8 The method shown may include some or all of the steps. The storage medium may include read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc. The storage medium may also include non-volatile memory or non-transitory memory, etc.

[0240] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data provider to another website, computer, server, or data provider via wired or wireless means.

[0241] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

Claims

1. A crystal oscillator circuit, characterized in that, The circuit includes: a crystal oscillator core circuit, an RC oscillation circuit, and a logic control circuit; the logic control circuit is coupled to the crystal oscillator core circuit and the RC oscillation circuit respectively; the crystal oscillator core circuit includes a drive module and an auxiliary control module; The RC oscillation circuit is used to generate a first clock signal with a frequency close to that of the crystal oscillator; The driving module is used to drive the crystal oscillator to operate and generate a second clock signal; The logic control circuit is used to control the operation of the RC oscillation circuit and to drive the drive module through the auxiliary control module. When the circuit is enabled, the auxiliary control module drives the drive module to start working. The logic control circuit drives the auxiliary control module to short-circuit the input and output terminals of the crystal oscillator to quickly charge the compensation capacitor of the crystal oscillator. At the same time, it controls the RC oscillation circuit to output the first clock signal. After the compensation capacitor is fully charged, the connection between the compensation capacitor and the input terminal of the drive module is disconnected, and the first clock signal is output as the system clock signal and input to the input terminal of the drive module. After a certain delay, the input of the first clock signal to the drive module is stopped, and the compensation capacitor is reconnected to the input terminal of the drive module, so that the drive module drives the crystal oscillator to output the second clock signal. After the second clock signal stabilizes, the system clock signal is switched from the first clock signal to the second clock signal.

2. The crystal oscillator circuit according to claim 1, characterized in that, The driving module includes: an inverting amplifier, and a feedback resistor connected between the input and output terminals of the inverting amplifier; The auxiliary control module includes: a control switch; the control switch includes: a first switch, a second switch, and a third switch; The first terminal of the first switch is connected to the input terminal of the crystal oscillator, and the second terminal of the first switch is connected to the input terminal of the inverting amplifier; The first end of the second switch is connected to the signal excitation port of the logic control circuit, and the second end of the second switch is connected to the input terminal of the inverting amplifier; The first end of the third switch is connected to the input end of the inverting amplifier, and the second end of the third switch is connected to the output end of the inverting amplifier. The control terminals of the first switch, the second switch, and the third switch are respectively controlled by the logic control signal output by the logic control circuit.

3. The crystal oscillator circuit according to claim 2, characterized in that, The auxiliary control module also includes: The power gate switch, controlled by the output of the logic control circuit, is used to control the drive module to turn on or off the working power.

4. The crystal oscillator circuit according to claim 1, characterized in that, The logic control circuit includes: a register module, a state machine, and a counter module; The counter module is used to count pulses of the first clock signal and the second clock signal; The state machine is used to switch states based on the count value of the counter module and the set and written values ​​in the register module; and to select to output the first clock signal or the second clock signal based on the current state.

5. The crystal oscillator circuit according to claim 4, characterized in that, The counter module includes: a first counter, a second counter, and a third counter; The first counter and the second counter are used to count pulses of the first clock signal; The third counter is used to count pulses of the second clock signal.

6. The crystal oscillator circuit according to claim 5, characterized in that, The states include: ST1, off state; ST2, DC operating point established state; ST3, similar frequency injection traction state; ST4, the crystal oscillator frequency is gradually stabilizing; ST5, normal operating state; The register module includes: three read-only registers and four read-write registers; The three read-only registers include a first read-only register, a second read-only register, and a third read-only register; The first read-only register is used to store the set duration of the ST2 state, the second read-only register is used to store the set duration of the ST3 state, and the third read-only register is used to store the set duration of the first clock signal; The four readable and writable registers are used to store the pulse values ​​of the second clock signal recorded by the third counter.

7. The crystal oscillator circuit according to claim 4, characterized in that, The state machine includes: Clock output port, used to output clock signal; A clock indicator port is used to indicate whether the clock signal output by the clock output port is the first clock signal from the RC oscillation circuit or the second clock signal from the crystal oscillator.

8. The crystal oscillator circuit according to any one of claims 1 to 7, characterized in that, The circuit further includes an electrostatic discharge (ESD) protection circuit for providing ESD protection; the ESD protection circuit includes a first branch connected to the input terminal of the crystal oscillator and a second branch connected to the output terminal of the crystal oscillator. The first branch includes a first diode and a second diode. The anode of the first diode is grounded, and the cathode of the first diode and the anode of the second diode are connected to the input terminal of the crystal oscillator. The cathode of the second diode is connected to the power supply. The second branch includes a third diode and a fourth diode. The anode of the third diode is grounded, and the cathode of the third diode and the anode of the fourth diode are connected to the output terminal of the crystal oscillator. The cathode of the fourth diode is connected to the power supply.

9. A fast start-up method for a crystal oscillator circuit, characterized in that, The method includes: After power-on, the enable circuit and the crystal oscillator drive module start working, shorting the input and output terminals of the crystal oscillator to quickly charge the compensation capacitor of the crystal oscillator, and at the same time controlling the RC oscillation circuit to output the first clock signal. After the compensation capacitor has finished charging, disconnect the compensation capacitor from the input terminal of the drive module. The first clock signal is output as the system clock signal, and the first clock signal is input to the input terminal of the drive module. After a certain delay, the input of the first clock signal to the driving module is stopped, and the compensation capacitor is reconnected to the input terminal of the driving module, so that the driving module drives the crystal oscillator to output the second clock signal. After the second clock signal stabilizes, the system clock signal is switched from the first clock signal to the second clock signal.

10. The fast start-up method for a crystal oscillator circuit according to claim 9, characterized in that, The method further includes: The connection control between the crystal oscillator and the drive module is realized by using a state machine and logic operations, and the control of the RC oscillation circuit and the drive module is also realized. Using the first clock signal, the state machine and the logic operation realize stable detection of the second clock signal.

11. An electronic device, characterized in that, Includes the crystal oscillator circuit as described in any one of claims 1 to 9.

12. A computer-readable and writable storage medium having a computer program stored thereon, characterized in that, The computer program is executed by a computer to perform the steps of the fast startup method for the crystal oscillator circuit according to any one of claims 9 to 10.

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