High-gain floating inverting amplifier for switched capacitor integrator
By employing a high-gain floating inverting amplifier main amplifier and auxiliary amplifier structure in the switched capacitor integrator, the problems of insufficient gain and nonlinear distortion are solved, linearity is improved and power consumption is reduced, making it suitable for high-precision ADCs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-04-07
AI Technical Summary
Existing floating inverting amplifiers have insufficient gain and high nonlinear distortion in switched capacitor integrators, making it difficult to meet the requirements of high-precision ADCs.
A high-gain floating inverting amplifier is adopted. Through the circuit structure and timing design of the main amplifier and auxiliary amplifier, two identical auxiliary amplifiers are used to replace the fixed bias voltage to achieve high gain. The floating node is reset during the sampling stage to ensure the charge integration function.
It significantly improves the linearity and gain of switched capacitor integrators, reduces power consumption, and solves the problems of insufficient gain and nonlinear distortion, making it suitable for high-precision ADCs.
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Figure CN121814036A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a high-gain floating inverting amplifier for a switched capacitor integrator. Background Technology
[0002] Switched-capacitor integrators are a crucial module in noise-shaping analog-to-digital converters (ADCs). Traditional switched-capacitor integrators use operational transconductance amplifiers (OTAs) based on quiescent current and a fixed DC operating point as their core amplifiers. This results in very high power consumption as the circuit's operating speed increases. Floating inverting amplifiers (FIAs) are fully dynamic amplifier circuits with excellent output common-mode characteristics. Their schematic diagram is shown below. Figure 1 As shown. The literature "XYTang, XX Yang, WD Zhao, CK Hsu, JX Liu, LX Shen, A. Mukherjee, W. Shi, DZ Pan, and N. Sun, “A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier,” 2020 IEEE International Solid-State Circuits Conference (Isscc), pp. 162–+, 2020.” first applied FIA to switched-capacitor integrators and found that compared to OTA, FIA can provide a faster settling speed and can realize fully dynamic circuit design, greatly reducing the power consumption of the circuit.
[0003] However, existing floating inverting amplifiers suffer from insufficient gain and high nonlinear distortion when applied to switched capacitor integrators.
[0004] Therefore, it is necessary to improve one or more of the problems existing in the above-mentioned related technical solutions.
[0005] It should be noted that this section is intended to provide background or context for the technical solutions of this disclosure as set forth in the claims. The description herein does not constitute an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0006] The purpose of this disclosure is to provide a high-gain floating inverting amplifier for a switched capacitor integrator, thereby overcoming at least to some extent one or more problems caused by limitations and defects in related technologies.
[0007] According to embodiments of this disclosure, a high-gain floating inverting amplifier for a switched-capacitor integrator is provided, comprising: The main amplifier includes the energy storage capacitor C. res First FIA, Second FIA, First Transistor M P Second transistor M P First transistor M N Second transistor M N First transistor M CP Second transistor M CP First transistor M CN and the first transistor M CN ;in, Energy storage capacitor C res The first end is respectively connected to the first sampling switch φ S The first terminal and the first integrating switch φ int The first terminal is electrically connected, and the first sampling switch φ S The second terminal is connected to the power supply V DD Electrical connection, first integrating switch φ int The second terminal is respectively connected to the first transistor M P The source of the second transistor M P The source and second sampling switch φ S The first terminal is electrically connected, and the second sampling switch φ S The second terminal is connected to the common-mode level V. CM Third sampling switch φ S The first and fourth sampling switches φ S The first terminal is electrically connected, and the third sampling switch φ S The second terminal is connected to the IP1 output terminal of the first FIA and the first transistor M, respectively. P The drain and the first transistor M CP The source electrical connection, the first transistor M CP The gate of the first transistor M is electrically connected to the ON1 terminal of the first FIA. P gate and V IP Terminal electrical connection, fourth sampling switch φ S The second terminal is connected to the IN1 output terminal of the first FIA and the second transistor M, respectively. P The drain and the second transistor M CP The source is electrically connected to the second transistor M. CP The gate of the second transistor M is electrically connected to the OP1 input terminal of the first FIA. P gate and V IP Terminal electrical connection; First transistor M CP Drain and V ON Terminal, first capacitor C LThe first terminal, the first transistor M CN The drain, the fifth sampling switch φ S The first terminal is electrically connected, and the second transistor M CP Drain and V OP Terminal, second capacitor C L The first terminal and the second transistor M CN The drain, the sixth sampling switch φ S The first terminal is electrically connected, and the fifth sampling switch φ S The first end, the sixth sampling switch φ S The first terminal and common-mode level V CM Electrical connection; Energy storage capacitor C res The second end is respectively connected to the seventh sampling switch φ S First terminal and second integral switch φ int The first terminal is electrically connected, and the second integral switch φ int The second terminal is respectively connected to the first transistor M N The source of the second transistor M N The source and the eighth sampling switch φ S The first terminal is electrically connected, and the eighth sampling switch φ S The second terminal is connected to the common-mode level V. CM Ninth sampling switch φ S The first and tenth sampling switches φ S The first terminal is electrically connected, and the ninth sampling switch φ S The second terminal is connected to the IP2 output terminal of the second FIA and the first transistor M, respectively. N The drain and the first transistor M CN The source electrical connection, the first transistor M CN The gate of the first transistor M is electrically connected to the ON2 input terminal of the second FIA. N gate and V IP Terminal electrical connection, tenth sampling switch φ S The second terminal is connected to the IN2 output terminal of the second FIA and the second transistor M, respectively. N The drain and the second transistor M CN The source is electrically connected to the second transistor M. CN The gate of the second transistor is electrically connected to the OP2 input terminal of the second FIA. N gate and V IP Terminal electrical connection.
[0008] Furthermore, the first capacitor C L The second terminal, the second capacitor C L The second and seventh sampling switches φ S The second end of each is grounded.
[0009] Furthermore, the energy storage capacitor C res First transistor M P Second transistor M P First transistor M N Second transistor M N It forms an auxiliary amplifier.
[0010] Furthermore, during the sampling phase, all sampling switches φ S Close, all integral switches φ int Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res Both ends are reset to power supply V. DD And ground, while all outputs are reset to common-mode level V. CM .
[0011] Furthermore, during the integration phase, all integral switches φ int Close, all sampling switches φ S Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform the function of charge integration.
[0012] Furthermore, the DC gain of the high-gain floating inverting amplifier is:
[0013] in, This is the absolute value of the gain of the auxiliary amplifier. The average transconductance of FIA in the integral phase, This is the equivalent output impedance.
[0014] Furthermore, all floating nodes of the main amplifier and auxiliary amplifier in the high-gain floating inverting amplifier are reset to the common-mode level V during the sampling phase. CM .
[0015] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: In the embodiments of this disclosure, the high-gain floating inverting amplifier for the switched-capacitor inverting amplifier described above includes, on the one hand, the circuit structure and timing design of the main amplifier and auxiliary amplifier of the high-gain floating inverting amplifier. The high-gain floating inverting amplifier uses two identical auxiliary amplifiers to replace the fixed bias voltage in a conventional sleeve-type floating inverting amplifier circuit, thereby increasing the gain of the sleeve-type floating inverting amplifier. Resetting all floating nodes of the main amplifier and auxiliary amplifier in the high-gain floating inverting amplifier during the sampling phase can significantly improve the linearity of the switched-capacitor inverting amplifier using this amplifier as the core amplifier. On the other hand, during the sampling phase, all sampling switches φ SClose, all integral switches φ int Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res Both ends are reset to the power supply voltage V. DD And ground, while all outputs are reset to common-mode level V. CM During the integration phase, all integral switches φ int Close, all sampling switches φ S Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform the function of charge integration. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0017] Figure 1 A circuit diagram of a floating inverting amplifier in an exemplary embodiment of this disclosure is shown; Figure 2 This diagram shows a circuit diagram of a switched capacitor integrator in an exemplary embodiment of this disclosure; Figure 3 A timing diagram of the switched capacitor integrator in an exemplary embodiment of this disclosure is shown; Figure 4 This diagram illustrates a sleeve-type floating inverting amplifier circuit in an exemplary embodiment of this disclosure. Figure 5 A schematic diagram illustrating the enhancement of a single-pole amplifier gain in an exemplary embodiment of this disclosure is shown; Figure 6 A circuit diagram of a high-gain floating inverting amplifier for a switched-capacitor integrator is shown in an exemplary embodiment of the present disclosure; Figure 7 A circuit diagram of the auxiliary amplifier in an exemplary embodiment of this disclosure is shown; Figure 8 This diagram illustrates the reset of the floating node of the main amplifier in an exemplary embodiment of this disclosure. Figure 9 This diagram illustrates the reset of the floating node of the auxiliary amplifier in an exemplary embodiment of this disclosure. Figure 10 A comparison graph showing the gain as a function of output swing in an exemplary embodiment of this disclosure is shown; Figure 11 A comparison graph showing the variation of THD with output swing in an exemplary embodiment of this disclosure is shown; Figure 12 A complete circuit diagram of a switched-capacitor integrator based on a high-gain floating inverting amplifier is shown in an exemplary embodiment of this disclosure. Detailed Implementation
[0018] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0019] Furthermore, the accompanying drawings are merely illustrative diagrams of embodiments of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.
[0020] The schematic diagram and timing sequence of the switched capacitor integrator are as follows: Figure 2 and Figure 3 As shown. The integrator's operation is specifically divided into two stages: the sampling stage and the integration stage. In the sampling stage, the sampling phase (φ) S The clock is high, and the integrating phase (φ) int The clock is low, corresponding to φ S When the switch is closed, φ int When the switch is open, the differential input signal is applied to the two sampling capacitors (C). S The system charges the input voltage to achieve sampling. During the integration phase, the integrating phase (φ)... int When the clock is high, the sampling phase (φ) S The clock is low, corresponding to φ int When the switch is closed, φ S When the switch is opened, all the charge stored in the sampling capacitor is transferred to the integrating capacitor (C). int On the amplifier, the integration of charge is achieved. Assuming the amplifier is an ideal amplifier, i.e., with infinite gain, the input-output relationship of the integrator can be obtained as follows: (1) Assume the amplifier's DC gain is A V The input-output relationship of the integrator can be obtained as follows: (2) Comparing equations (1) and (2), it can be seen that since the gain of the amplifier in the switched-capacitor integrator is finite, the gain and pole positions of the circuit transfer function deviate from the ideal situation, and the deviation increases as the amplifier gain decreases. When applied to practical systems, such as high-precision ADCs, this deviation will cause nonlinear distortion, and in severe cases, it will lead to system collapse.
[0021] use Figure 1 The amplifier circuit implemented using the FIA structure shown has a relatively low gain, typically less than 30 dB. When applied to a switched-capacitor integrator, this can cause a significant shift in the system's transfer function, introducing nonlinear errors. To improve the gain, a sleeve-type floating inverting amplifier circuit (CFIA) is used. The schematic diagram of CFIA is shown below. Figure 4 As shown, this circuit structure can only boost the FIA gain to about 50 dB. For some circuit systems that have high requirements for the linearity of switched capacitor integrators, such as multi-stage noise-shaping ADCs, this gain is far from sufficient.
[0022] Figure 5 The circuit structure shown is a method to increase the gain of a single-pole amplifier. The principle is to use gain bootstrapping to further increase the output impedance of the amplifier, thereby further increasing the small-signal gain of the amplifier. Figure 5 The output impedance of the circuit shown is: (3) Where A is the DC gain of the auxiliary amplifier; g m2 r is the transconductance of the M2 transistor; o1 and r o2 These are the small-signal resistances of M1 and M2, respectively. From equation (3), it can be seen that... Figure 5 The output impedance of the structure shown is A times greater than that of the sleeve structure.
[0023] This example implementation provides a high-gain floating inverting amplifier for a switched-capacitor integrator. (Reference) Figure 6 As shown, the high-gain floating inverting amplifier for the switched capacitor integrator may include: The main amplifier includes the energy storage capacitor C. res First FIA, Second FIA, First Transistor M P Second transistor M P First transistor M N Second transistor M N First transistor M CP Second transistor M CP First transistor M CN and the first transistor M CN ;in, Energy storage capacitor Cres The first end is respectively connected to the first sampling switch φ S The first terminal and the first integrating switch φ int The first terminal is electrically connected, and the first sampling switch φ S The second terminal is connected to the power supply V DD Electrical connection, first integrating switch φ int The second terminal is respectively connected to the first transistor M P The source of the second transistor M P The source and second sampling switch φ S The first terminal is electrically connected, and the second sampling switch φ S The second terminal is connected to the common-mode level V. CM Third sampling switch φ S The first and fourth sampling switches φ S The first terminal is electrically connected, and the third sampling switch φ S The second terminal is connected to the IP1 output terminal of the first FIA and the first transistor M, respectively. P The drain and the first transistor M CP The source electrical connection, the first transistor M CP The gate of the first transistor M is electrically connected to the ON1 terminal of the first FIA. P gate and V IP Terminal electrical connection, fourth sampling switch φ S The second terminal is connected to the IN1 output terminal of the first FIA and the second transistor M, respectively. P The drain and the second transistor M CP The source is electrically connected to the second transistor M. CP The gate of the second transistor M is electrically connected to the OP1 input terminal of the first FIA. P gate and V IP Terminal electrical connection; First transistor M CP Drain and V ON Terminal, first capacitor C L The first terminal, the first transistor M CN The drain, the fifth sampling switch φ S The first terminal is electrically connected, and the second transistor M CP Drain and V OP Terminal, second capacitor C L The first terminal and the second transistor M CN The drain, the sixth sampling switch φ S The first terminal is electrically connected, and the fifth sampling switch φ S The first end, the sixth sampling switch φ S The first terminal and common-mode level V CM Electrical connection; Energy storage capacitor C resThe second end is respectively connected to the seventh sampling switch φ S First terminal and second integral switch φ int The first terminal is electrically connected, and the second integral switch φ int The second terminal is respectively connected to the first transistor M N The source of the second transistor M N The source and the eighth sampling switch φ S The first terminal is electrically connected, and the eighth sampling switch φ S The second terminal is connected to the common-mode level V. CM Ninth sampling switch φ S The first and tenth sampling switches φ S The first terminal is electrically connected, and the ninth sampling switch φ S The second terminal is connected to the IP2 output terminal of the second FIA and the first transistor M, respectively. N The drain and the first transistor M CN The source electrical connection, the first transistor M CN The gate of the first transistor M is electrically connected to the ON2 input terminal of the second FIA. N gate and V IP Terminal electrical connection, tenth sampling switch φ S The second terminal is connected to the IN2 output terminal of the second FIA and the second transistor M, respectively. N The drain and the second transistor M CN The source is electrically connected to the second transistor M. CN The gate of the second transistor is electrically connected to the OP2 input terminal of the second FIA. N gate and V IP Terminal electrical connection.
[0024] Through the high-gain floating inverting amplifier described above for the switched capacitor integrator, on the one hand, during the sampling phase, all sampling switches φ S Close, all integral switches φ int Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res Both ends are reset to the power supply voltage V. DD And ground, while all outputs are reset to common-mode level V. CM During the integration phase, all integral switches φ int Close, all sampling switches φ S Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform charge integration. On the other hand, while maintaining the advantages of low power consumption and high energy efficiency of the fully dynamic design, it can solve the problems of insufficient gain and high nonlinear distortion when the floating inverting amplifier is used in the switched capacitor integrator.
[0025] Below, we will refer to Figures 6 to 12 The various parts of the high-gain floating inverting amplifier for the switched capacitor integrator described in this example embodiment will be explained in more detail.
[0026] In one embodiment, this application is based on Figure 5 The method for increasing the gain of a single-pole amplifier is shown. A novel circuit structure for a high-gain floating inverting amplifier is proposed, such as... Figure 6 As shown. This application uses two completely identical optimized and improved conventional FIAs, as follows. Figure 7 As shown, this serves as an auxiliary amplifier, replacing the fixed voltage bias of the CFIA common-gate transistor. The connection method of the auxiliary amplifier is referenced. Figure 6 The working principle of the novel high-gain floating inverting amplifier proposed in this application is as follows: during the sampling phase, all φ S When the switch is closed, all φ int When the switch is open, the energy storage capacitors (C) of the main amplifier and auxiliary amplifier... res The two ends of the circuit are reset to the power supply voltage (V). DD ) and ground, while all outputs are reset to common-mode level (V CM During the integration phase, all φ int When the switch is closed, all φ S When the switch is open, the energy storage capacitors (C) of the main amplifier and auxiliary amplifier... res The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform charge integration. Assume the average transconductance of a conventional Cascoded FIA in the integration phase is... G m,avg The equivalent output impedance is R out The absolute value of the gain of the auxiliary amplifier is A Aux Combining equation (3), the DC gain of the high-gain floating inverting amplifier proposed in this application can be derived as follows: (4) As can be seen from equation (4), the high-gain FIA proposed in this application has a gain that is approximately increased compared to the conventional CFIA. A Aux times.
[0027] In one specific embodiment, since the floating inverting amplifier is a fully dynamic circuit, conventional FIAs and CFIAs both have floating nodes, and the parasitic capacitance (C) of these nodes... parThe charge stored in the integrator is determined by the voltage and noise on the integrating capacitor after the integration phase ends, and is injected into the amplifier in the next integration phase. This introduces random noise, affecting the linearity of the switched capacitor integrator. To improve this issue, all floating nodes of the main amplifier and auxiliary amplifier in the high-gain floating inverting amplifier proposed in this application are reset to the common-mode level (V) during the sampling phase. CM ),like Figure 8 and Figure 9 As shown.
[0028] This application proposes a novel high-gain floating inverting amplifier circuit structure applied to a switched-capacitor integrator. To verify the effectiveness of this application, based on a 130nm CMOS process, under the same load, the gain of the proposed high-gain FIA and a conventional CFIA as a function of output swing were designed and simulated, as shown below. Figure 10 As shown. Figure 10 Simulation results show that the output swing (gain decrease of 3 dB) of the high-gain FIA proposed in this application is basically the same as that of the conventional CFIA, but the high-gain FIA proposed in this application has a significantly improved gain compared to the conventional CFIA. Figure 11 The design of a high-gain FIA is demonstrated in a switched-capacitor integrator. Simulations are performed to show the total harmonic distortion (THD) of the switched-capacitor integrator as a function of the output swing in two cases: resetting all floating nodes and not resetting floating nodes, during the sampling phase. Figure 11 Simulation results show that the method of resetting all floating nodes of the high-gain FIA main amplifier and auxiliary amplifier proposed in this application can effectively reduce the THD of the switched capacitor integrator. This verifies that when the high-gain FIA proposed in this application is applied to the switched capacitor integrator, it can significantly improve the linearity of the circuit.
[0029] In one specific embodiment, the complete circuit of the high-gain floating inverting amplifier proposed in this application applied to a switched capacitor integrator is as follows: Figure 12 As shown. The specific implementation method is: two integrating capacitors (C... int The sampling capacitor (C) is connected across the input and output terminals of the high-gain FIA proposed in this application, respectively, forming a negative feedback connection. S ) and load capacitance (C L Connection method reference Figure 2 Timing Design and Figure 3 Consistent. Figure 12 In the circuit shown, the total load capacitance of the amplifier (C) L,tot )for: (5) Considering the finite bandwidth of the operational amplifier, the input-output relationship of the switched-capacitor integrator can be obtained as follows: (6) Among them, T int For the integral phase (φ) int The total time; τ is the time constant, which is related to the average transconductance of the main amplifier. G m,avg The relationship is: (7) From equations (6) and (7), it can be seen that the setup error of the switched capacitor integrator is directly related to the average transconductance of the main amplifier. The average transconductance of the main amplifier can be obtained by considering the accuracy requirements of the switched capacitor integrator in the system.
[0030] The average transconductance of a floating inverting amplifier can be obtained by the following formula: (8) (9) (10) Where n represents the process parameter; U T This is the thermal voltage, which is positively correlated with temperature, and is approximately 26 mV at room temperature; I AMP (0 + ) by storage capacitor (C res The size of the main amplifier storage capacitor (C) is determined by the average transconductance of the main amplifier. Based on the index of the average transconductance of the main amplifier, and combining equations (8) to (10), the storage capacitor of the main amplifier (C) can be obtained. res The capacitance value. Assume the gate of the main amplifier's sleeve MOS device has a fixed bias voltage (V). CM ), that is, the circuit is Figure 4 The structure of the CFIA is shown. When the storage capacitor (C) res With the capacitance value fixed, it is only necessary to increase the input MOS device (M) value in the main amplifier. p and M N ) and sleeve MOS devices (M CP and M CN The size of the device is sufficient to ensure that it quickly enters the weak inversion region during the integration phase.
[0031] After determining the dimensions of the main amplifier, the value of the load capacitance of the auxiliary amplifier can be obtained, which is the parasitic capacitance of the gate of the MOS device in the main amplifier. The average transconductance of the auxiliary amplifier can be obtained according to equation (7), and then, combined with equations (8) to (10), the storage capacitance (C) in the auxiliary amplifier can be determined. res The capacitance value is used to determine the dimensions of other components in the auxiliary amplifier.
[0032] Through the high-gain floating inverting amplifier described above for the switched capacitor integrator, on the one hand, during the sampling phase, all sampling switches φ S Close, all integral switches φ int Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res Both ends are reset to the power supply voltage V. DD And ground, while all outputs are reset to common-mode level V. CM During the integration phase, all integral switches φ int Close, all sampling switches φ S Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform charge integration. On the other hand, while maintaining the advantages of low power consumption and high energy efficiency of the fully dynamic design, it can solve the problems of insufficient gain and high nonlinear distortion when the floating inverting amplifier is used in the switched capacitor integrator.
[0033] It should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise" in the above description indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.
[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.
[0035] In the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0036] In embodiments of this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0038] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A high-gain floating inverting amplifier for a switched-capacitor integrator, characterized in that, include: The main amplifier includes the energy storage capacitor C. res First FIA, Second FIA, First Transistor M P Second transistor M P First transistor M N Second transistor M N First transistor M CP Second transistor M CP First transistor M CN and the first transistor M CN ; in, Energy storage capacitor C res The first end is respectively connected to the first sampling switch φ S The first terminal and the first integrating switch φ int The first terminal is electrically connected, and the first sampling switch φ S The second terminal is connected to the power supply V DD Electrical connection, first integrating switch φ int The second terminal is respectively connected to the first transistor M P The source of the second transistor M P The source and second sampling switch φ S The first terminal is electrically connected, and the second sampling switch φ S The second terminal is connected to the common-mode level V. CM Third sampling switch φ S The first and fourth sampling switches φ S The first terminal is electrically connected, and the third sampling switch φ S The second terminal is connected to the IP1 output terminal of the first FIA and the first transistor M, respectively. P The drain and the first transistor M CP The source electrical connection, the first transistor M CP The gate of the first transistor M is electrically connected to the ON1 terminal of the first FIA. P gate and V IP Terminal electrical connection, fourth sampling switch φ S The second terminal is connected to the IN1 output terminal of the first FIA and the second transistor M, respectively. P The drain and the second transistor M CP The source is electrically connected to the second transistor M. CP The gate of the second transistor M is electrically connected to the OP1 input terminal of the first FIA. P gate and V IP Terminal electrical connection; First transistor M CP Drain and V ON Terminal, first capacitor C L The first terminal, the first transistor M CN The drain, the fifth sampling switch φ S The first terminal is electrically connected, and the second transistor M CP Drain and V OP Terminal, second capacitor C L The first terminal and the second transistor M CN The drain, the sixth sampling switch φ S The first terminal is electrically connected, and the fifth sampling switch φ S The first end, the sixth sampling switch φ S The first terminal and common-mode level V CM Electrical connection; Energy storage capacitor C res The second end is respectively connected to the seventh sampling switch φ S First terminal and second integral switch φ int The first terminal is electrically connected, and the second integral switch φ int The second terminal is respectively connected to the first transistor M N The source of the second transistor M N The source and the eighth sampling switch φ S The first terminal is electrically connected, and the eighth sampling switch φ S The second terminal is connected to the common-mode level V. CM Ninth sampling switch φ S The first and tenth sampling switches φ S The first terminal is electrically connected, and the ninth sampling switch φ S The second terminal is connected to the IP2 output terminal of the second FIA and the first transistor M, respectively. N The drain and the first transistor M CN The source electrical connection, the first transistor M CN The gate of the first transistor M is electrically connected to the ON2 input terminal of the second FIA. N gate and V IP Terminal electrical connection, tenth sampling switch φ S The second terminal is connected to the IN2 output terminal of the second FIA and the second transistor M, respectively. N The drain and the second transistor M CN The source is electrically connected to the second transistor M. CN The gate of the second transistor is electrically connected to the OP2 input terminal of the second FIA. N gate and V IP Terminal electrical connection.
2. The high-gain floating inverting amplifier for a switched-capacitor integrator according to claim 1, characterized in that, First capacitor C L The second terminal, the second capacitor C L The second and seventh sampling switches φ S The second end of each is grounded.
3. The high-gain floating inverting amplifier for a switched-capacitor integrator according to claim 1, characterized in that, Energy storage capacitor C res First transistor M P Second transistor M P First transistor M N Second transistor M N It forms an auxiliary amplifier.
4. The high-gain floating inverting amplifier for a switched-capacitor integrator according to claim 3, characterized in that, During the sampling phase, all sampling switches φ S Close, all integral switches φ int Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res Both ends are reset to power supply V. DD And ground, while all outputs are reset to common-mode level V. CM .
5. The high-gain floating inverting amplifier for a switched-capacitor integrator according to claim 1, characterized in that, During the integration phase, all integral switches φ int Close, all sampling switches φ S Disconnect the energy storage capacitors C of the main amplifier and auxiliary amplifier. res The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform the function of charge integration.
6. The high-gain floating inverting amplifier for a switched-capacitor integrator according to claim 1, characterized in that, The DC gain of the high-gain floating inverting amplifier is: in, This is the absolute value of the gain of the auxiliary amplifier. The average transconductance of FIA in the integral phase, This is the equivalent output impedance.
7. The high-gain floating inverting amplifier for a switched-capacitor integrator according to claim 1, characterized in that, In a high-gain floating inverting amplifier, all floating nodes of the main amplifier and auxiliary amplifier are reset to the common-mode level V during the sampling phase. CM .