Duty cycle correction of phase interpolator output

Abstract

The invention relates to duty cycle correction of phase interpolator output. An example phase interpolator in an integrated circuit (IC) includes a first circuit including a transistor pair and a current source, the transistor pair including a first transistor coupled between a first node and the current source, and a second transistor coupled between a second node and the current source, a gate of the first transistor is configured to receive a first clock signal, and a gate of the second transistor is configured to receive a second clock signal inverted with the first clock signal; a load circuit including a first inductor coupled between the first node and the second node and a resistor coupled between a voltage source and a center terminal of the first inductor; and a second circuit coupled between the center terminal of the first inductor and alternating current (AC) ground, the second circuit being tuned to conduct a second harmonic of the first clock signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to integrated circuits. BACKGROUND

[0002] Recent growth in data centers and cloud processing has created new research in the field of communication links with high data rates. Examples include copper cable based serializer / deserializer (SerDes) links for short distance rack-to-rack communications. Another example includes coherent light based links for medium to long distance applications (e.g., between data centers). SerDes can be a circuit that can serialize and deserialize data used in device-to-device communications. Both SerDes and optical links can include transceivers for transmitting and receiving signals from a transmission medium. A transceiver can be a circuit that can both transmit and receive signals. A transceiver can include a transmitter and a receiver. A transmitter can be a circuit that transmits signals over a transmission medium. A receiver can be a circuit that observes signals propagating through a transmission medium.

[0003] Both transmitters and receivers can use high precision, multi-phase clock signals in operation. A clock signal can be a signal that switches between two states (called high and low states) at a certain frequency. A multi-phase clock signal can be multiple clock signals at the same frequency that differ in phase. The frequency of a clock signal can be the number of oscillations per unit of time. The phase of a clock can quantify the moment in time when the clock crosses a particular value. Phase can be measured as a phase angle. A clock generator can be a circuit that generates clock signals. For example, a clock generator can generate four clock signals at the same frequency that differ in phase by 90 degrees consecutively. Four-phase clock generation can include an in-phase clock signal (Φ o + 0° phase), a quadrature clock signal (Φ o + 90° phase), a clock signal that is inverted from the in-phase clock signal (Φ o + 180° phase), and a clock signal that is inverted from the quadrature clock signal (Φ o + 270° phase). Inversion can be a difference of 180° between two phases. The quantity Φ o can be an arbitrary phase angle. For purposes of illustration, assume Φ o is zero.

[0004] A phase interpolator (PI) can be a circuit that receives multi-phase clock signals as input and generates clock signals as output, where a phase somewhere between the phases of the input clock signals (e.g., interpolated) differs by a value based on an input control code. For example, a PI can receive four-phase clock signals as input and generate four-phase clock signals as output, but each clock signal is shifted by a selected phase angle, such as the phase clock signal, the phase clock signal, the phase clock signal, and the phase clock signal.a phase clock signal, wherein is a selected phase angle. Non-idealities in the PI can result in a duty cycle distortion (DCD) in each output clock signal. A duty cycle of a clock signal can be a percentage of time that the clock signal is in a high state.

[0005] The presence of DCD can affect the performance of circuits that use the output clocks from the PI. A duty cycle correction (DCC) circuit can be a circuit that mitigates or eliminates DCD in a clock signal. Each clock signal output from the PI can include a separate DCC to compensate for DCD. As the number of clock signals of different phases increases, the power and circuit area consumed by multiple DCCs to compensate for DCD also increases. SUMMARY

[0006] In an embodiment, a phase interpolator in an integrated circuit (IC) is described. The phase interpolator can include a first circuit including a transistor pair and a current source. The transistor pair can include a first transistor coupled between a first node and the current source, and a second transistor coupled between a second node and the current source. A gate of the first transistor can be configured to receive a first clock signal, and a gate of the second transistor can be configured to receive a second clock signal that is inverted from the first clock signal. The phase interpolator can include a load circuit including a first inductor coupled between the first node and the second node, and a resistor coupled between a voltage source and a center terminal of the first inductor. The phase interpolator can include a second circuit coupled between the center terminal of the first inductor and an alternating current (AC) ground, the second circuit tuned to conduct a second harmonic of the first clock signal.

[0007] In another embodiment, a phase interpolator in an integrated circuit (IC) is described. The phase interpolator can include a first current source and a second current source. The phase interpolator can include a first transistor pair including a first transistor coupled between a first node and the first current source, and a second transistor coupled between a second node and the first current source. The first transistor pair can be configured to output a first clock signal at the first node and a second clock signal at the second node, the second clock signal being inverted from the first clock signal. The phase interpolator can include a second transistor pair including a third transistor coupled between a third node and the second current source, and a fourth transistor coupled between a fourth node and the second current source. The second transistor pair can be configured to output a third clock signal at the third node that is orthogonal to the first clock signal and a fourth clock signal at the fourth node that is inverted from the third clock signal. The phase interpolator can include a first inductor coupled between the first and second nodes and a second inductor coupled between the third and fourth nodes. The phase interpolator can include a first resistor coupled between a voltage source and a center terminal of the first inductor and a second resistor coupled between the voltage source and a center terminal of the second inductor. The phase interpolator can include a first network coupled between the center terminal of the first inductor and an alternating current (AC) ground. The phase interpolator can include a second network coupled between the center terminal of the second inductor and the AC ground.

[0008] In another embodiment, a clock distribution circuit in an integrated circuit (IC) is described. The clock distribution circuit can include a phase interpolator. The phase interpolator can include a first circuit including a pair of transistors and a current source. The pair of transistors can include a first transistor coupled between a first node and the current source, and a second transistor coupled between a second node and the current source. A gate of the first transistor can be configured to receive a first clock signal, and a gate of the second transistor is configured to receive a second clock signal that is inverted from the first clock signal. The phase interpolator can include a load circuit including a first inductor coupled between the first node and the second node, and a first resistor coupled between a voltage source and a center terminal of the first inductor. The phase interpolator can include a second circuit coupled between the center terminal of the first inductor and an alternating current (AC) ground, the second circuit tuned to conduct a second harmonic of the first clock signal. The clock distribution circuit can include a third circuit coupled to the first node. The third circuit can include a first series of inverters, a second resistor coupled between an input and an output of a first inverter in the first series. The clock distribution circuit can include a fourth circuit coupled to the second node. The fourth circuit can include a second series of inverters, a third resistor coupled between an input and an output of a second inverter in the second series. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram depicting a communication circuit according to some embodiments.

[0010] Figure 2A is a block diagram depicting a clock distribution circuit according to some embodiments.

[0011] Figure 2B is a block diagram depicting a PI of the clock distribution circuit of Figure 2A according to some embodiments.

[0012] Figure 3 is a schematic diagram depicting a PI core according to some embodiments.

[0013] Figure 4A is a schematic diagram depicting a CMOS converter according to some embodiments.

[0014] Figure 4B is a schematic diagram depicting a model of the converter of Figure 4A with distortion on an input clock signal.

[0015] Figure 5A is a plot depicting amplitude versus duty cycle of a clock signal output from the converter of Figure 4A without DCD compensation.

[0016] Figure 5B is a plot depicting the phase and duty cycle of a clock signal output from a Figure 4A converter without DCD compensation.

[0017] Figure 6 is a schematic diagram of a model of a PI core of a Figure 3 coupled to a load circuit and a harmonic potential well according to embodiments.

[0018] Figure 7A is a schematic diagram of a harmonic potential well according to some embodiments.

[0019] Figure 7B is a side view of an IC in which a harmonic potential well of Figure 7A may be implemented according to some embodiments.

[0020] Figure 7C is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of Figure 7A according to some embodiments.

[0021] Figure 7D is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of a quadrature PI according to some embodiments.

[0022] Figure 8A is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of a quadrature PI according to other embodiments.

[0023] Figure 8B is a side view of a physical layout shown in Figure 8A according to some embodiments.

[0024] Figure 9A is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of a quadrature PI according to other embodiments.

[0025] Figure 9B is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of a quadrature PI according to other embodiments.

[0026] Figure 10A is a schematic diagram of a harmonic potential well according to other embodiments.

[0027] Figure 10B is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of Figure 10A according to other embodiments.

[0028] Figure 11A is a mixed physical layout and schematic diagram of a load circuit and a harmonic potential well of Figure 10A according to other embodiments.

[0029] Figure 11B is a mixed physical layout and schematic of a load circuit and harmonic potential well for quadrature PI according to other embodiments.

[0030] Figure 12 is a mixed physical layout and schematic of a load circuit and harmonic potential well for quadrature PI according to other embodiments. DETAILED DESCRIPTION

[0031] Figure 1 is a block diagram depicting a communication circuit 10 according to some embodiments. The communication circuit 11 can include a transceiver 13 in an integrated circuit (IC) 11. The IC can be a set of circuits formed from a semiconductor material and conductive interconnects disposed on the semiconductor material. The conductive interconnects can be structures that form or electrically connect circuit elements. Various semiconductor materials and semiconductor fabrication processes are known for making ICs. Persons of skill in the art can select among one or more such materials and processes based on the description of examples and embodiments herein. Complementary metal-oxide-semiconductor (CMOS) fabrication processes for forming integrated circuits on silicon are widely used and well known. Thus, for clarity, various examples and embodiments are described below within the context of ICs formed using CMOS fabrication processes.

[0032] The transceiver 13 can include a transmitter 12 and a receiver 14. The transmitter 12 can transmit signals to a transmission medium 15, shown as TX medium 15. The receiver 14 can observe signals from the transmission medium 15. The transmission medium can be a physical path for propagating signals. The transmission medium 15 can be wired (e.g., copper cable, optical link, etc.) or wireless (e.g., over the air).

[0033] The IC 11 includes a clock generator 16 and clock distribution circuitry 18. The clock generator 16 can be a phase-locked loop (PLL) or similar type of well-known circuit configured to generate clock signals. In some embodiments, the clock generator 16 can generate four clock signals 20 that are phase-continuous with a 90-degree difference in phase. The clock signals 20 can be sinusoidal signals having a common frequency and different phases. A sinusoidal signal can be a signal having a waveform based on a sine or cosine function.

[0034] The clock distribution circuit can be a circuit that provides clock signals to other circuits. The clock distribution circuit 18 can distribute clock signals 21 to the transmitter 12 and the receiver 14. The clock distribution circuit 18 can generate the clock signals 21 by manipulating the clock signal 20 output from the clock generator 16. In some embodiments, the clock distribution circuit 18 outputs four clock signals 21 that are 90 degrees out of phase in succession by manipulating the clock signal 20. The clock signals 21 can be square wave signals that have a common frequency and different phases. A square wave signal can be a signal that has a non-sinusoidal waveform in which the amplitude repeatedly rises sharply to a maximum amplitude, remains at the maximum amplitude for a period of time, falls sharply to a minimum amplitude, and remains at the minimum amplitude for a period of time. The clock 21 can be used by circuits of the transmitter 12, for example, by a digital-to-analog converter (DAC). A DAC can be a circuit that converts a digital signal to an analog signal. An analog signal can be a signal that is continuous in time and represents some other quantity, referred to as the amplitude or level of the signal. A digital signal can be a signal that is discrete in time and represents some other quantity as discrete values. The clock 21 can be used by circuits of the receiver 14, for example, by an analog-to-digital converter (ADC). An ADC can be a circuit that converts an analog signal to a digital signal. DACs and ADCs are just some example circuits, and many other types of circuits can use the multiphase clock signals generated by the embodiments and examples herein.

[0035] Figure 2A is a block diagram depicting a clock distribution circuit 18 according to some embodiments. Example applications of the clock distribution circuit 18 are shown in Figure 1 and described above. It should be understood that the clock distribution circuit 18 can have various other applications of circuits that use multiphase clock signals.

[0036] The clock distribution circuit 18 can include a phase interpolator (PI) 22, converters 281...284, and a control circuit 26. The PI 22 can include an input for receiving the clock signal 20. The clock signal 20 can include an in-phase clock signal (I), a clock signal that is inverted from the in-phase clock signal (IB), a quadrature (Q) clock signal, and a clock signal that is inverted from the quadrature clock signal (QB). The I, Q, IB, and QB clock signals can have a common frequency and phases of (Φ0+0°), (Φ0+90°), (Φ0+180°), and (Φ0+270°), respectively, where Φ0may be an arbitrary phase angle. The PI 22 can include an input for supplying the clock signals 21. The PI 22 can delay the clock signals 20 by selected phase angles to generate the clock signals 21. The PI 22 can output phase-delayed versions of the clock signals I and IB, which are referred to as OI and OIB, respectively. The PI 22 can output phase-delayed versions of the clock signals Q and QB, which are referred to as OQ and OQB, respectively. The OI, OQ, OIB, and OQB clock signals can have a common frequency and phases of (Φ0+0°), (Φ0+90°), (Φ0+180°), and (Φ0+270°), respectively. and a phase, where may be a selected phase angle. The control circuit can be a circuit comprising digital logic configured to perform functions. Digital logic can be circuitry that manipulates digital signals, and can include logic gates, arithmetic logic units (ALUs), processors, memory, and the like, or any combination thereof. The control circuit 26 can generate phase selection signals for the PI 22 to select phase angles

[0037] In some embodiments, the PI 22 includes PI cores 241 and 242. Each of the PI cores 241 and 242 can receive the clock signal 20. The PI core 241 can generate OI and OIB clock signals as outputs. The PI core 242 can generate OQ and OQB clock signals as outputs. Thus, the PI core 241 can be referred to as an in-phase (I) PI core and the PI core 242 can be referred to as a quadrature (Q) PI core. The PI 22 can be referred to as a quadrature PI. The control circuit 26 can provide an I phase selection signal to the PI core 241 and a Q phase selection signal to the PI core 242. The PI core 241 can include a harmonic potential well 301 and the PI core 242 can include a harmonic potential well 302. Other types of PIs known in the art can also be used with the techniques described herein. For example, a PI can include a single PI core that supplies two clock phases to a multi-phase filter, which in turn outputs four clock phases. Such a PI can include a harmonic potential well in a single PI core. The functions of the harmonic potential well in the PI cores and embodiments thereof are described below.

[0038] As discussed above, the clock signals 20 and 21 can be sinusoidal signals. In some embodiments, the circuitry coupled to the clock distribution circuit 18 can use clock signals having square waveforms. The converters 281...284 can be circuits that convert sinusoidal input signals to square wave output signals. The converters 281...284 can receive the OI, OIB, OQ, and OQB clock signals, respectively. The converters 281...284 can output square wave clock signals CLK0, CLK180, CLK90, and CLK270, respectively.

[0039] In some embodiments, each of the converters 281...284 can include a DCC control loop for compensating for DCD. The DCC control loop is discussed further below. As discussed above, operating the DCC control loop for each phase of a multi-phase clock signal can be expensive in terms of power consumption and circuit area. The control circuit 26 can supply a DCC enable signal (DCC EN) to each converter 281...284. The DCC enable signal can be used to turn off the DCC control loop in each converter 281...284. The PI 22 can use the harmonic potential wells 301 and 302 to compensate for DCD, as discussed further below. In other embodiments, the converters 281...284 can omit the circuitry of the DCC control loop. In such embodiments, the control circuit 26 can omit the DCC enable signal.

[0040] Figure 2B is a block diagram depicting the PI 22 according to some embodiments. Figure 2B Circuitry of the PI cores 241 and 242 is shown according to some embodiments. Figure 3 is a schematic diagram depicting the PI core 300 according to some embodiments. Each of the PI cores 241 and 242 can be implemented as shown for the PI core 300. For clarity, the discussion Figure 2A below returns to the discussion of the PI 22 Figure 3 .

[0041] The PI core 300 can include circuitry of transistors, current sources, the load 36, and the harmonic potential well 30. The transistors can be field effect transistors (FETs). A FET can be a four-terminal device having a gate, a source, a drain, and a substrate terminal. Unless otherwise indicated, the transistors described herein have their substrate terminal coupled to their source terminal, and thus, the substrate terminal is not explicitly shown. A FET can be a p-channel FET or an n-channel FET, where n and p refer to the type of doping in the semiconductor material and the type of majority charge carriers, as known in the art. By convention, any n-channel transistor is schematically shown with the source as an arrow away from the gate, and any p-channel transistor is schematically shown with the source as an arrow facing the gate. There are many types of FETs known in the art from which one or more can be selected by a person of ordinary skill in the art based on the description of examples and embodiments herein. Metal oxide semiconductor field effect transistors (MOSFETs) are widely used and well known FETs in CMOS-based ICs. A p-channel MOSFET can be referred to as a PMOS transistor, and an n-channel MOSFET can be referred to as an NMOS transistor. Thus, for clarity, various examples and embodiments are described below within the context of an NMOS transistor, a PMOS transistor, or a combination thereof.

[0042] The PI core 300 can include differential transistor pairs 321...324. A transistor pair can be a first transistor coupled to a second transistor. For example, a source-coupled transistor pair can be a first transistor and a second transistor with their sources coupled. In some cases, the sources of the transistors in a source-coupled pair can be directly coupled. In other cases, the sources of the transistors in a source-coupled pair can be coupled through an impedance, sometimes referred to as a source degeneration impedance. A differential transistor pair can be a source-coupled transistor pair with their gates receiving a differential signal pair. A differential signal pair can be two signals of equal magnitude and opposite polarity (e.g., a first signal and a second signal that is inversely phased from the first signal). One signal in a differential signal pair can be referred to as a positive signal, and the other signal can be referred to as a negative signal. In some embodiments, the differential transistor pairs 33k (k e {1, 2, 3, 4}) include a transistor 42k and a transistor 44k. Each of the transistors 42k and 44k can be an NMOS transistor. The source of the transistor 42k can be coupled to the source of the transistor 44k. The drain of the transistor 42k can be coupled to a node 46. The drain of the transistor 44k can be coupled to a node 48. A node can be a point in a circuit at which two or more circuit elements are connected. A node can be shown in the figures as a solid circle at the junction of wires. It should be noted that, for ease of illustration, a node can be shown as two or more separate junctions connected only by wires, without circuit elements (e.g., a shorted connection). In this case, the reference number assigned to the node can be at one of the junctions or at one of the wires between the junctions, all of which collectively represent the node.

[0043] The differential transistor pair 321 can receive a differential signal pair including an I clock signal (positive signal) and an IB clock signal (negative signal). The I clock signal can be coupled to the gate of the transistor 421 and the IB clock signal can be coupled to the gate of the transistor 441. The differential transistor pair 322 can receive a differential signal pair including an IB clock signal (positive signal) and an I clock signal (negative signal). The IB clock signal can be coupled to the gate of the transistor 422 and the I clock signal can be coupled to the gate of the transistor 442. The differential transistor pair 323 can receive a differential signal pair including a Q clock signal (positive signal) and a QB clock signal (negative signal). The Q clock signal can be coupled to the gate of the transistor 423 and the QB clock signal can be coupled to the gate of the transistor 443. The differential transistor pair 324 can receive a differential signal pair including a QB clock signal (positive signal) and a Q clock signal (negative signal). The QB clock signal can be coupled to the gate of the transistor 424 and the Q clock signal can be coupled to the gate of the transistor 444. The I, IB, Q, and QB clock signals can be supplied by a clock generator (e.g., a clock generator 20 of Figure 1 、 2A .

[0044] The PI core 300 can include current sources 401...404. A current source can be a circuit that supplies a current with a magnitude and a direction. An independent current source can be a current source that is independent of a voltage across the circuit, which is within a compliance voltage range (e.g., a current source can supply a minimum and a maximum voltage to a load, beyond which the circuit is no longer an independent current source). Each of the current sources 401...404 can be an independent current source. In addition, each of the current sources 401...404 can be a weighted current source. A weighted current source can be a current source in which the magnitude of the current has a selectable weight between a minimum weight and a maximum weight (e.g., the current can have a magnitude that is one of a plurality of discrete magnitudes). The weighted nature of the current sources is indicated in the figures by an arrow diagonally through the current source symbol. The weighting of the current sources 401...404 can be controlled by a control circuit (e.g., the control circuit 26 of Figure 2A .

[0045] The current source 401 can be coupled between a ground 34 and a node formed by the sources of the transistors 421 and 441. A ground can be a reference point in a circuit from which voltages in the circuit are measured. The ground 34 can be a direct current (DC) ground. A DC ground can be a ground that serves as a reference point for DC voltages in a circuit. The current source 401 can supply a current II. The current source 402 can be coupled between the ground 34 and a node formed by the sources of the transistors 422 and 442. The current source 402 can supply a current IIB. The current source 403 can be coupled between the ground 34 and a node formed by the sources of the transistors 423 and 443. The current source 403 can supply a current IQ. The current source 404 can be coupled between the ground 34 and a node formed by the sources of the transistors 424 and 444. The current source 404 can supply a current IQB. The directions of the currents II, IIB, IQ, and IQB can be toward the ground 34 (e.g., the current sources sink current from their respective differential transistor pairs).

[0046] The combination of a differential transistor pair and a current source as shown can be a transconductance circuit. A transconductance circuit can be a circuit that converts a voltage to a current. The PI core 300 can include transconductance circuits 331...334. The transconductance circuit 33k (k e {1, 2, 3, 4}) can include a differential transistor pair 32k and a current source 40k.

[0047] A load 36 can be coupled between a supply voltage (VDD) and each of nodes 46 and 48. A harmonic potential well 30 can be coupled between the load 36 and a ground 38. The ground 38 can be an alternating current (AC) ground. An AC ground can be a ground that serves as a reference point for AC voltages in a circuit. The load 36 can be an impedance network. A network can be an interconnection of circuit components. Impedance can be a component opposite to current. Example impedances include resistors, capacitors, and inductors as discrete circuit components. Some impedances can be part of or properties of components (e.g., the inter-terminal capacitance of a transistor). Embodiments of the load 36 are shown in Figure 6

[0048] In operation, the transconductance circuits 331...334 can draw current through the load 36 in response to respective input differential signal pairs. The transconductance circuits 331...334 can combine to direct current between a first branch between the load 36 and node 46 and a second branch between the load 36 and node 48. The load 36 can convert the current into a differential voltage signal pair (with a positive signal Op and a negative signal On) at nodes 46 and 48. The voltage signal Op has a frequency in common with the input clock signals (I, IB, Q, QB) and a phase that is a vector sum of the phases of the input clock signals. The vector sum can be determined based on the weighting of the current sources 401...404. The voltage signal On is inverted from the voltage signal Op. The PI core 300 can enable a 0 to 360° phase rotation.

[0049] Returning to Figure 2B , the PI core 241 (e.g., IPI core) can include differential transistor pairs 331...334 (shown as DPs 331...334) and current sources 401...404 (shown as CSs 401...404). The differential transistor pairs 331...334 and the current sources 401...404 can be respectively Figure 3 ​The example of differential transistor pairs 32I1...32I4 and current sources 40I1...40I4 is shown in FIG. 3. Differential transistor pair 32I1 can receive a differential signal pair including I clock signal (positive signal) and IB clock signal (negative signal). Differential transistor pair 32I2 can receive a differential signal pair including IB clock signal (positive signal) and I clock signal (negative signal). Differential transistor pair 32I3 can receive a differential signal pair including Q clock signal (positive signal) and QB clock signal (negative signal). Differential transistor pair 32I4 can receive a differential signal pair including QB clock signal (positive signal) and Q clock signal (negative signal). Current sources 40I1...40I4 can supply currents II, IIB, IQ, and IQB, respectively. The weighting of current sources 40I1...40I4 can be controlled by I phase select signals from control circuit 26. The outputs of differential transistor pairs 32I1...32I4 can be coupled to nodes 46I and 48I. Load circuit 36I can be coupled to nodes 46I and 48I. Node 46I can supply clock signal OIB, and node 48I can supply clock signal OI.

[0050] PI core 242 (e.g., Q PI core) can include differential transistor pairs 33Q1...33Q4 (shown as DP 33Q1...33Q4) and current sources 40Q1...40Q4 (shown as CS 40Q1...40Q4). Differential transistor pairs 33Q1...33Q4 and current sources 40Q1...40Q4 can be respectively Figure 3 The example of differential transistor pairs 32Q1...32Q4 and current sources 40Q1...40Q4 is shown in FIG. 3. Differential transistor pair 32Q1 can receive a differential signal pair including I clock signal (positive signal) and IB clock signal (negative signal). Differential transistor pair 32Q2 can receive a differential signal pair including IB clock signal (positive signal) and I clock signal (negative signal). Differential transistor pair 32Q3 can receive a differential signal pair including Q clock signal (positive signal) and QB clock signal (negative signal). Differential transistor pair 32Q4 can receive a differential signal pair including QB clock signal (positive signal) and Q clock signal (negative signal). Current sources 40Q1...40Q4 can supply currents II, IIB, IQ, and IQB, respectively. The weighting of current sources 40Q1...40Q4 can be controlled by Q phase select signals from control circuit 26. The outputs of differential transistor pairs 32Q1...32Q4 can be coupled to nodes 46Q and 48Q. Load circuit 36Q can be coupled to nodes 46Q and 48Q. Node 46Q can supply clock signal OQB, and node 48Q can supply clock signal OQ.

[0051] The PI core 241 can include a harmonic potential well 301 coupled between the load 36I and the ground 38. The PI core 242 can include a harmonic potential well 30Q coupled between the load 36Q and the ground 38. The harmonic potential wells 301 and 30Q can be examples of the harmonic potential well 30 shown in FIG. 1. As shown, the harmonic potential wells 301 and 30Q can share a common AC ground, such as the ground 38. Embodiments for implementing the harmonic potential wells 301 and 30Q with a common AC ground are described below. Figure 3 The PI core 241 can include a harmonic potential well 301 coupled between the load 36I and the ground 38. The PI core 242 can include a harmonic potential well 30Q coupled between the load 36Q and the ground 38. The harmonic potential wells 301 and 30Q can be examples of the harmonic potential well 30 shown in FIG. 1. As shown, the harmonic potential wells 301 and 30Q can share a common AC ground, such as the ground 38. Embodiments for implementing the harmonic potential wells 301 and 30Q with a common AC ground are described below.

[0052] Figure 4A is a schematic diagram depicting a converter 400 according to some embodiments. Each converter 281...284 can be implemented as shown for the converter 400. The converter 400 includes a capacitor 52, inverters 541...544, switches 53 and 55, a resistor 57, and optionally a DCC circuit 62. The capacitor 52 can be coupled between an input of the converter 400 and a node 51. The inverters 541...544 can be coupled in series. The inverter 541 can be coupled between the node 51 and an input of the inverter 542. The inverter 542 can be coupled between the inverter 541 and 543. The inverter 543 can be coupled between the inverter 542 and 544. The inverter 544 can be coupled between the inverter 543 and an input of the DCC circuit 62. An output of the DCC circuit 62 can be coupled to the node 51 through the switch 55. A series combination of the switch 53 and the resistor 57 can be coupled between the node 51 and a node between the inverters 541 and 542. The switches 53 and 55 can be single-pole single-throw (SPST) switches. An SPST switch can be a circuit component that selectively connects two terminals based on a control input. For example, an SPST switch can be implemented using a transistor. The control input of the switch 55 is a DCC enable signal (DCC EN). The control input of the switch 53 is a logical inverse of the DCC enable signal (shown as NOT DCC EN). A sinusoidal clock signal can be coupled to the input of the converter 400 through the capacitor 52 (e.g., one of the clock signals OI, OIB, OQ, and OQB). The node between the output of the inverter 544 and the input of the DCC circuit 62 can provide a clock signal having a square waveform as an output. The number of inverters can be any even number (e.g., 2, 4, etc.). Each inverter 541...544 can be a CMOS logic circuit.

[0053] The DCC circuit 62 can include a resistor 61, a capacitor 64, a capacitor 65, and an operational amplifier 63. The output of the inverter 544 can be coupled through the resistor 61 to the inverting input of the operational amplifier 63. The capacitor 64 can be coupled between the non-inverting input of the operational amplifier 63 and ground 34. The capacitor 65 can be coupled between the output and the inverting input of the operational amplifier 63. The output of the operational amplifier 63 can be the output of the DCC circuit 62 (e.g., the output of the operational amplifier 63 can be coupled through the switch 55 to the node 51).

[0054] When the switch 55 is closed (e.g., DCC EN is set active), the DCC circuit 62 can be connected to form a DCC loop. The DCC circuit 62 acts as an error amplifier. However, as discussed above, more enabled DCC loops in an enabled converter result in increased power consumption. Thus, in embodiments, the control circuit 26 can set the DCC enable signal to inactive, which can open the switch 55 and shut off the DCC circuit 52 (e.g., no DCC loop). The switch 53 can be closed to connect the resistor 57 and provide self-biasing for the inverter 541. As discussed below, the harmonic well in the PI core can be used to compensate for the DCD. In some embodiments, the DCC circuit 62 can be omitted from the converter 400. In this embodiment, the switches 55 and 53 can also be omitted, and the resistor 57 can be coupled between the input and output of the inverter 541. In addition to reducing power consumption, this embodiment can also save circuit area.

[0055] Figure 4B is a schematic diagram depicting a model of the converter 400 with distortion on the input clock signal. In Figure 4B , it is assumed that the DCC circuit 62 is shut off (DCC EN is inactive) or omitted. The input clock can be represented by an AC source with a waveform Ain cos (coot), where Ain is the amplitude (e.g., in millivolts), coo is the angular frequency in radians / second, and t is the independent variable representing time. It has been observed that the DCD can be contributed by the high-order even-mode harmonics generated inside the PI. A harmonic of a sinusoidal signal with a fundamental frequency can be a signal with a frequency that is an integer multiple of the fundamental frequency. The second harmonic can be a harmonic with a frequency that is twice the fundamental frequency. In particular, the presence of the second harmonic can significantly change the duty cycle of the clock signal output from the converter 400 (without compensation in the PI). This can be represented by an AC source superimposed on the input clock with a waveform AH2 cos (2coot + Φ), where AH2 is the amplitude of the second harmonic (e.g., in millivolts), 2coo is the angular frequency in radians / second, and Φ is the initial phase of the second harmonic.

[0056] Figure 5Ais a plot depicting the amplitude versus duty cycle of a clock signal output from converter 400 without DCD compensation. The plot includes a vertical axis representing duty cycle (as a %) and a horizontal axis representing the amplitude of the second harmonic (in mV). The plot is qualitative rather than quantitative. The amplitude H2 increases from left to right starting from zero. The duty cycle percentage increases upward starting from 50 and decreases downward starting from 50. Curve 502 can represent the relationship for a 180° initial phase of the second harmonic. Curve 504 can represent the relationship for a 90° initial phase of the second harmonic. Curve 506 can represent the relationship for a 0° initial phase of the second harmonic. As can be seen from the plot, if the amplitude of the second harmonic is reduced, the output duty cycle improves (e.g., tends toward 50%). Furthermore, if the initial phase of the second harmonic is 90° (or 270°) compared to the fundamental (e.g., clock signal), the duty cycle dependence on the second harmonic is also reduced.

[0057] Figure 5B is a plot depicting the phase versus duty cycle of a clock signal output from converter 400 without DCD compensation. The plot includes a vertical axis representing duty cycle (as a %) and a horizontal axis representing the initial phase of the second harmonic (in degrees). The plot is qualitative rather than quantitative. The amplitude H2 increases from left to right starting from zero. The duty cycle percentage increases upward starting from 50 and decreases downward starting from 50. Curve 510 can represent the relationship for a second harmonic amplitude of two units (e.g., a unit can be any amount of mV). Curve 512 can represent the relationship for a second harmonic amplitude of one unit. Curve 514 can represent the relationship for a second harmonic amplitude of zero units. Similar to the plot in Figure 5A , as can be seen from the plot in Figure 5B , if the amplitude of the second harmonic is reduced, the output duty cycle improves (e.g., tends toward 50%). Furthermore, if the initial phase of the second harmonic is 90° (or 270°) compared to the fundamental (e.g., clock signal), the duty cycle dependence on the second harmonic is also reduced.

[0058] Figure 6is a schematic diagram depicting a model 600 of a PI core 300 coupled to a load circuit and a harmonic potential well according to embodiments. The model 600 can include a differential transistor pair including transistors 602 and 604 (e.g., NMOS transistors). The source of transistor 602 can be coupled to the source of transistor 604. The model 600 can include a current source 606 coupled between ground 34 and the sources of transistors 602 and 604. The drain of transistor 602 can be coupled to node 46, and the drain of transistor 604 can be coupled to node 48. The current source 602 can supply a current IDC, which can be the sum of the currents supplied by current sources 401...404. The differential transistor pair can receive a differential signal pair represented by Vd*cos(coot) (positive signal) and -Vd*cos(coot) (negative signal). The positive signal can be coupled to the gate of transistor 602, and the negative signal can be coupled to the gate of transistor 604.

[0059] The load circuit 36 can include a capacitor 80, resistors 82, 84, and 88, and an inductor 86. The capacitor 80 can be coupled between nodes 46 and 48. The resistors 82 and 84 can be coupled in series between nodes 46 and 48. The inductor 86 can be coupled between nodes 46 and 48. The resistor 88 can be coupled between a supply voltage (VDD) and node 60. Node 60 can include the junction between resistors 82 and 84 and the center terminal of inductor 86. The center terminal of the inductor can be the point at which the inductance is divided in half. Thus, the center terminal at node 60 creates an inductor 861 between node 60 and node 46 and an inductor 862 between node 60 and node 48. If the inductor 86 has an inductance L, then each of inductors 861 and 862 can have an inductance L / 2. Each resistor 82 and 84 can have a resistance R / 2. The resistor 88 can have a resistance RCM. In some embodiments, the capacitor 80 can be a discrete capacitor. In other embodiments, the capacitor 80 can represent the parasitic capacitance seen from the drains of the differential transistor pair. In some embodiments, the resistors 82 and 84 can be the parasitic resistances of inductors 861 and 862, respectively.

[0060] As Figure 6As shown, the PI core 300 can be modeled by a differential pair of transistors in large signal operation. Common mode (CM) harmonic currents can be generated at both the tail node (e.g., the source of the differential pair of transistors) and the output drain node. The CM harmonic currents can cause a CM voltage swing at the output after passing through the resistor 88. With the presence of a common mode voltage offset resistance at the output (e.g., the resistor 88), the amplitude of the second harmonic voltage is further increased. In typical implementations, RCM can be large enough to be the dominant contributor to the output second harmonic voltage. Consider the effect of the input clock amplitude on the PI core output waveform. A larger input amplitude can increase the CM swing by introducing larger even harmonic currents due to transistor operation (e.g., switching between the saturation region and the triode region). Large CM variations can worsen the output duty cycle. The presence of mismatches / unbalances in the input clock can further increase the value of the second harmonic.

[0061] In some embodiments, a harmonic potential well 30 can be coupled between the node 60 and the ground 38. The harmonic potential well can be a circuit that provides a low impedance path for an AC signal of a selected frequency, where the AC signal can be a harmonic of the fundamental signal. The harmonic potential well 30 can be tuned to the second harmonic frequency 2ω0. The harmonic mitigation method can significantly improve the PI core output duty cycle and compensate for the DCD. The harmonic mitigation method can remove the need for an error amplifier based DCC circuit for each output clock signal. Eliminating the error amplifier based DCC circuit can eliminate the noise amplification and residual duty cycle error from the error amplifier input mismatches. Further, in some embodiments, the harmonic potential well 30 can be a network of passive components. Thus, the harmonic mitigation can be achieved without introducing additional power consumption and with little impact on circuit area. The harmonic potential well 30 can provide a low impedance in the CM path at the second harmonic frequency. The least intrusive location to capture the second harmonic current can be at the node 60. The harmonic potential well 30 can include a DC block so that the voltage supply (VDD) or the ground 34 can be used as an AC ground based on physical proximity. Various embodiments of the harmonic potential well 30 are described below.

[0062] Figure 7Ais a schematic diagram depicting a harmonic potential well 30 according to some embodiments. The harmonic potential well 30 can include a capacitor 62. An inductor 64 in series with the capacitor 62 can model the parasitic inductance of the terminals of the capacitor 62. Thus, in some embodiments, the harmonic potential well 30 can be a shunt capacitor. The capacitance of the capacitor 62 can be set to increase the low impedance path at a phase offset of -90° at 2ω0. The capacitor 62 can absorb the second harmonic current and minimize the second harmonic current at the output of the PI core. The capacitor 62 can have no impact on the differential swing at the output. The parasitic inductance inductor 64 of the capacitor 62 can determine its self-resonant frequency (SRF). At the operating frequency, the capacitor 62 can operate below its SRF. The parasitic inductance is omitted from the subsequent figures and description for clarity.

[0063] Figure 7B is a side view of an IC 11 according to some embodiments. The IC 11 can include a conductive interconnect 704 disposed on a semiconductor substrate 702. Circuitry of the IC 11 can be formed in the semiconductor substrate 702 and the conductive interconnect 704. The conductive interconnect 704 can include layers 706 and 708. The layers 706 can be patterned metal to form conductors. The layers 708 can be dielectric material. Vias (not shown) can be formed in the layers 708 to implement interlayer electrical connections between conductors on different layers 706. The load circuit 36 and the harmonic potential well 30 can be formed in the conductive interconnect 704 using one or more layers 706.

[0064] Figure 7C is a hybrid physical layout and schematic diagram of the load circuit 36 and the harmonic potential well 30 according to some embodiments. The physical layout of the inductor 86 in the load circuit 36 is shown from a top-down perspective. The inductor 86 can be formed using one or more layers 706 of the conductive interconnect 704. In some embodiments, the inductor 86 can be implemented as a two-turn inductor structure with a center terminal. The inductor 86 can include a coil 716 with two end terminals 710, 712 and a center terminal 714. The end terminals 710, 712 of the coil 714 can be coupled to the nodes 46 and 48 of the output of the PI core, respectively. The center terminal 714 can be coupled to the node 60 of the load circuit 36. The coil 716 can be symmetric about a vertical center line 705. The coil 716 can include a center region 700 that is free of any conductors of the coil 716. The vertical center line 705 can divide the center region 700 into two halves, a left and a right portion. A horizontal center line 703 can divide the center region 700 into two halves, a top and a bottom portion. The coil 716, the center terminal 714, and the end terminals 710, 712 of the inductor 86 are electrically connected and represent one continuous region or segment of conductive material. The coil 716 can be implemented within one or more layers 706 of the conductive interconnect of the IC 704.

[0065] In an embodiment, the coil 716 of the inductor 86 can be implemented as a symmetric two-turn rectangular coil. In other embodiments, the coil 716 of the inductor 86 can include more than two turns. In other embodiments, the coil 716 of the inductor 86 can have other shapes than rectangular that the IC fabrication process allows. Thus, the inductor 86 is shown as an implementation of a two-turn rectangular coil for the purposes of clarity and description, and it is not intended to be limiting.

[0066] The coil 716 of the inductor 86 can be surrounded by a shield 66. The shield 66 can be coupled to a ground (e.g., the ground 34). The shield 66 can be formed on the same layer 706 of the conductive interconnect 704 as the coil 716 or on a different layer 706. Although shown as a continuous rectangle, the shield 66 can have other shapes, including other shapes that conform to the shape of the coil 716. Additionally, the shield 66 can have discontinuities in continuity such that the shield 66 is not a continuous ring.

[0067] As illustratively shown, the capacitor 62 of the harmonic potential well 30 can be coupled between the node 60 (e.g., the center terminal 714) and the ground 38 (e.g., the AC ground). The resistor 88 can be coupled between the node 60 (the center terminal 714) and the supply voltage (VDD). Embodiments of physical implementations of the capacitor 62 are described below.

[0068] Figure 7D is a mixed physical layout and schematic of the load circuits 36I and 36Q of the PI 22 and the harmonic potential wells 30I and 30Q according to some embodiments. The elements of the load circuits 36I and 36Q and the harmonic potential wells 30I and 30Q are distinguished from the load circuits 36 and the harmonic potential well 30 with the same reference numbers, plus “I” and “Q” for the PI core 241 (I PI core) and the PI core 242 (Q PI core). The designation “I” in the reference symbol indicates that the element is part of the PI core 241. The designation “Q” in the reference symbol indicates that the element is part of the PI core 242.

[0069] The load circuit 36I can include an inductor 86I and the load circuit 36Q can include an inductor 86Q. Each of the load circuits 36I and 36Q can be implemented as shown in Figure 6 Figure 6 and 7C ​Inductor 86I in FIG. 6A and inductor 86Q in FIG. 6B are typically implemented. Coil 716I of inductor 86I can have a center region 700I. Coil 716I can be symmetric about a vertical center line 705I. Coil 716Q of inductor 86Q can have a center region 700Q. Coil 716Q can be symmetric about a vertical center line 706Q. Coils 716I, 716Q can be disposed adjacent to each other and can be formed using the same layer 706 or different layers 706 of electrically conductive interconnect 704. Shield 66I can surround coil 716I. Shield 66Q can surround coil 716Q. In some embodiments, shields 66I and 66Q can share a common side between coils 716I and 716Q. Shields 66I, 66Q can be coupled to ground 36. Resistors 68I and 66Q can model the resistance (Rshield) of the connection between shields 66I and 66Q and ground 34. Center regions 700I and 700Q can be divided in half by center line 703. Harmonic well 301 includes capacitor 62I and harmonic well 30Q includes capacitor 62Q. Capacitor 62I is coupled between center terminal 714I and shield 66I. Capacitor 62Q is coupled between center terminal 714Q and shield 66Q. Shields 66I and 66Q can act as AC ground 38.

[0070] Because the I / Q phase difference of the clock signal is 90°, the I / Q phase difference of the second harmonic current is 180°. The anti-correlation of the second harmonic currents in PI core 241 and PI core 242 can allow shields 66I, 66Q to act as a virtual ground for the second harmonic current (e.g., the ground is virtual because Rshield exists between shields 66I, 66Q and ground 34). Shields 66I, 66Q can be a self-contained system for the second harmonic current. Capacitor 62I can conduct second harmonic current IH2 from center terminal 714I toward shield 66I and capacitor 62Q can conduct second harmonic current IH2 from shield 66Q toward center terminal 714Q. The net current from shields 66I, 66Q through Rshield to ground 34 can be zero or close to zero.

[0071] Figure 8A is a mixed physical layout and schematic of load circuits 36I and 36Q and harmonic wells 301 and 30Q of PI 22 according to other embodiments. Like Figure 7D Elements of FIG. 6A that are the same or similar Figure 8A Elements of FIG. 6A that are the same or similar Figure 8A and Figure 7DThe difference between the embodiments in FIGS. 6A and 6B is that the capacitors 621 and 62Q can be divided in half. That is, the capacitor 621 can be divided into capacitors 6211 and 6212, each having the same capacitance (e.g., half the capacitance of the capacitor 621). Likewise, the capacitor 62Q can be divided into capacitors 62Q1 and 62Q2, each having the same capacitance. The capacitor 6211 can be coupled between the center terminal 7141 and the shield 661, and can conduct a current of 0.5*IH2from the center terminal 7141 toward the shield 661. The capacitor 6212 can be coupled between the center terminal 7141 and the shield 661, and can conduct a current of 0.5*IH2from the center terminal 7141 toward the shield 661. The capacitors 6211 and 6212 can be coupled to different portions of the shield 661. Likewise, the capacitor 62Q1 can be coupled between the center terminal 714Q and the shield 66Q, and can conduct a current of 0.5*IH2from the shield 66Q toward the center terminal 714Q. The capacitor 62Q2 can be coupled between the center terminal 714Q and the shield 66Q, and can conduct a current of 0.5*IH2from the shield 66Q toward the center terminal 714Q. The capacitors 62Q1 and 62Q2 can be coupled to different portions of the shield 66Q.

[0072] Figure 8B is according to some embodiments Figure 8A A side view of the physical layout shown in FIG. 6A. The physical layout shows the conductive interconnect 704 of the IC 11 disposed on the substrate 702 of the IC 11 and looking in the direction 725 Figure 8A ) In the example, four layers of the conductive interconnect 704 are shown. The four layers can be any four layers of the multi-layer conductive interconnect, which can include more than four layers. The first layer includes the coils 7161, 716Q of the inductors 861, 86Q, respectively. The terminals 712Q, 714Q, 710Q, 7121, 7141, and 7101 are shown. A second layer below the first layer includes the shields 661, 66Q. A third layer below the second layer includes the first plates of each of the capacitors 6211, 6212, 62Q1, and 62Q2. The conductor 806Q can implement the first plate of each of the capacitors 62Q1 and 62Q2. Since the first plates of the capacitors 62Q1 and 62Q2 are electrically connected Figure 8A ), a single conductor 806Q can be used to implement both plates. Likewise, the conductor 8061 can implement the first plate of each of the capacitors 6211 and 6212. Since the first plates of the capacitors 6211 and 6212 are electrically connected Figure 8A), so a single conductor 8061 can be used to implement both plates. A fourth layer below the third layer includes a second plate of each of capacitors 6211, 6212, 62Q1, and 62Q2. Conductor 808Q1 can implement the second plate of capacitor 62Q1. Conductor 808Q2 can implement the second plate of capacitor 62Q2. Likewise, conductor 80811 can implement the second plate of capacitor 6211. Conductor 80812 can implement the second plate of capacitor 6212. One or more vias 804Q can electrically connect conductor 806Q and shield 66Q. One or more vias 8041 can electrically connect conductor 8061 and shield 661. One or more vias and conductors 810Q can electrically connect center terminal 714Q as well as conductors 802Q1 and 802Q2. One or more vias and conductors 8101 can electrically connect center terminal 7141 as well as conductors 80211 and 80212. Thus, capacitors 6211, 6212, 62Q1, and 62Q2 can be disposed below shield 66 to avoid the top-up area.

[0073] Figure 9A is a mixed physical layout and schematic of load circuits 36I and 36Q and harmonic potential wells 301 and 30Q of PI 22 according to other embodiments. Like Figure 7D elements of Figure 9A elements of Figure 9A are similarly described and denoted with like reference numbers. Inductors 861 and 86Q can exhibit minimum magnetic flux coupling at the center (e.g., the intersection of vertical centerline 7051 and horizontal centerline 703, and the intersection of vertical centerline 705Q and horizontal centerline 703) of regions 7011 and 700Q, respectively. In some embodiments, capacitors 621 can be disposed at or near the center of region 7011. Capacitors 62Q can be disposed at or near the center of region 700Q. This placement of capacitors 621 and 62Q can exhibit minimum interaction with inductors 861 and 86Q, respectively. To avoid any systematic errors and ensure symmetric differential operation, the connections of shields 661, 66Q to capacitors 621 and 62Q can be symmetric. In Figure 9A embodiments of Figure 9A , capacitors 621 can be coupled to a side of shield 661 that is perpendicular to vertical centerline 7051 and opposite the side closest to center terminal 7141. Likewise, capacitors 62Q can be coupled to a side of shield 66Q that is perpendicular to vertical centerline 705Q and opposite the side closest to center terminal 714Q.

[0074] Figure 9B is a mixed physical layout and schematic of load circuits 36I and 36Q and harmonic potential wells 301 and 30Q of PI 22 according to other embodiments. Figure 9B similar to Figure 9A , but with different implementations of the connections between capacitors 621 and 62Q and shield 66. InFigure 9B In embodiments of the 62I can be coupled to both sides of the shield 66I parallel to the vertical centerline 705I. The connection between the capacitor 62I and the shield 66I can be at or near the horizontal centerline 703. Likewise, the capacitor 62Q can be coupled to both sides of the shield 66Q parallel to the vertical centerline 705I. The connection between the capacitor 62I and the shield 66Q can be at or near the horizontal centerline 703.

[0075] Figure 10A is a schematic diagram depicting a harmonic potential well 30 according to other embodiments. The harmonic potential well 30 can include a capacitor 70 in series with an inductor 72 (e.g., an LC tank). Unlike the Figure 7A Unlike embodiments of the 62, this embodiment can employ an explicit inductor in series with the capacitor. The addition of the inductor 72 can add an additional degree of freedom to select the capacitor 70 independent of the parasitic lead inductance of the capacitor 70. Thus, the capacitor 70 can have a smaller capacitance than the capacitor 62. In some embodiments, the capacitor 70 can be programmable to achieve second harmonic tuning over a range of frequencies. The LC tank of the capacitor 70 and the inductor 72 can be set to increase a low impedance path at a frequency of 2ω0with a phase offset of 0°. The LC tank can absorb the second harmonic current and minimize the second harmonic current at the output of the PI core. The LC tank can have no impact on the differential swing at the output.

[0076] Figure 10B is a mixed physical layout and schematic diagram of the load circuit 36 and the harmonic potential well 30 according to other embodiments. Except to show the placement of the LC tank, Figure 7C elements of the Figure 10B elements of the Figure 7C embodiments of the Figure 10B embodiments of the Figure 10B LC tank including the capacitor 70 and the inductor 72. Otherwise, Figure 7C the description of the Figure 10B .

[0077] Figure 11A is a mixed physical layout and schematic diagram of the load circuit 36 and the harmonic potential well 30 according to other embodiments. Except to show the placement of the LC tank, Figure 11A similar to Figure 10BIn some embodiments, the LC tank of harmonic potential well 30 can be located at or near the center of center region 700 (e.g., at or near the intersection of vertical centerline 705 and horizontal centerline 703). Inductor 72 can be divided into two halves, e.g., inductor 721 and inductor 722. Capacitor 70 can be coupled in series with inductors 721 and 722. The LC tank can be coupled to shield 66, e.g., the side of shield 66 that is perpendicular to vertical centerline 705 and opposite the side closest to center terminal 714.

[0078] Figure 11B is a mixed physical layout and schematic of load circuits 36I and 36Q and harmonic potential wells 30I and 30Q of PI 22 according to other embodiments. As with Figure 9A elements of Figure 11B elements of

[0079] Figure 12 is a mixed physical layout and schematic of load circuits 36I and 36Q and harmonic potential wells 30I and 30Q of PI 22 according to other embodiments. As with Figure 11B elements of Figure 12 elements of Figure 12In an embodiment of the application, the 8-shaped pattern of inductors 72I and 72Q can be replaced with odd number of turns. Capacitor 70I can be coupled to the center of the odd number of turns of inductor 72I. Capacitor 70Q can be coupled to the center of the odd number of turns of inductor 72Q.

[0080] While certain processes and methods have been described as having various sequential stages, one or more embodiments can also involve apparatuses or devices for performing these processes or methods. The devices can be specially constructed for the required purposes, or they can be a general purpose computer selectively activated or configured by a computer program stored in the computer. Various general purpose machines can be used with computer programs written in accordance with the teachings of this document, or it can be more convenient to construct more specialized apparatuses to perform the required processes.

[0081] As used herein, the phrase "at least one of" following with a series of items (where the terms "and" or "or" are used to separate items in the list) modifies the entire list of items as opposed to each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each listed item; rather, the phrase allows for the inclusion of at least one of any one of the items, and / or at least one of any combination of the items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refer to only A, only B, or only C; and / or any combination of A, B, and C. In instances where "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended, this is explicitly described.

[0082] It should be understood that, although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present disclosure.

[0083] As used herein, the term "coupled" and its derivatives refer both to direct and indirect connections, unless specifically described as being "directly coupled."

[0084] While one or more embodiments of the application have been described with a certain degree of particularity, certain changes can be made within the scope of the claims. It is noted that the described embodiments are to be considered merely illustrative and not restrictive, and that the scope of the claims is not to be limited to the details given herein, but can be modified within the scope and equivalents of the claims. In the claims, means-plus-function clauses, if used, are intended to cover the structures described herein as performing the recited function and not only structural equivalents.

[0085] The boundaries of the components, operations, and data stores are somewhat arbitrary, and particular operations are stated in the context of specific illustrative configurations. Other allocations of functionality are envisioned and can fall within the scope of the application. In general, structures and functionality presented as separate components in the exemplary configurations can be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component can be implemented as separate components. These and other variations, modifications, additions, and improvements can fall within the scope of the appended claims.

Claims

1. A phase interpolator in an integrated circuit (IC), comprising: A first circuit includes a transistor pair and a current source. The transistor pair includes a first transistor coupled between a first node and the current source, and a second transistor coupled between a second node and the current source. The gate of the first transistor is configured to receive a first clock signal, and the gate of the second transistor is configured to receive a second clock signal that is inversely related to the first clock signal. A load circuit comprising a first inductor coupled between the first node and the second node and a resistor coupled between a voltage source and the center terminal of the first inductor; and A second circuit is coupled between the center terminal of the first inductor and the AC ground, and the second circuit is tuned to conduct the second harmonic of the first clock signal.

2. The phase interpolator according to claim 1, further comprising: A shielding element surrounding the first inductor; The second circuit is coupled between the center terminal of the first inductor and the shield.

3. The phase interpolator of claim 2, wherein the second circuit includes a capacitor.

4. The phase interpolator of claim 3, wherein the first inductor is disposed on a first layer of the conductive interconnect of the IC, and wherein the capacitor is disposed on a second layer of the conductive interconnect, the second layer being above or below the first layer.

5. The phase interpolator of claim 3, wherein the first inductor includes a coil in a conductive interconnect of the IC, and wherein the capacitor is disposed in a region inside the coil within the conductive interconnect.

6. The phase interpolator of claim 2, wherein the second circuit includes a capacitor connected in series with the second inductor, the series coupling of the capacitor and the second inductor being between the center terminal of the first inductor and the shield.

7. The phase interpolator of claim 6, wherein the first inductor comprises a coil in a conductive interconnect of the IC, and wherein the capacitor and the second inductor are disposed in a region inside the coil in the conductive interconnect.

8. A phase interpolator in an integrated circuit (IC), comprising: First current source and second current source; A first transistor pair, comprising a first transistor coupled between a first node and the first current source, and A second transistor coupled between a second node and a first current source, the first transistor being configured to output a first clock signal at the first node and a second clock signal at the second node, the second clock signal being inverted from the first clock signal; The second transistor pair includes a third transistor coupled between the third node and the second current source, and A fourth transistor is coupled between the fourth node and the second current source, the second transistor being configured to output a third clock signal orthogonal to the first clock signal at the third node and a fourth clock signal at the fourth node, the fourth clock signal being inversely phase with the third clock signal; A first inductor is coupled between the first and second nodes; and a second inductor, which is coupled between the third and fourth nodes; A first resistor coupled between a voltage source and the center terminal of the first inductor; and a second resistor coupled between the voltage source and the center terminal of the second inductor; A first network is coupled between the center terminal of the first inductor and the AC ground; and A second network is coupled between the center terminal of the second inductor and the AC ground.

9. The phase interpolator of claim 8, further comprising: A shielding element surrounding the first inductor and the second inductor; The AC grounding is the shielding component.

10. The phase interpolator of claim 9, wherein the first network includes a first capacitor and the second network includes a second capacitor.

11. The phase interpolator of claim 10, wherein the first inductor and the second inductor are disposed on a first layer of conductive interconnects of the IC, and wherein the first capacitor and the second capacitor are disposed on a second layer of conductive interconnects, the second layer being above or below the first layer.

12. The phase interpolator of claim 10, wherein the first inductor includes a first coil in a conductive interconnect of the IC, wherein the second inductor includes a second coil in the conductive interconnect, wherein the first capacitor is disposed in a region inside the first coil in the conductive interconnect, and wherein the second capacitor is disposed in a region inside the second coil in the conductive interconnect.

13. The phase interpolator of claim 9, wherein the first network includes a first capacitor connected in series with a third inductor, the series coupling of the first capacitor and the third inductor being between the center terminal of the first inductor and the shield, and wherein the second network includes a second capacitor connected in series with a fourth inductor, the series coupling of the second capacitor and the fourth inductor being between the center terminal of the second inductor and the shield.

14. The phase interpolator of claim 13, wherein the first inductor includes a first coil in a conductive interconnect of the IC, wherein the second inductor includes a second coil in a conductive interconnect of the IC, wherein the first capacitor and the third inductor are disposed in a region inside the first coil in the conductive interconnect, and wherein the second capacitor and the fourth inductor are disposed in a region inside the second coil in the conductive interconnect.

15. The phase interpolator of claim 14, wherein each of the third inductor and the fourth inductor comprises a figure-eight coil.

16. A clock distribution circuit in an integrated circuit (IC), comprising: A phase interpolator, comprising: A first circuit includes a transistor pair and a current source. The transistor pair includes a first transistor coupled between a first node and the current source, and a second transistor coupled between a second node and the current source. The gate of the first transistor is configured to receive a first clock signal, and the gate of the second transistor is configured to receive a second clock signal that is inversely related to the first clock signal. A load circuit comprising a first inductor coupled between the first node and the second node, and a first resistor coupled between a voltage source and the center terminal of the first inductor; and A second circuit is coupled between the center terminal of the first inductor and the AC ground, and the second circuit is tuned to conduct the second harmonic of the first clock signal. A third circuit, coupled to the first node, includes a first series of inverters, a second resistor coupled between the input and output of the first inverter in the first series; and A fourth circuit, coupled to the second node, includes a second series of inverters and a third resistor coupled between the input and output of the second inverters in the second series.

17. The clock distribution circuit of claim 16, further comprising: A shielding element surrounding the first inductor; The second circuit is coupled between the center terminal of the first inductor and the shield.

18. The clock distribution circuit of claim 17, wherein the second circuit includes a capacitor.

19. The clock distribution circuit of claim 17, wherein the second circuit includes a capacitor connected in series with the second inductor, the series coupling of the capacitor and the second inductor being between the center terminal of the first inductor and the shield.

20. The clock distribution circuit of claim 16, further comprising a clock generator configured to supply the first clock signal and the second clock signal.

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