Caching method and device, equipment, storage medium, program product and chip

Abstract

The invention relates to a caching method and device, equipment, a storage medium, a program product and a chip. The method comprises the steps that cache configuration information of reference image block data is acquired, the reference image block data is used for motion compensation of an image frame of a video in the encoding and decoding process, and the cache configuration information comprises at least one kind of video type information; target capacity information of the data storage unit is determined according to the at least one type of video type information, the target capacity information is information of a storage space of the data storage unit, and the storage space is matched with the at least one type of video type information; and caching the reference image block data into a data storage unit. By adopting the method, the video coding and decoding performance can be improved.

Description

Technical Field

[0001] This application relates to the field of video encoding and decoding technology, and in particular to a caching method, apparatus, device, storage medium, program product, and chip. Background Technology

[0002] Currently, during video encoding and decoding, reference image block data can be cached in a specific data storage unit. This data storage unit can then be accessed during encoding and decoding to retrieve the corresponding reference image block data. If the corresponding reference image block data is not present in the data storage unit, it is then retrieved from memory.

[0003] In related technologies, the data storage unit for caching reference image block data typically uses a fixed-size memory space, for example, configuring the data storage unit to be 32 kilobytes (KB), so that the data storage unit can store reference image block data with a pixel width of 256 pixels, a height of 128 bits, and a depth of 8 bits.

[0004] However, using fixed-size data storage units to cache reference image block data can negatively impact video encoding and decoding performance. Summary of the Invention

[0005] Therefore, it is necessary to provide a caching method, apparatus, device, storage medium, program product, and chip that can improve video encoding and decoding performance in response to the above-mentioned technical problems.

[0006] Firstly, this application provides a caching method, including:

[0007] Obtain cache configuration information for reference image block data, wherein the reference image block data is used for motion compensation of video image frames during encoding and decoding, and the cache configuration information includes at least one video type information;

[0008] Based on the at least one video type information, the target capacity information of the data storage unit is determined, wherein the target capacity information is the storage space information of the data storage unit, and the storage space matches the at least one video type information;

[0009] The reference image block data is cached in the data storage unit.

[0010] In one embodiment, the target capacity information includes the storage space size information and / or storage space allocation information of the data storage unit.

[0011] This embodiment allows for the configuration of the storage space of the data storage unit from the perspective of size and the allocation method of pixel data in each channel, thereby enabling the data storage unit to meet the size and allocation requirements of different video types and improving video encoding and decoding performance.

[0012] In one embodiment, the video type information includes video standard type information, video transmission type information, and video data sampling type information.

[0013] This embodiment enables the caching configuration of reference image block data adapted to view frames of different video standard types, video transmission types, and data sampling types.

[0014] In one embodiment, when the cache configuration information includes the video standard type information and the video transmission type information; determining the target capacity information of the data storage unit based on the at least one video type information includes:

[0015] Based on the video standard type information, the size information of the macroblock is determined, wherein the macroblock is the encoding and decoding unit of the image frame in the video corresponding to the video standard type information;

[0016] Based on the video transmission type information, determine the amount of data transmitted in a single transmission instruction;

[0017] Based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock, the storage space size information of the data storage unit is determined.

[0018] This embodiment combines the size of the macroblock and the amount of data transmitted in a single transmission instruction to determine the storage space size, thereby enabling the configured storage space to improve both cache hit rate and data transmission efficiency.

[0019] In one embodiment, the video transmission type information includes bus width information and bus transmission length information. The step of determining the amount of data transmitted per transmission command in a single operation based on the video transmission type information includes:

[0020] Based on the bus width information and the bus transmission length information, the amount of data transmitted in a single transmission command is determined.

[0021] This embodiment takes into account not only the impact of bus width on data transmission, but also the impact of bus transmission length on data transmission, thereby making the accuracy of the amount of data transmitted in a single transmission command more precise.

[0022] In one embodiment, determining the storage space size information of the data storage unit based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock includes:

[0023] Based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock, at least one candidate storage space information for the data storage unit is determined;

[0024] Determine the cache hit rate corresponding to at least one candidate storage space information of the data storage unit;

[0025] Based on the cache hit rate corresponding to the at least one candidate storage space information, determine the average access time corresponding to the at least one candidate storage space information.

[0026] The storage space size information of the data storage unit is determined based on the average access time corresponding to the at least one candidate storage space information.

[0027] In this embodiment, the average access time of at least one candidate storage space information is determined based on the cache hit rate, and the storage space size information is determined from the at least one candidate storage space information based on the average access time, so that the average access time of the storage space configured with the storage space size information is minimized.

[0028] In one embodiment, determining the cache hit rate corresponding to at least one candidate storage space information of the data storage unit includes:

[0029] The ratio of the macroblock size information to the at least one candidate storage space information is determined as the hit rate of a single data storage unit corresponding to the at least one candidate storage space information.

[0030] Based on the hit rate of the individual data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame, the cache hit rate corresponding to at least one candidate storage space information of the data storage unit is determined.

[0031] This embodiment achieves a higher cache hit rate by combining the hit rate of a single data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame when determining the cache hit rate.

[0032] In one embodiment, when the cache configuration information includes the video data sampling type information, determining the target capacity information of the data storage unit based on the at least one video type information includes:

[0033] Based on the video data sampling type information, determine the sampling ratio of the pixel data corresponding to the luminance channel and chrominance channel respectively;

[0034] Based on the sampling ratio of the pixel data corresponding to the luminance channel and the chrominance channel, the storage space allocation information of the data storage unit is determined.

[0035] This embodiment determines the storage space allocation information of the data storage unit according to the sampling ratio corresponding to the video data sampling type, so that the storage space configured by the storage space allocation information can store the pixel data of each channel in an appropriate ratio without wasting storage space.

[0036] Secondly, this application provides a caching device, comprising:

[0037] The acquisition module is used to acquire cache configuration information of reference image block data, wherein the reference image block data is used for motion compensation of image frames in the video during the encoding and decoding process, and the cache configuration information includes at least one video type information;

[0038] A capacity determination module is used to determine the target capacity information of a data storage unit based on the at least one video type information, wherein the target capacity information is the storage space information of the data storage unit, and the storage space matches the at least one video type information;

[0039] A caching module is used to cache the reference image block data into the data storage unit.

[0040] In one embodiment, the target capacity information includes the storage space size information and / or storage space allocation information of the data storage unit.

[0041] In one embodiment, the video type information includes video standard type information, video transmission type information, and video data sampling type information.

[0042] In one embodiment, when the cache configuration information includes the video standard type information and the video transmission type information, the capacity determination module is further configured to determine the macroblock size information based on the video standard type information, wherein the macroblock is the encoding / decoding unit of the image frame in the video corresponding to the video standard type information; determine the amount of data transmitted per transmission instruction based on the video transmission type information; and determine the storage space size information of the data storage unit based on the amount of data transmitted per transmission instruction and the macroblock size information.

[0043] In one embodiment, the video transmission type information includes bus width information and bus transmission length information. The capacity determination module is further configured to determine the amount of data transmitted in a single transmission instruction based on the bus width information and the bus transmission length information.

[0044] In one embodiment, the capacity determination module is further configured to: determine at least one candidate storage space information of the data storage unit based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock; determine the cache hit rate corresponding to each of the at least one candidate storage space information of the data storage unit; determine the average access time corresponding to each of the at least one candidate storage space information based on the cache hit rate corresponding to each of the at least one candidate storage space information; and determine the storage space size information of the data storage unit based on the average access time corresponding to each of the at least one candidate storage space information.

[0045] In one embodiment, the capacity determination module is further configured to determine the ratio of the macroblock size information to the at least one candidate storage space information as the hit rate of a single data storage unit corresponding to the at least one candidate storage space information; and to determine the cache hit rate corresponding to the at least one candidate storage space information of the data storage unit based on the hit rate of the single data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame.

[0046] In one embodiment, when the cache configuration information includes the video data sampling type information, the capacity determination module is further configured to determine the sampling ratio of pixel data corresponding to the luminance channel and the chroma channel respectively based on the video data sampling type information; and determine the storage space allocation information of the data storage unit based on the sampling ratio of pixel data corresponding to the luminance channel and the chroma channel respectively.

[0047] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the caching method of the first aspect described above.

[0048] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the caching method of the first aspect described above.

[0049] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the caching method of the first aspect described above.

[0050] In a sixth aspect, this application also provides a chip including a processor coupled to a memory for executing a computer program or instructions stored in the memory, wherein when the processor executes the computer program or instructions, the caching method of the first aspect described above is executed.

[0051] The aforementioned caching method, apparatus, device, storage medium, program product, and chip acquire caching configuration information for reference image block data. This reference image block data is used for motion compensation of video image frames during encoding and decoding. The caching configuration information includes at least one video type. Based on this at least one video type, the target capacity information of the data storage unit is determined. This target capacity information represents the storage space of the data storage unit, and the storage space matches the at least one video type. The reference image block data is then cached in the data storage unit. Because the target capacity information of the data storage unit is determined based on different video type information, the target capacity information is matched to different types of video, thereby improving video encoding and decoding performance. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A flowchart illustrating a caching method provided in an embodiment of this application;

[0054] Figure 2 This application provides a schematic diagram of the partitioning of image block data;

[0055] Figure 3 This is a schematic diagram illustrating another method for dividing image block data according to an embodiment of this application;

[0056] Figure 4 A flowchart illustrating another caching method provided in an embodiment of this application;

[0057] Figure 5 A flowchart illustrating another caching method provided in an embodiment of this application;

[0058] Figure 6 A structural block diagram of a caching device provided in an embodiment of this application;

[0059] Figure 7 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] In the video encoding and decoding process, using fixed-size data storage units to cache reference image block data may result in different efficiency in the use of data storage units for different types of videos during encoding and decoding, thus affecting video encoding and decoding performance.

[0062] For example, different video standard types define different macroblock sizes. Using the same data storage unit for different macroblock sizes will cause a mismatch between storage space and bus, thereby reducing the performance of high-performance video encoding and decoding.

[0063] For example, the macroblock corresponding to the H.264 video standard is 16*16 pixels, while the macroblock corresponding to the H.265 video standard is 64*64 pixels. If a 16*16 pixel data storage unit is used, a larger number of data storage units will be needed to meet the data caching requirements of a single H.265 macroblock. If a 64*64 pixel data storage unit is used, it will result in a waste of storage space and bus space for the H.264 macroblock.

[0064] During video encoding and decoding, motion vectors can be used to describe the displacement parameters of a specific image block within the currently encoded image frame relative to a reference image block. Since the direction of motion of objects in a video is arbitrary, the motion vector is also arbitrary and can point to any position within the reference image block. Therefore, accessing the reference image block data in the data storage unit is not a sequential traversal, but rather a random access.

[0065] Since caching is originally based on spatial and temporal locality, random access to reference image blocks in the data storage unit disrupts spatial locality. Furthermore, the data stream of reference image blocks is often quite large; a single frame of 1080p resolution (p) YUV420 image occupies approximately 3 megabytes (MB) of memory, and a reference image block often exists across 4 to 8 frames. When the decoder jumps between different reference frames and between different positions within the same reference frame, older data in the cache is quickly overwritten by newer data, resulting in poor temporal locality. Therefore, due to poor spatial and temporal locality, access to reference image block data in the data storage unit results in a low cache hit rate.

[0066] Furthermore, to achieve higher prediction accuracy, the codec uses fractional-pixel precision motion compensation, which means the motion vector may not point to a specific integer pixel. During decoding, the decoder needs to access multiple integer pixels surrounding the fractional pixel pointed to by the motion vector, and then use filtering to calculate the difference between these integer and integer pixels. For example, calculating a 1 / 4 pixel requires accessing a 6x6 array of integer pixels surrounding that 1 / 4 pixel. This additional access due to interpolation filtering amplifies the memory range required for a single motion compensation operation, further reducing cache hit rate.

[0067] The cache hit rate of a data storage unit is related to both the size of the data storage unit and the macroblock size. Using the same data storage unit for different macroblock sizes leads to a lower cache hit rate, which in turn reduces the performance of high-performance video encoding and decoding.

[0068] For example, video data sampling types may include YUV420, YUV422, YUV444, etc. The ratio of pixel data in the Y, U, and V channels is different in different sampling types. Therefore, using a fixed-size data storage unit will affect the utilization efficiency of pixel data in the Y, U, and V channels.

[0069] For example, different chips transmit video of different types. Using a fixed-size data storage unit will affect the bus efficiency of different chips, and thus affect the video encoding and decoding performance. For instance, large System-on-a-Chip (SOC) chips have a large total throughput and read a large amount of data per command (256-bit bus width, 8-burst length), while small SOC chips have a small total throughput and read a small amount of data per command (128-bit bus width, 4-burst length). Data storage units suitable for data transmission in small SOC chips are often unsuitable for data transmission in large SOC chips, thus affecting video encoding and decoding performance.

[0070] To address the aforementioned issues, embodiments of this application provide a caching method, apparatus, device, storage medium, program product, and chip. These methods determine the target capacity information of data storage units based on different video type information, thereby matching the target capacity information with different types of videos and ultimately improving video encoding / decoding performance.

[0071] The caching method provided in this application can be applied to a caching device, which can be a video codec chip or any device containing a video codec chip. For example, the caching device can be a graphics card, a graphics processing unit (GPU), a multimedia set-top box, etc.

[0072] In one exemplary embodiment, such as Figure 1 As shown, a caching method is provided. Taking the application of this method to the aforementioned video codec chip as an example, the caching method includes steps S101 to S103. Wherein:

[0073] S101. Obtain the cache configuration information of the reference image block data.

[0074] The reference image block data is used for motion compensation of video image frames during the encoding and decoding process.

[0075] In this application, the video encoding / decoding process requires caching reference image block data. This allows the video encoding / decoding chip to directly retrieve the reference image block data from the cached data storage unit during subsequent processing, eliminating the need for memory access and thus reducing bandwidth consumption and improving video encoding / decoding performance. Accordingly, to ensure the data storage unit matches the current reference image block data, the cache configuration information of the reference image block data can be obtained.

[0076] This application does not limit the cache configuration information. In some embodiments, the cache configuration information includes at least one video type information.

[0077] For example, video type information includes video standard type information, video transmission type information, and video data sampling type information. The video standard type information characterizes the video encoding / decoding standard and may include standards such as H.264 and H.265. The video transmission type information characterizes the bus information of the video codec chip and may include bus width and bus transmission length information. The sampling type information characterizes the video data sampling format; different data sampling formats have different proportions of luminance and chrominance data streams, and data sampling formats may include YUV444, YUV420, YUV422, etc.

[0078] This embodiment enables the implementation of buffer configurations adapted to view frames of different video standard types, video transmission types, and data sampling types.

[0079] This application does not limit how the cache configuration information for obtaining reference image block data is obtained. In some embodiments, the video codec chip can automatically identify any frame in the currently processed video to determine the video standard type information and video data sampling type information. Correspondingly, the video codec chip can also identify its own bus to determine the video transmission type information.

[0080] In other embodiments, the video codec chip may also be input or pre-configured by the user, thereby enabling the video codec chip to obtain cache configuration information from the user input or pre-configured information.

[0081] S102. Determine the target capacity information of the data storage unit based on at least one video type information.

[0082] In this step, after the video codec chip obtains the buffer configuration information of the reference image block data, it can determine the target capacity information of the data storage unit based on at least one video type information.

[0083] The target capacity information refers to the storage space information of the data storage unit, and the storage space is matched with at least one video type information.

[0084] For example, matching storage space with at least one type of video information can effectively improve cache hit rate, enabling reference image block data to be stably retained without frequent replacement; during motion compensation, there is no need to repeatedly retrieve the same reference image block data, which can effectively avoid the bus bandwidth being repeatedly occupied, reduce memory access latency caused by bus congestion, thereby optimizing the processing efficiency of motion compensation, and ultimately effectively guaranteeing and improving video encoding and decoding performance.

[0085] In some embodiments, the target capacity information includes storage space size information of the data storage unit and / or storage space allocation information.

[0086] The storage space size information indicates the size of the storage space in the data storage unit. The storage space allocation information indicates the proportion of pixel data for each channel (e.g., the luminance channel and the chroma channel) stored in the storage space of the data storage unit.

[0087] This embodiment allows for the configuration of the storage space of the data storage unit from the perspective of size and the allocation method of pixel data in each channel, thereby enabling the data storage unit to meet the size and allocation requirements of different video types and improving video encoding and decoding performance.

[0088] For example, different storage spaces may have different storage space size information and / or storage space allocation information. After the video codec chip obtains at least one video type information, it can match the at least one video type information with different configured storage spaces to determine the most suitable storage space for the at least one video type information (i.e., the storage space with the best video encoding performance). The size information and / or storage space allocation information of the most suitable storage space are then determined as the target capacity information of the data storage unit.

[0089] In the embodiments of this application, different cache configuration information can be used to determine the target capacity information of the data storage unit in different ways.

[0090] In some embodiments, when the cache configuration information includes video standard type information and video transmission type information, the video codec chip can determine the macroblock size information based on the video standard type information and the amount of data transmitted per transmission instruction based on the video transmission type information. The video codec chip can then determine the storage space size information of the data storage unit based on the amount of data transmitted per transmission instruction and the macroblock size information.

[0091] In this context, a macroblock is a codec unit for an image frame in a video that corresponds to the video standard type information. For example, a video codec chip divides an entire frame into multiple codec units of fixed size, each codec unit being a rectangular pixel block, and each rectangular pixel block being a macroblock.

[0092] For example, different video standard types correspond to different macroblock sizes. Therefore, by determining the video standard type information, the macroblock size information of the image frames in the encoded and decoded video can be determined. For instance, the macroblock size corresponding to the H.264 standard is 16*16 pixels, while the macroblock size corresponding to the H.265 standard is 32*32 pixels or 64*64 pixels.

[0093] This embodiment combines the size of the macroblock and the amount of data transmitted in a single transmission instruction to determine the storage space size, thereby enabling the configured storage space to improve both cache hit rate and data transmission efficiency.

[0094] This application's embodiments address how to determine the amount of data transmitted per transmission command in a single transmission based on video transmission type information. In some embodiments, the video transmission type information includes bus width information and bus transmission length information. Therefore, the amount of data transmitted per transmission command in a single transmission can be determined based on the bus width information and the bus transmission length information. This embodiment, by considering not only the impact of bus width on data transmission but also the impact of bus transmission length, achieves higher accuracy in determining the amount of data transmitted per transmission command in a single transmission.

[0095] In the example row, the bus width information is 64 bits, and the bus transmission length information is 4. Therefore, by multiplying the bus width and the burst length, we can obtain that the amount of data transmitted in a single transmission instruction is 32 bytes (B).

[0096] This application embodiment does not limit how the target capacity information of the data storage unit is determined based on the data volume and macroblock size information of each transmission command. In some embodiments, the video codec chip can first determine at least one candidate storage space information of the data storage unit based on the data volume and macroblock size information of each transmission command; determine the cache hit rate corresponding to each of the at least one candidate storage space information of the data storage unit; and determine the average access time corresponding to each of the at least one candidate storage space information based on the cache hit rate corresponding to each of the at least one candidate storage space information. The video codec chip determines the storage space size information of the data storage unit based on the average access time corresponding to each of the at least one candidate storage space information.

[0097] In this embodiment, the average access time of at least one candidate storage space information is determined based on the cache hit rate, and the storage space size information is determined from the at least one candidate storage space information based on the average access time, so that the average access time of the storage space configured with the storage space size information is minimized.

[0098] For example, a video codec chip can determine the storage space size information of a data storage unit based on the average access time corresponding to at least one candidate storage space information. This may include determining the candidate storage space information corresponding to the smallest average access time as the storage space size information of the data storage unit.

[0099] For example, if each transmission instruction transmits 32 bytes of data per transmission, the corresponding macroblock size is 16*16 pixels, and the pixel bit depth is 8 bits, then to improve read efficiency, the width of the data storage unit can be set to 32 pixels (each pixel is 1 byte of data) per transmission, and 32 pixels is an integer multiple of 16 pixels (the width of the macroblock). Based on the 32-pixel width of the data storage unit, at least one candidate storage space information for the data storage unit can be determined, such as 32*2 pixels, 32*4 pixels, 32*16 pixels, etc. Subsequently, by calculating the cache hit rate and average access time corresponding to the candidate storage space information, the target capacity information of the final data storage unit can be determined from at least one candidate storage space information.

[0100] In some embodiments, the video codec chip can determine the hit rate of a single data storage unit corresponding to each of the macroblock size information and at least one candidate storage space information by comparing the macroblock size information with at least one candidate storage space information. Subsequently, the video codec chip can determine the cache hit rate corresponding to each of the at least one candidate storage space information of the data storage unit based on the hit rate of the single data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame.

[0101] This embodiment achieves a higher cache hit rate by combining the hit rate of a single data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame when determining the cache hit rate.

[0102] For example, the number of data storage units is positively correlated with the cache hit rate, and it also affects the data access latency, which in turn affects the encoding and decoding performance. For example, formula (1) is the formula for calculating the hit rate of a single storage unit, formula (2) is the formula for calculating the cache hit rate, and formula (3) is the formula for calculating the average access time.

[0103] (1)

[0104] (2)

[0105] (3)

[0106] in, The hit rate for a single data storage unit. For macroblock size, Candidate capacity for data storage units. The number of data storage units used. This refers to the number of data storage units included in each image frame. The number of macroblocks included in each image frame. For cache hit rate, Average access time, For the time of hit, N represents the time of the miss. N (e.g., 2). and You can set it up according to the specific situation.

[0107] For example, the size of the macroblock corresponding to the H.264 standard is 16*16 pixels. If the candidate capacity of the data storage unit corresponding to the H.264 standard is 16*8 pixels, then according to formula (1), the hit rate R of a single data storage unit is 16*16 / (16*8*n)=100%, where n is 2, that is, the number of data storage units used is 2.

[0108] For example, the size of the macroblock corresponding to the H.264 standard is 16*16 pixels. If the candidate capacity of the data storage unit corresponding to the H.264 standard is 64*8 pixels, then according to formula (1), the hit rate R of a single data storage unit is 16*16 / (64*8*n)=25%, where n is 2, that is, the number of data storage units used is 2.

[0109] For example, the size of the macroblock corresponding to the H.264 standard is 16*16 pixels. If the candidate capacity of the data storage unit corresponding to the H.264 standard is 32*4 pixels, then according to formula (1), the hit rate R of a single data storage unit is 16*16 / (32*4*n)=100%, where n is 2, that is, the number of data storage units used is 2.

[0110] For example, without considering the hit rate of individual data storage units, the cache hit rate can be the ratio of the number of data storage units to the number of macroblocks. After considering the block size, the cache hit rate can be corrected by the hit rate of individual data storage units as shown in formula (2).

[0111] For example, if the candidate capacity is 32*4 pixels, each data storage unit can be read 4 times. Taking a reference image block data of 32KB (256*128 pixels, 8-bit depth) and a macroblock size of 16*16 pixels as an example, each image frame can be divided into 256 data storage units and 128 macroblocks. Substituting the macroblock size of 16*16 pixels and the candidate capacity of 32*4 pixels into formula (1), the hit rate R of a single storage unit can be calculated. Then, substituting the hit rate R of a single storage unit, the number of data storage units (256) included in each image frame, and the number of macroblocks (128) included in each image frame into formula (2), the cache hit rate HR can be calculated. Finally, substituting the cache hit rate and the number of macroblocks (128) included in each image frame into formula (3), the average access time can be calculated. Correspondingly, a similar method can be used to calculate the candidate storage space information corresponding to the minimum average access time for candidate capacity of 32*2 pixels and 32*16 pixels, and then configure it as the storage space size information of the data storage unit.

[0112] For example, Figure 2 This is a schematic diagram of the partitioning of image block data provided in an embodiment of this application, such as... Figure 2 As shown, the macroblock size corresponding to the H.264 standard is 16*16 pixels, and the storage space size of the determined data storage unit can be 32*4 pixels. Taking a reference image block data of 32KB (256*128 pixels 8-bit depth) as an example, it can be divided into 256 data storage units.

[0113] For example, Figure 3 This is a schematic diagram illustrating another method for dividing image patch data according to an embodiment of this application, such as... Figure 2As shown, the macroblock size corresponding to the H.265 standard is 32*32 or 64*64. The storage space size of the determined data storage unit can be 32*16 pixels. Taking a 32KB (256*128 pixels 8-bit depth) reference image block data as an example, it can be divided into 64 cache units.

[0114] In some embodiments, when the cache configuration information includes video data sampling type information, the video codec chip can determine the sampling ratio of the pixel data corresponding to the luminance channel and chrominance channel based on the video data sampling type information. Subsequently, the video codec chip can determine the storage space allocation information of the data storage unit based on the sampling ratio of the pixel data corresponding to the luminance channel and chrominance channel.

[0115] This embodiment determines the storage space allocation information of the data storage unit according to the sampling ratio corresponding to the video data sampling type, so that the storage space configured by the storage space allocation information can store the pixel data of each channel in an appropriate ratio without wasting storage space.

[0116] Among them, the sampling type information is used to characterize the data sampling format of the video. Different data sampling formats have different data stream ratios of luminance data and chrominance data. The data sampling format can include YUV444 format, YUV420, YUV422, etc.

[0117] For example, video data exists in three channels: YUV. The Y channel contains luminance data, while the U and V channels contain chrominance data. The proportions of luminance and chrominance data streams differ depending on the data sampling format. For instance, in the YUV420 data sampling format, the Y channel data is four times the amount of U and V channel data. Accordingly, if the total capacity of the data storage unit is 32KB*3, the storage space allocation information can be set so that the Y channel data uses 64KB of data storage unit, while the U and V channel data share the 32KB data storage unit.

[0118] For example, the Y-channel data corresponding to the YUV420 data sampling format is twice that of the U-channel and V-channel data. Accordingly, if the total capacity of the data storage unit is 32KB*2, the storage space allocation information can be set so that the Y-channel data uses 32KB of data storage unit, and the U-channel and V-channel data share the same 32KB of data storage unit.

[0119] For example, the YUV444 data sampling format corresponds to one time the total amount of Y-channel data, U-channel data, and V-channel data. Correspondingly, if the total capacity of the data storage unit is 32KB*3, the storage space allocation information can be set so that Y-channel data uses 32KB of data storage units, and U-channel and V-channel data each use 32KB of data storage units.

[0120] S103. Cache the reference image block data into the data storage unit.

[0121] In this step, once the target capacity information of the data storage unit is determined, the video codec chip can cache the reference image block data in the data storage unit so that the reference image block data can be read directly from the data storage unit during subsequent video encoding and decoding processes.

[0122] The caching method provided in this application embodiment obtains caching configuration information for reference image block data. The reference image block data is used for motion compensation of video image frames during encoding and decoding. The caching configuration information includes at least one video type information. Based on the at least one video type information, the target capacity information of the data storage unit is determined. The target capacity information is the storage space information of the data storage unit, and the storage space matches the at least one video type information. The reference image block data is then cached in the data storage unit. Because the target capacity information of the data storage unit is determined based on different video type information, the target capacity information is matched with different types of videos, saving storage resources and thus improving video encoding and decoding performance.

[0123] For example, a video codec chip can determine not only the storage space size information of the data storage unit, but also the storage space allocation information, without any restriction on the order in which they are determined. For example, a video codec chip can determine only the storage space size information of the data storage unit. For example, a video codec chip can also determine only the storage space allocation information.

[0124] In one exemplary embodiment, such as Figure 4 As shown, another caching method is provided. Taking the application of this method to the aforementioned video codec chip as an example, this caching method includes steps S201 to S208. Wherein:

[0125] S201. Obtain the cache configuration information of the reference image block data.

[0126] The reference image block data is used for motion compensation of video image frames during encoding and decoding. The buffer configuration information includes video standard type information and video transmission type information. The video transmission type information includes bus width information and bus transmission length information.

[0127] S202. Determine the macroblock size information of the target image frame based on the video standard type information.

[0128] Among them, a macroblock is the encoding and decoding unit of an image frame in a video that corresponds to the video standard type information.

[0129] S203. Determine the amount of data transmitted in a single transmission command based on the bus width information and bus transmission length information.

[0130] S204. Based on the amount of data transmitted in a single transmission instruction and the size of the macroblock, determine at least one candidate storage space information for the data storage unit.

[0131] S205. Determine the cache hit rate corresponding to at least one candidate storage space information of the data storage unit.

[0132] In some embodiments, the video codec chip can determine the hit rate of a single memory unit corresponding to each of the macroblock size information and at least one candidate memory space information by comparing the macroblock size information with at least one candidate memory space information. The video codec chip determines the cache hit rate corresponding to at least one candidate memory space information of the data storage unit based on the hit rate of a single memory unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame.

[0133] S206. Based on the cache hit rate corresponding to at least one candidate storage space information, determine the average access time corresponding to at least one candidate storage space information.

[0134] S207. Determine the storage space size information of the data storage unit based on the average access time corresponding to at least one candidate storage space information.

[0135] S208. Cache the reference image block data into the data storage unit.

[0136] In one exemplary embodiment, such as Figure 5 As shown, another caching method is provided. Taking the application of this method to the aforementioned video codec chip as an example, this caching method includes S301 to S304. Wherein:

[0137] S301. Obtain the cache configuration information of the reference image block data.

[0138] The reference image block data is used for motion compensation of video image frames during the encoding and decoding process, and the cache configuration information includes video data sampling type information.

[0139] S302. Based on the video data sampling type information, determine the sampling ratio of the pixel data corresponding to the luminance channel and chrominance channel respectively.

[0140] S303. Determine the storage space allocation information of the data storage unit based on the sampling ratio of the pixel data corresponding to the luminance channel and chrominance channel respectively.

[0141] S304. Cache the reference image block data into the data storage unit.

[0142] The caching method provided in this application embodiment obtains caching configuration information for reference image block data. The reference image block data is used for motion compensation of video image frames during encoding and decoding. The caching configuration information includes at least one video type information. Based on the at least one video type information, the target capacity information of the data storage unit is determined. The target capacity information is the storage space information of the data storage unit, and the storage space matches the at least one video type information. The reference image block data is then cached in the data storage unit. Because the target capacity information of the data storage unit is determined based on different video type information, the target capacity information is matched with different types of videos, thereby improving video encoding and decoding performance.

[0143] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0144] Based on the same inventive concept, this application also provides a caching device for implementing the caching method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more caching device embodiments provided below can be found in the limitations of the caching method described above, and will not be repeated here.

[0145] In one exemplary embodiment, such as Figure 6 As shown, a caching device 400 is provided, including: an acquisition module 401, a capacity determination module 402, and a transmission module 403, wherein:

[0146] The acquisition module 401 is used to acquire the cache configuration information of the reference image block data. The reference image block data is used for motion compensation of the image frames in the video during the encoding and decoding process. The cache configuration information includes at least one video type information.

[0147] The capacity determination module 402 is used to determine the target capacity information of the data storage unit based on at least one video type information. The target capacity information is the storage space information of the data storage unit, and the storage space matches at least one video type information.

[0148] The caching module 403 is used to cache reference image block data into the data storage unit.

[0149] In one embodiment, the target capacity information includes storage space size information of the data storage unit and / or storage space allocation information.

[0150] In one embodiment, the video type information includes video standard type information, video transmission type information, and video data sampling type information.

[0151] In one embodiment, when the cache configuration information includes video standard type information and video transmission type information, the capacity determination module 402 is further configured to determine the macroblock size information based on the video standard type information, wherein the macroblock is the encoding and decoding unit of the image frame in the video corresponding to the video standard type information; determine the amount of data transmitted per transmission instruction based on the video transmission type information; and determine the storage space size information of the data storage unit based on the amount of data transmitted per transmission instruction and the macroblock size information.

[0152] In one embodiment, the video transmission type information includes bus width information and bus transmission length information. The capacity determination module 402 is also used to determine the amount of data transmitted in a single transmission instruction based on the bus width information and bus transmission length information.

[0153] In one embodiment, the capacity determination module 402 is further configured to determine at least one candidate storage space information of the data storage unit based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock; determine the cache hit rate corresponding to each of the at least one candidate storage space information of the data storage unit; determine the average access time corresponding to each of the at least one candidate storage space information based on the cache hit rate corresponding to each of the at least one candidate storage space information; and determine the storage space size information of the data storage unit based on the average access time corresponding to each of the at least one candidate storage space information.

[0154] In one embodiment, the capacity determination module 402 is further configured to determine the ratio of the macroblock size information to at least one candidate storage space information as the hit rate of a single data storage unit corresponding to at least one candidate storage space information; and to determine the cache hit rate corresponding to at least one candidate storage space information of the data storage unit based on the hit rate of a single data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame.

[0155] In one embodiment, when the cache configuration information includes video data sampling type information, the capacity determination module 402 is further configured to determine the sampling ratio of pixel data corresponding to the luminance channel and chrominance channel respectively based on the video data sampling type information; and determine the storage space allocation information of the data storage unit based on the sampling ratio of pixel data corresponding to the luminance channel and chrominance channel respectively.

[0156] Each module in the aforementioned cache device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can invoke and execute the operations corresponding to each module.

[0157] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. The computer program is executed by the processor to implement a caching method.

[0158] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0159] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the caching method described above when executing the computer program.

[0160] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described caching method.

[0161] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described caching method.

[0162] In one embodiment, a chip is provided, including a processor coupled to a memory for executing a computer program or instructions stored in the memory, wherein, when the processor executes the computer program or instructions, the caching method described above is performed.

[0163] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0164] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0165] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application's patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A caching method, characterized in that, The method includes: Obtain cache configuration information for reference image block data, wherein the reference image block data is used for motion compensation of video image frames during encoding and decoding, and the cache configuration information includes at least one video type information; Based on the at least one video type information, the target capacity information of the data storage unit is determined, wherein the target capacity information is the storage space information of the data storage unit, and the storage space matches the at least one video type information; The reference image block data is cached in the data storage unit.

2. The method according to claim 1, characterized in that, The target capacity information includes the storage space size information and / or storage space allocation information of the data storage unit.

3. The method according to claim 2, characterized in that, The video type information includes video standard type information, video transmission type information, and video data sampling type information.

4. The method according to claim 3, characterized in that, When the cache configuration information includes the video standard type information and the video transmission type information; Determining the target capacity information of the data storage unit based on the at least one video type information includes: Based on the video standard type information, the size information of the macroblock is determined, wherein the macroblock is the encoding and decoding unit of the image frame in the video corresponding to the video standard type information; Based on the video transmission type information, determine the amount of data transmitted in a single transmission instruction; Based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock, the storage space size information of the data storage unit is determined.

5. The method according to claim 4, characterized in that, The video transmission type information includes bus width information and bus transmission length information. Determining the amount of data transmitted per transmission command based on the video transmission type information includes: Based on the bus width information and the bus transmission length information, the amount of data transmitted in a single transmission command is determined.

6. The method according to claim 4, characterized in that, The step of determining the storage space size information of the data storage unit based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock includes: Based on the amount of data transmitted in a single transmission instruction and the size information of the macroblock, at least one candidate storage space information for the data storage unit is determined; Determine the cache hit rate corresponding to at least one candidate storage space information of the data storage unit; Based on the cache hit rate corresponding to the at least one candidate storage space information, determine the average access time corresponding to the at least one candidate storage space information. The storage space size information of the data storage unit is determined based on the average access time corresponding to the at least one candidate storage space information.

7. The method according to claim 6, characterized in that, Determining the cache hit rate corresponding to at least one candidate storage space information of the data storage unit includes: The ratio of the macroblock size information to the at least one candidate storage space information is determined as the hit rate of a single data storage unit corresponding to the at least one candidate storage space information. Based on the hit rate of the individual data storage unit, the number of data storage units included in each image frame, and the number of macroblocks included in each image frame, the cache hit rate corresponding to at least one candidate storage space information of the data storage unit is determined.

8. The method according to any one of claims 3-7, characterized in that, When the cache configuration information includes the video data sampling type information, determining the target capacity information of the data storage unit based on the at least one video type information includes: Based on the video data sampling type information, determine the sampling ratio of the pixel data corresponding to the luminance channel and chrominance channel respectively; Based on the sampling ratio of the pixel data corresponding to the luminance channel and the chrominance channel, the storage space allocation information of the data storage unit is determined.

9. A buffer device, characterized in that, The device includes: The acquisition module is used to acquire cache configuration information of reference image block data, wherein the reference image block data is used for motion compensation of image frames in the video during the encoding and decoding process, and the cache configuration information includes at least one video type information; A capacity determination module is used to determine the target capacity information of a data storage unit based on the at least one video type information, wherein the target capacity information is the storage space information of the data storage unit, and the storage space matches the at least one video type information; A caching module is used to cache the reference image block data into the data storage unit.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

13. A chip, characterized in that, The method includes a processor coupled to a memory for executing a computer program or instructions stored in the memory, wherein when the processor executes the computer program or instructions, the method as described in any one of claims 1 to 8 is performed.

Images