Semiconductor device

Abstract

The invention provides a semiconductor device. A semiconductor device includes: a substrate; a first connection structure disposed on the substrate, the first connection structure including a first connection conductor; a transistor disposed between the substrate and the first connection structure; a first bonding structure including a first bonding pad connected to the first connection conductor; a second bonding structure including a second bonding pad connected to the first bonding pad; a second connection structure including a second connection conductor connected to the second bonding pad; a stacked structure disposed on the second connection structure; a channel structure penetrating the stacked structure; and a chip protector penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip protector surrounding the stacked structure and the channel structure.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110338972.1 (application date: March 30, 2021, invention title: semiconductor device and method of manufacturing the semiconductor device). Technical Field

[0002] This disclosure generally relates to a semiconductor device and a method for manufacturing the semiconductor device, and more specifically, to a three-dimensional semiconductor device and a method for manufacturing the three-dimensional semiconductor device. Background Technology

[0003] Semiconductor devices include memory cells capable of storing data. Three-dimensional semiconductor devices include memory cells arranged in three dimensions, thereby reducing the area occupied by memory cells per unit area of ​​the substrate.

[0004] To improve the integration density of three-dimensional semiconductor devices, the number of memory cell stacks can be increased. However, as the number of memory cell stacks increases, the operational reliability of the three-dimensional semiconductor device may deteriorate. Summary of the Invention

[0005] According to this disclosure, a semiconductor device includes: a substrate; a first connection structure disposed on the substrate, the first connection structure including a first connection conductor; a transistor disposed between the substrate and the first connection structure, the transistor being connected to the first connection conductor; a first bonding structure including a first bonding pad connected to the first connection conductor, the first bonding structure being disposed on the first connection structure; a second bonding structure including a second bonding pad connected to the first bonding pad, the second bonding structure being disposed on the first bonding structure; a second connection structure including a second connection conductor connected to the second bonding pad, the second connection structure being disposed on the second bonding structure; a stacked structure disposed on the second connection structure, the stacked structure including alternating layers of insulating layers and conductive patterns; a channel structure penetrating the stacked structure, the channel structure being connected to the second connection conductor; and a chip protector penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip protector surrounding the stacked structure and the channel structure.

[0006] Furthermore, according to this disclosure, a semiconductor device includes: a transistor; a first connection conductor connected to the transistor; a first bonding pad connected to the first connection conductor; a second bonding pad connected to the first bonding pad; a second connection conductor connected to the second bonding pad; a channel structure connected to the second connection conductor; and a chip protector including a first protector and a second protector on the first protector, wherein the second protector surrounds the first bonding pad, the second bonding pad, the second connection conductor, and the channel structure.

[0007] Furthermore, according to this disclosure, a semiconductor device includes: a transistor; a first connection conductor connected to the transistor; a first bonding pad connected to the first connection conductor; a second bonding pad connected to the first bonding pad; a second connection conductor connected to the second bonding pad; a channel structure connected to the second connection conductor; a stacked structure surrounding the channel structure; and a chip protector surrounding the first connection conductor, the first bonding pad, the second bonding pad, the second connection conductor, the channel structure, and the stacked structure, wherein the chip protector includes a first protective member and a second protective member on the first protective member, and wherein the first bonding pad, the second bonding pad, the second connection conductor, the channel structure, and the stacked structure are disposed at a height higher than the bottom surface of the second protective member and lower than the top surface of the second protective member.

[0008] Furthermore, according to this disclosure, a method for manufacturing a semiconductor device includes the following steps: forming a first semiconductor structure including a first transistor, a second transistor, and a first bonding pad electrically connected to the first transistor; forming a second semiconductor structure including a stacked structure, a channel structure penetrating the stacked structure, a second bonding pad electrically connected to the channel structure, and a contact sacrificial structure; bonding the first semiconductor structure to the second semiconductor structure by bonding the first bonding pad to the second bonding pad; forming a first hole in the second semiconductor structure by removing the contact sacrificial structure; forming a second hole extending from the second semiconductor structure to the interior of the first semiconductor structure by expanding the first hole; and forming a contact portion in the second hole.

[0009] Similarly, according to this disclosure, a method of manufacturing a semiconductor device includes the following steps: forming a first semiconductor structure including a first transistor and a first bonding pad electrically connected to the first transistor; forming a second semiconductor structure including a stacked structure, a channel structure penetrating the stacked structure, and a second bonding pad electrically connected to the channel structure; bonding the first semiconductor structure to the second semiconductor structure by bonding the first bonding pad to the second bonding pad; forming a first through-slit extending from the second semiconductor structure to the interior of the first semiconductor structure; and forming a first protective member in the first through-slit, wherein the first protective member surrounds the stacked structure and the channel structure. Attached Figure Description

[0010] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be readily apparent to those skilled in the art.

[0011] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals refer to similar elements.

[0012] Figure 1A This is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' is shown.

[0014] Figure 1C It is along Figure 1A The cross-sectional view taken by line B-B' is shown.

[0015] Figure 1D It is along Figure 1A The cross-sectional view taken by line C-C' is shown.

[0016] Figure 1E yes Figure 1B An enlarged view of region C shown.

[0017] Figure 1F yes Figure 1B An enlarged view of region D shown.

[0018] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figure 7A and Figure 7B It is shown Figures 1A to 1F A diagram illustrating a method for manufacturing a semiconductor device.

[0019] Figure 8 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0020] Figure 9 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0021] The specific structural and functional descriptions disclosed herein are illustrative only and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0022] The embodiments are intended to provide a semiconductor device with improved operational reliability and a method for manufacturing the semiconductor device.

[0023] Figure 1A This is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' is shown. Figure 1C It is along Figure 1A The cross-sectional view taken by line B-B' is shown. Figure 1D It is along Figure 1A The cross-sectional view taken by line C-C' is shown. Figure 1E yes Figure 1B An enlarged view of region C shown. Figure 1F yes Figure 1B An enlarged view of region D shown.

[0024] Reference Figures 1A to 1D A semiconductor device may include a cell region CER, a first region RG1, a second region RG2, and a chip guard region CGR. The cell region CER, the first region RG1, the second region RG2, and the chip guard region CGR are regions distinguishable from each other from a planar viewpoint defined by a first direction D1 and a second direction D2. The chip guard region CGR may surround the cell region CER. The first region RG1 and the second region RG2 may be disposed between the cell region CER and the chip guard region CGR.

[0025] The semiconductor device may include a first semiconductor structure SEM1 and a second semiconductor structure SEM2. The first semiconductor structure SEM1 and the second semiconductor structure SEM2 may be bonded together via a wafer bonding process. The first semiconductor structure SEM1 may include a first substrate 100, a first interconnect structure CNS1, and a first bonding structure BDS1. The second semiconductor structure SEM2 may include a second bonding structure BDS2, a second interconnect structure CNS2, a stacked structure STA, a channel structure CS, and a source structure SOS.

[0026] The first substrate 100 may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other because they are not parallel to each other. For example, the first direction D1 and the second direction D2 may be orthogonal to each other. The first substrate 100 may be a semiconductor substrate. In one example, the first substrate 100 may be a silicon substrate.

[0027] A first connection structure CNS1 may be disposed on a first substrate 100. The first connection structure CNS1 may include a first insulating layer 110 and a first connection conductor CB1. The first insulating layer 110 may cover the first substrate 100. The first insulating layer 110 may include an insulating material. In one example, the first insulating layer 110 may include an oxide or a nitride.

[0028] The first connecting conductor CB1 may include a first contact CT1 and a first wiring ML1. The first contact CT1 and the first wiring ML1 may be connected to each other. The first contact CT1 and the first wiring ML1 may include conductive materials.

[0029] The first transistor TR1, the second transistor TR2, and the third transistor TR3 can be disposed between the first connection structure CNS1 and the first substrate 100. The first transistor TR1 can be a transistor disposed in the cell region CER. The second transistor TR2 can be a transistor disposed in the first region RG1. The third transistor TR3 can be a transistor disposed in the second region RG2.

[0030] The first transistor TR1 can be a page buffer constituting a semiconductor device or a transistor connected to a page buffer. The second transistor TR2 can be an X decoder constituting a semiconductor device or a transistor connected to an X decoder. The third transistor TR3 can be an electrostatic discharge (ESD) circuit constituting a semiconductor device or a transistor connected to an ESD circuit.

[0031] Each of the first to third transistors TR1, TR2, and TR3 may include an impurity region IR, a gate insulating layer GI, and a gate GE. The impurity region IR can be formed by doping an impurity into the first substrate 100. The impurity region IR may be connected to a first connection conductor CB1. The impurity region IR may be connected to a first contact CT1. The gate insulating layer GI may include an insulating material. In one example, the gate insulating layer GI may include an oxide. The gate GE may include a conductive material. The gate GE may be connected to the first connection conductor CB1. The gate GE may be connected to the first contact CT1.

[0032] An isolation layer IS may be disposed in the first substrate 100. The isolation layer IS can electrically isolate the first transistor to the third transistors TR1, TR2 and TR3 from each other. The isolation layer IS may include an insulating material. In one example, the isolation layer IS may include an oxide.

[0033] A first bonding structure BDS1 may be disposed on a first connection structure CNS1. The first bonding structure BDS1 may include a second insulating layer 120 and a first bonding pad BP1. The second insulating layer 120 may cover the first insulating layer 110. The second insulating layer 120 may include an insulating material. In one example, the second insulating layer 120 may include a nitride or an oxide.

[0034] The first bonding pad BP1 can be connected to the first connecting conductor CB1 in the first connection structure CNS1. The first bonding pad BP1 can also be connected to the first contact CT1 in the first connection structure CNS1. The first bonding pad BP1 may include a conductive material. In one example, the first bonding pad BP1 may include copper.

[0035] A second bonding structure BDS2 can be disposed on a first bonding structure BDS1. The second bonding structure BDS2 may include a third insulating layer 130 and a second bonding pad BP2. The third insulating layer 130 may cover the second insulating layer 120. The third insulating layer 130 and the second insulating layer 120 can be bonded to each other using a wafer bonding process. The third insulating layer 130 may include an insulating material. In one example, the third insulating layer 130 may include a nitride or an oxide. The interface between the first bonding structure BDS1 and the second bonding structure BDS2 can be defined as a bonding interface.

[0036] The second bonding pad BP2 can be connected to the first bonding pad BP1 in the first bonding structure BDS1. The second bonding pad BP2 and the first bonding pad BP1 can be bonded to each other via a wafer bonding process. The second bonding pad BP2 may include a conductive material. In one example, the second bonding pad BP2 may include copper.

[0037] The second connection structure CNS2 can be disposed on the second bonding structure BDS2. The second connection structure CNS2 may include a fourth insulating layer 140 and a second connection conductor CB2. The fourth insulating layer 140 may cover the third insulating layer 130. The fourth insulating layer 140 may include an insulating material. In one example, the fourth insulating layer 140 may include an oxide or a nitride.

[0038] The second connecting conductor CB2 may include a second wiring ML2, a second contact CT2, and a bit line contact BCT. The second contact CT2 may be connected to the second wiring ML2. The bit line contact BCT may be connected to the second contact CT2. The second bonding pad BP2 may be connected to the second connecting conductor CB2 in the second connection structure CNS2. The second wiring ML2, the second contact CT2, and the bit line contact BCT may include conductive material.

[0039] A stacked structure STA can be disposed on a second connection structure CNS2. The stacked structure STA may include alternately stacked conductive patterns CP and stacked insulating layers IP. The conductive patterns CP can serve as word lines or select lines in a semiconductor device. The conductive patterns CP may include a conductive material. The stacked insulating layers IP may include an insulating material. In one example, the stacked insulating layers IP may include an oxide. The stacked structure STA may include a stepped structure defined by the conductive patterns CP and the stacked insulating layers IP.

[0040] A channel structure CS and a memory layer MR can be configured to penetrate the stacked structure STA. The stacked structure STA can surround the channel structure CS and the memory layer MR. The channel structure CS can extend on the third direction D3. The channel structure CS may include a fill layer FI and a channel layer CL surrounding the fill layer FI. The fill layer FI may include an insulating material. In one example, the fill layer FI may include an oxide. The channel structure CS can be connected to a second connection conductor CB2. The channel layer CL can be connected to a second wiring ML2 through a bit line contact BCT and a second contact CT2. The semiconductor device may include... Figure 1B The bit line contact portion BCT, the second contact portion CT2, and the second wiring ML2 shown may include... Figure 1B Bit line contact, second contact, and second wiring (not shown). Not connected to. Figure 1B The bit line contact BCT, the second contact CT2, and the channel layer CL of the second wiring ML2 shown can be connected to Figure 1B Bit line contact, second contact, and second wiring are not shown in the diagram.

[0041] The channel layer CL can be electrically connected to the first transistor TR1 via the bit line contact BCT, the second contact CT2 in the cell region CER, the second wiring ML2 in the cell region CER, the second bonding pad BP2 in the cell region CER, the first bonding pad BP1 in the cell region CER, the first contact CT1 in the cell region CER, and the first wiring ML1 in the cell region CER. The channel layer CL may include a conductive material. In one example, the channel layer CL may include polysilicon.

[0042] The memory layer MR can extend onto D3. The memory layer MR may include a tunneling insulating layer surrounding a channel structure CS, a data storage layer surrounding the tunneling insulating layer, and a barrier layer surrounding the data storage layer. The tunneling insulating layer may include a material through which charge can tunnel. In one example, the tunneling insulating layer may include an oxide. In one embodiment, the data storage layer may include a material in which charge can be trapped. In one example, the data storage layer may include a nitride. In another embodiment, depending on the data storage method, the data storage layer may include various materials. In one example, the data storage layer may include silicon, a phase change material, or nanodots. The barrier layer may include a material capable of blocking charge movement. In one example, the barrier layer may include an oxide.

[0043] A slit structure SLS can be provided that penetrates the stacked structure STA. The slit structure SLS can extend in a second direction D2 and a third direction D3. Conductive patterns CP disposed on the same layer can be isolated from each other in a first direction D1 by the slit structure SLS. Stacked insulating layers IP disposed at the same height can be isolated from each other in the first direction D1 by the slit structure SLS. The slit structure SLS may include an insulating material. In one example, the slit structure SLS may include an oxide.

[0044] The second semiconductor structure SEM2 may include a fifth insulating layer 150. The fifth insulating layer 150 may be disposed on the second interconnect structure CNS2. The fifth insulating layer 150 may cover the stepped structure of the stacked structure STA. The fifth insulating layer 150 may surround the stacked structure STA. The fifth insulating layer 150 may include an insulating material. In one example, the fifth insulating layer 150 may include an oxide.

[0045] The second semiconductor structure SEM2 may further include a word line contact WCT. The word line contact WCT can connect the second connection conductor CB2 of the second connection structure CNS2 and the conductive pattern CP of the stacked structure STA. The word line contact WCT can also connect the second contact CT2 of the second connection structure CNS2 and the conductive pattern CP of the stacked structure STA. The conductive pattern CP of the stacked structure STA can be electrically connected to the second transistor TR2 via the word line contact WCT, the second contact CT2 in the first region RG1, the second wiring ML2 in the first region RG1, the second bonding pad BP2 in the first region RG1, the first bonding pad BP1 in the first region RG1, the first contact CT1 in the first region RG1, and the first wiring ML1 in the first region RG1.

[0046] A source structure SOS can be disposed on a stacked structure STA and a fifth insulating layer 150. The source structure SOS may include a source layer SA, a sixth insulating layer 160, and a source contact SC. The source layer SA can be disposed on the stacked structure STA. The source layer SA may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The source layer SA may be connected to a channel layer CL. The source layer SA may include a conductive material. In one example, the source layer SA may include polysilicon.

[0047] The sixth insulating layer 160 may cover the source layer SA. The sixth insulating layer 160 may include an insulating material. In one example, the sixth insulating layer 160 may include an oxide or a nitride.

[0048] The source contact SC can be disposed in the sixth insulating layer 160. The source contact SC can be connected to the source layer SA. The source contact SC may include a conductive material.

[0049] A third contact CT3 can be provided, which penetrates the sixth insulating layer 160 and the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1. The third contact CT3 can be disposed in the second region RG2. The third contact CT3 can contact the first wiring ML1 in the second region RG2. The third contact CT3 can be electrically connected to the third transistor T3 through the first wiring ML1 in the second region RG2 and the first contact CT1 in the second region RG2.

[0050] Chip guards CG1, CG2, and CG3 can be provided, penetrating the sixth insulating layer 160 and fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, the second insulating layer 120 of the first bonding structure BDS1, and the first insulating layer 110 of the first connection structure CNS1. Although a semiconductor device including three chip guards CG1, CG2, and CG3 has been shown, the number of chip guards is not limited to only three. For example, four or more chip guards, or two or fewer chip guards, may be present. In the following description, the case where the number of chip guards CG1, CG2, and CG3 is three will be used as an example.

[0051] A semiconductor device may include a first chip protector CG1, a second chip protector CG2, and a third chip protector CG3. The first to third chip protectors CG1, CG2, and CG3 may be disposed within a chip protection region CGR. Each of the first to third chip protectors CG1, CG2, and CG3 may surround a cell region CER. In one example, from a planar view defined by a first direction D1 and a second direction D2 (see...), Figure 1A From the perspective of [reference needed], each of the first to third chip protectors CG1, CG2, and CG3 can surround the cell region CER. Each of the first to third chip protectors CG1, CG2, and CG3 can surround the first connection conductor CB1, the first bonding pad BP1 and the second bonding pad BP2, the second connection conductor CB2, the word line contact WCT, the stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA. Each of the first to third chip protectors CG1, CG2, and CG3 can surround the third contact CT3. The second chip protector CG2 can surround the first chip protector CG1. The third chip protector CG3 can surround the first chip protector CG1 and the second chip protector CG2.

[0052] Each of the first to third chip protection components CG1, CG2, and CG3 may include a first component CGa extending in the first direction D1, a second component CGb extending in the second direction D2, and a third component CGc connecting the first component CGa and the second component CGb (see...). Figure 1A The third component CGc can extend in a direction intersecting the first direction D1 and the second direction D2. From a planar view defined by the first direction D1 and the second direction D2, each of the first chip protector to the third chip protector CG1, CG2 and CG3 can have a ring shape.

[0053] The first component CGa of each of the first to third chip protectors CG1, CG2, and CG3 may be spaced apart from each other in the second direction D2. The cell region CER may be disposed between the first components CGa of each of the first to third chip protectors CG1, CG2, and CG3. The first connecting conductor CB1 and the second connecting conductor CB2, the first bonding pad BP1 and the second bonding pad BP2, the word line contact WCT, the stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA may be disposed between the first components CGa of each of the first to third chip protectors CG1, CG2, and CG3. The length of the first component CGa of each of the first to third chip protectors CG1, CG2, and CG3 in the first direction D1 may be greater than the length of the stacked structure STA in the first direction D1.

[0054] The second components CGb of each of the first to third chip protectors CG1, CG2, and CG3 may be spaced apart from each other in the first direction D1. Cell regions CER may be disposed between the second components CGb of each of the first to third chip protectors CG1, CG2, and CG3. First connecting conductor CB1 and second connecting conductor CB2, first bonding pad BP1 and second bonding pad BP2, word line contact WCT, stacked structure STA, channel structure CS, memory layer MR, and source layer SA may be disposed between the second components CGb of each of the first to third chip protectors CG1, CG2, and CG3. The length of the second component CGb of each of the first to third chip protectors CG1, CG2, and CG3 may be greater than the length of the stacked structure STA in the second direction D2.

[0055] The cell region CER can be surrounded by the first to third components CGa, CGb, and CGc of each of the first to third chip protectors CG1, CG2, and CG3. The first connection conductor CB1 and the second connection conductor CB2, the first bonding pad BP1 and the second bonding pad BP2, the word line contact WCT, the stack-up structure STA, the channel structure CS, the memory layer MR, and the source layer SA can be surrounded by the first to third components CGa, CGb, and CGc of each of the first to third chip protectors CG1, CG2, and CG3.

[0056] Each of the first to third chip protection components CG1, CG2, and CG3 may include a plurality of first protection components GP1 and second protection components GP2 stacked on the third direction D3. The planar shape of each of the first protection components GP1 and the second protection components GP2 defined by the first direction D1 and the second direction D2 may be similar to Figure 1A The planar shape of each of the first to third chip protectors CG1, CG2 and CG3 shown is defined by the first direction D1 and the second direction D2. Viewed from the planar perspective defined by the first direction D1 and the second direction D2, each of the first protective member GP1 and the second protective member GP2 may have an annular shape.

[0057] Each first protective component GP1 may include a first component GP1a extending in the first direction D1 (see...). Figure 1D ), and the second component GP1b extending in the second direction D2 (see Figure 1C And a third component connecting each first component GP1a and each second component GP1b. The length of the first component GP1a of the first protective component GP1 in the first direction D1 may be greater than the length of the stacked structure STA in the first direction D1. The length of the second component GP1b of the first protective component GP1 in the second direction D2 may be greater than the length of the stacked structure STA in the second direction D2.

[0058] Each second protective component GP2 may include a first component GP2a extending in the first direction D1 (see...). Figure 1D ), and the second component GP2b extending in the second direction D2 (see Figure 1C The second protection component GP2 consists of a first component GP2a and a second component GP2b. The length of the first component GP2a in the first direction D1 may be greater than the length of the stacked structure STA in the first direction D1. The length of the second component GP2b in the second direction D2 may be greater than the length of the stacked structure STA in the second direction D2. The first components GP2a of the second protection component GP2 may be spaced apart from each other in the second direction D2. The stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA may be disposed between the first components GP2a of the second protection component GP2. The second components GP2b of the second protection component GP2 may be spaced apart from each other in the first direction D1. The stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA may be disposed between the second components GP2b of the second protection component GP2.

[0059] The first protective component GP1 of each of the first to third chip protectors CG1, CG2, and CG3 can be disposed in the first insulating layer 110 of the first connection structure CNS1. The first protective component GP1 of each of the first to third chip protectors CG1, CG2, and CG3 can be stacked on the third direction D3. The first protective components GP1 of each of the first to third chip protectors CG1, CG2, and CG3 can overlap each other. In one example, the first protective components GP1 of each of the first to third chip protectors CG1, CG2, and CG3 can overlap each other perpendicularly.

[0060] The second protective component GP2 of each of the first to third chip protective components CG1, CG2, and CG3 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1 on the third-direction D3, and contact the first protective component GP1 located at the highest height among the first protective components GP1. The second protective component GP2 of each of the first to third chip protective components CG1, CG2, and CG3 can be disposed on the first protective component GP1 located at the highest height among the first protective components GP1.

[0061] The first protective component GP1 of each of the first to third chip protective components CG1, CG2, and CG3 can be positioned at the same height as the first connecting conductor CB1 of the first connection structure CNS1. The first protective component GP1 of each of the first to third chip protective components CG1, CG2, and CG3 can surround the first connecting conductor CB1 of the first connection structure CNS1.

[0062] The second protection component GP2 of each of the first to third chip protection components CG1, CG2 and CG3 may surround the first bonding pad BP1 and the second bonding pad BP2, the second connecting conductor CB2, the word line contact WCT, the third contact CT3, the stacked structure STA, the channel structure CS, the memory layer MR and the source layer SA.

[0063] The first bonding pad BP1 and the second bonding pad BP2, the second connecting conductor CB2, the word line contact WCT, the third contact CT3, the stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA can be disposed at the same height as the second protection component. Alternatively, the first bonding pad BP1 and the second bonding pad BP2, the second connecting conductor CB2, the word line contact WCT, the third contact CT3, the stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA can be disposed at a height higher than the bottom surface of the second protection component GP2, and can be disposed at a height lower than the top surface of the second protection component GP2.

[0064] A seventh insulating layer 170 may be disposed on the source structure SOS. The seventh insulating layer 170 may cover the sixth insulating layer 160. The seventh insulating layer 170 may include an insulating material. In one example, the seventh insulating layer 170 may include an oxide or a nitride.

[0065] A third wiring ML3 can be disposed in the seventh insulating layer 170. The third wiring ML3 can be connected to the source contact SC. The third wiring ML3 may include a conductive material. A fourth wiring ML4 can be disposed in the seventh insulating layer 170. The fourth wiring ML4 can be connected to the third contact CT3. The fourth wiring ML4 may include a conductive material.

[0066] Reference Figure 1E The third contact portion CT3 may include a first barrier part BO1 and a first conductive part CO1. The first conductive part CO1 may extend on the third contact portion D3. The first conductive part CO1 may extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The first conductive part CO1 may penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0067] The outer wall CO1_S of the first conductive component CO1 can extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The outer wall CO1_S of the first conductive component CO1 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0068] The bottom surface CO1_B of the first conductive component CO1 can be disposed in the first insulating layer 110 of the first connection structure CNS1. The first conductive component CO1 may include a conductive material. In one example, the first conductive component CO1 may include tungsten or aluminum.

[0069] The first barrier component BO1 may extend on the third direction D3. The first barrier component BO1 may extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The first barrier component BO1 may penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0070] The outer wall BO1_S of the first barrier component BO1 can extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The outer wall BO1_S of the first barrier component BO1 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0071] The first barrier component BO1 may surround the first conductive component CO1. The first barrier component BO1 may cover the outer wall CO1_S and bottom surface CO1_B of the first conductive component CO1. The first conductive component CO1 may be disposed within the first barrier component BO1. The bottom surface BO1_B of the first barrier component BO1 may be disposed within the first insulating layer 110 of the first connection structure CNS1. The bottom surface BO1_B of the first barrier component BO1 may contact the first connecting conductor CB1 in the first connection structure CNS1. The first barrier component BO1 may include a conductive material different from the conductive material of the first conductive component CO1. In one example, the first barrier component BO1 may include titanium, titanium nitride, tantalum, or tantalum nitride.

[0072] The bottom surface CO1_B of the first conductive component CO1 can be separated from the first connecting conductor CB1 by the first barrier component BO1. Similar to the third contact CT3, the first connecting conductor CB1 may include the second barrier component BO2 and the second conductive component CO2.

[0073] Reference Figure 1FThe second protection component GP2 of each of the first to third chip protection components CG1, CG2, and CG3 may include a third barrier component BO3 and a third conductive component CO3. The third conductive component CO3 may extend onto the third chip protection component D3. The third conductive component CO3 may extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The third conductive component CO3 may penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0074] The outer wall CO3_S of the third conductive component CO3 can extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The outer wall CO3_S of the third conductive component CO3 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0075] The bottom surface CO3_B can be disposed in the first insulating layer 110 of the first connection structure CNS1. The third conductive component CO3 can include a conductive material. In one example, the third conductive component CO3 can include tungsten or aluminum.

[0076] The third barrier component BO3 can extend onto the third direction D3. The third barrier component BO3 can extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The third barrier component BO3 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0077] The outer wall BO3_S of the third barrier component BO3 can extend from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The outer wall BO3_S of the third barrier component BO3 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1.

[0078] The third barrier component BO3 may surround the third conductive component CO3. The third barrier component BO3 may cover the outer wall CO3_S and bottom surface CO3_B of the third conductive component CO3. The third conductive component CO3 may be disposed within the third barrier component BO3. The bottom surface BO3_B of the third barrier component BO3 may be disposed within the first insulating layer 110 of the first connection structure CNS1. The bottom surface BO3_B of the third barrier component BO3 may contact the first protective component GP1 in the first connection structure CNS1. The third barrier component BO3 may include a conductive material different from the conductive material of the third conductive component CO3. In one example, the third barrier component BO3 may include titanium, titanium nitride, tantalum, or tantalum nitride.

[0079] The bottom surface CO3_B of the third conductive component CO3 can be separated from the first protective component GP1 by the third barrier component BO3. Similar to the second protective component GP2, the first protective component GP1 may include the fourth barrier component BO4 and the fourth conductive component CO4.

[0080] The second protective component GP2 can be disposed within the first through slit SL1. The first through slit SL1 extends from the sixth insulating layer 160 of the source structure SOS to the first insulating layer 110 of the first connection structure CNS1. The first through slit SL1 can penetrate the sixth insulating layer 160, the fifth insulating layer 150 of the source structure SOS, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, and the second insulating layer 120 of the first bonding structure BDS1. The second protective component GP2 can cover the sidewall SL1_S and the bottom surface SL1_B of the first through slit SL1. The third barrier component BO3 of the second protective component GP2 can cover the sidewall SL1_S and the bottom surface SL1_B of the first through slit SL1.

[0081] A semiconductor device according to an embodiment of the present disclosure includes a third contact CT3 extending from a source structure SOS to a first connection structure CNS1, and first chip protectors to third chip protectors CG1, CG2, and CG3. Therefore, the wiring freedom of the semiconductor device can be ensured, and the size of the semiconductor device can be reduced or minimized.

[0082] A semiconductor device according to an embodiment of the present disclosure includes first to third chip protectors CG1, CG2, and CG3 extending from a source structure SOS to a first interconnect structure CNS1, such that the first to third chip protectors CG1, CG2, and CG3 can seal other components even at portions adjacent to the bonding interface. Therefore, chip breakage can be reduced or prevented, and moisture absorption can be mitigated or prevented.

[0083] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figure 7A and Figure 7B It is shown Figures 1A to 1F A diagram illustrating a method for manufacturing a semiconductor device.

[0084] For ease of description, and with reference Figures 1A to 1F The same components are represented by the same reference numerals, and repeated descriptions will be omitted.

[0085] The manufacturing method described below is merely... Figures 1A to 1F One embodiment of the method for manufacturing the semiconductor device shown. Figures 1A to 1F The method of manufacturing the semiconductor device shown is not limited to the following methods.

[0086] Reference Figure 2 It can form a second semiconductor structure SEM2 including a second substrate 200, a source structure SOS, a stacked structure STA, and a fifth insulating layer 150.

[0087] A second substrate 200 may be formed. The second substrate 200 may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The second substrate 200 may be a semiconductor substrate. In one example, the second substrate 200 may be a silicon substrate.

[0088] The source structure SOS can be formed on the second substrate 200. The steps of forming the source structure SOS may include forming a sixth insulating layer 160 on the second substrate 200, and forming a source layer SA in the sixth insulating layer 160.

[0089] The stacked structure STA and the fifth insulating layer 150 can be formed on the source structure SOS. The steps of forming the stacked structure STA and the fifth insulating layer 150 may include: alternately forming a stacked insulating layer IP and a sacrificial layer FL on the source structure SOS; forming a stepped structure by etching the stacked insulating layer IP and the stacked sacrificial layer FL; and forming the fifth insulating layer 150. The stacked sacrificial layer FL may include a material different from the material of the stacked insulating layer IP. In one example, the stacked sacrificial layer FL may include a nitride.

[0090] It can form a channel structure CS and a memory layer MR that penetrate the stacked structure STA.

[0091] Reference Figure 3A and Figure 3BConductive patterns CP and slit structures SLS can be formed. The steps of forming conductive patterns CP and slit structures SLS may include the following steps: forming a slit that penetrates the stacked structure STA, removing the stacked sacrificial layer FL through the slit, forming the conductive pattern CP in the empty space where the stacked sacrificial layer FL has been removed, and forming the slit structure SLS in the slit.

[0092] The second connection structure CNS2 can be formed on the stacked structure STA and the fifth insulating layer 150. The fourth insulating layer 140, the bit line contact portion BCT in the fourth insulating layer 140, the second contact portion CT2, and the second wiring ML2 can be formed therein.

[0093] A word line contact WCT connected to the conductive pattern CP can be formed. The word line contact WCT can be formed earlier than the second contact CT2. A portion of the fourth insulating layer 140 can be formed, and a word line contact WCT penetrating this portion of the fourth insulating layer 140 can be formed. Another portion of the fourth insulating layer 140 covering the word line contact WCT can also be formed.

[0094] A contact sacrificial structure CFS can be formed in the second region RG2. A portion of the fourth insulating layer 140 can be formed, a contact sacrificial structure CFS penetrating that portion of the fourth insulating layer 140 can be formed, and then another portion of the fourth insulating layer 140 covering the contact sacrificial structure CFS can be formed.

[0095] The contact sacrificial structure CFS can extend onto the third direction D3. The contact sacrificial structure CFS can extend from the fourth insulating layer 140 to the second substrate 200. The contact sacrificial structure CFS can penetrate the fifth insulating layer 150 and the sixth insulating layer 160 of the source structure SOS. The lowest portion of the contact sacrificial structure CFS can be disposed in the second substrate 200.

[0096] Each contact sacrificial structure CFS may include a first component CFS1 and a second component CFS2. The second component CFS2 of the contact sacrificial structure CFS may be disposed on the first component CFS1 of the contact sacrificial structure CFS. The second component CFS2 of the contact sacrificial structure CFS may be disposed in the fourth insulating layer 140 of the second connection structure CNS2. The first component CFS1 of the contact sacrificial structure CFS may extend from the fourth insulating layer 140 to the second substrate 200 and penetrate the fifth insulating layer 150 and the sixth insulating layer 160 of the source structure SOS. The contact sacrificial structure CFS may include a conductive material.

[0097] The first component CFS1 of the contact sacrifice structure CFS can be formed simultaneously with the word line contact WCT. The second component CFS2 of the contact sacrifice structure CFS can be formed simultaneously with the second contact CT2 connected to the word line contact WCT.

[0098] The first protective sacrificial structure GFS1, the second protective sacrificial structure GFS2, and the third protective sacrificial structure GFS3 can be formed in the chip protection region CGR. A portion of the fourth insulating layer 140 can be formed, and the first to third protective sacrificial structures GFS1, GFS2, and GFS3 can be formed through this portion of the fourth insulating layer 140. Another portion of the fourth insulating layer 140 can also be formed covering the first to third protective sacrificial structures GFS1, GFS2, and GFS3.

[0099] The first to third protective sacrificial structures GFS1, GFS2, and GFS3 can extend onto the third direction D3. The first to third protective sacrificial structures GFS1, GFS2, and GFS3 can extend from the fourth insulating layer 140 to the second substrate 200. The first to third protective sacrificial structures GFS1, GFS2, and GFS3 can penetrate the fifth insulating layer 150 and the sixth insulating layer 160 of the source structure SOS. The lowest portion of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 can be disposed within the second substrate 200.

[0100] Each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 may include a first component GFSa and a second component GFSb. The second component GFSb of each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 may be disposed on the first component GFSa of each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3. The second component GFSb of each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 may be disposed in the fourth insulating layer 140 of the second connection structure CNS2. The first component GFSa of each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 may extend from the fourth insulating layer 140 to the second substrate 200 and penetrate the fifth insulating layer 150 and the sixth insulating layer 160 of the source structure SOS. The first to third protective sacrificial structures GFS1, GFS2, and GFS3 may include a conductive material.

[0101] The first component GFSa of each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 can be formed simultaneously with the word line contact WCT and the first component CFS1 of the contact sacrificial structure CFS. The second component GFSb of each of the first to third protective sacrificial structures GFS1, GFS2, and GFS3 can be formed simultaneously with the second contact CT2 connected to the word line contact WCT and the second component CFS2 of the contact sacrificial structure CFS.

[0102] Each of the first to third protection sacrificial structures GFS1, GFS2, and GFS3 can surround the cell region CER. Each of the first to third protection sacrificial structures GFS1, GFS2, and GFS3 can surround the stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA. The second protection sacrificial structure GFS2 can surround the first protection sacrificial structure GFS1. The third protection sacrificial structure GFS3 can surround the first protection sacrificial structure GFS1 and the second protection sacrificial structure GFS2.

[0103] The second bonding structure BDS2 can be formed on the second connection structure CNS2. The third insulating layer 130 and the second bonding pad BP2 in the third insulating layer 130 can be formed.

[0104] Reference Figure 4A and Figure 4B It can form a first semiconductor structure SEM1 including a first substrate 100, first transistors to third transistors TR1, TR2 and TR3, a first connection structure CNS1 and a first bonding structure BDS1.

[0105] A first substrate 100 can be formed. A first transistor TR1 can be formed on a cell region CER of the first substrate 100, a second transistor TR2 can be formed on a first region RG1 of the first substrate 100, and a third transistor TR3 can be formed on a third region RG3 of the first substrate 100.

[0106] The first connection structure CNS1 can be formed on the first substrate 100 and the first to third transistors TR1, TR2 and TR3. A first insulating layer 110 covering the first substrate 100 and the first to third transistors TR1, TR2 and TR3, as well as a first wiring ML1 and a first contact CT1 in the first insulating layer 110, can be formed.

[0107] A first protective component GP1 for each of the first to third chip protective components CG1, CG2, and CG3 can be formed in the first insulating layer 110. A portion of the first insulating layer 110 can be formed, penetrating that portion of the first insulating layer 110, and another portion of the first insulating layer 110 can be formed covering the first protective component GP1.

[0108] The first protective component GP1 of the first chip protector CG1 may surround the cell region CER. The first protective component GP1 of the first chip protector CG1 may surround the first contact portion CT1 and the first wiring ML1 of the first connecting conductor CB1. The first protective component GP1 of the second chip protector CG2 may surround the first protective component GP1 of the first chip protector CG1. The first protective component GP1 of the third chip protector CG3 may surround the first protective component GP1 of the second chip protector CG2.

[0109] The first bonding structure BDS1 can be formed on the first connection structure CNS1. The second insulating layer 120 and the first bonding pad BP1 in the second insulating layer 120 can be formed.

[0110] Reference Figure 5 The first semiconductor structure SEM1 and the second semiconductor structure SEM2 can be bonded to each other using a wafer bonding process. The first bonding structure BDS1 and the second bonding structure BDS2 can also be bonded to each other using a wafer bonding process. The first bonding pad BP1 of the first bonding structure BDS1 and the second bonding pad BP2 of the second bonding structure BDS2 can be bonded to each other. The second insulating layer 120 of the first bonding structure BDS1 and the third insulating layer 130 of the second bonding structure BDS2 can also be bonded to each other.

[0111] After the second semiconductor structure SEM2 is reversed, the first semiconductor structure SEM1 and the second semiconductor structure SEM2 can be bonded to each other. Therefore, the second substrate 200 can be exposed. A bonding interface BB can be defined between the first bonding structure BDS1 and the second bonding structure BDS2. A bonding interface BB can also be defined between the first bonding pad BP1 and the second bonding pad BP2.

[0112] Reference Figure 6 The exposed second substrate 200 can be removed. When the second substrate 200 is removed, the contact sacrificial structure CFS and the first to third protective sacrificial structures GFS1, GFS2 and GFS3 can be exposed.

[0113] The exposed contact sacrificial structure CFS and the exposed first to third protective sacrificial structures GFS1, GFS2, and GFS3 can be removed. When the contact sacrificial structure CFS is removed, a first hole HO1 can be formed. The empty space formed when the contact sacrificial structure CFS is removed can be defined as the first hole HO1. The first hole HO1 can extend in the third direction D3 from the sixth insulating layer 160 to the fourth insulating layer 140 of the second connection structure CNS2, and penetrate the sixth insulating layer 160 and the fifth insulating layer 150. The bottom surface of the first hole HO1 can be located at a height higher than the height of the bonding interface BB.

[0114] A second through-slit SL2 can be formed when the exposed first to third protective sacrificial structures GFS1, GFS2, and GFS3 are removed. The empty space formed when the first to third protective sacrificial structures GFS1, GFS2, and GFS3 are removed can be defined as the second through-slit SL2. The second through-slit SL2 can extend in the third direction D3 from the sixth insulating layer 160 of the source structure SOS to the fourth insulating layer 140 of the second connection structure CNS2, and penetrate the sixth insulating layer 160 and the fifth insulating layer 150. The bottom surface of the second through-slit SL2 can be disposed in the fourth insulating layer 140 of the second connection structure CNS2. The bottom surface of the second through-slit SL2 can be located at a height higher than the bonding interface BB. The second through-slit SL2 can surround the cell region CER. The second through-slit SL2 can surround the stacked structure STA, the channel structure CS, the memory layer MR, and the source layer SA.

[0115] Reference Figure 7A and Figure 7B A mask layer MA can be formed on the source structure SOS. The mask layer MA may include a first opening OP1 and a second opening OP2. The steps of forming the mask layer MA may include forming a photoresist layer on the source structure SOS, and forming the first opening OP1 and the second opening OP2 by patterning the photoresist layer.

[0116] The first opening OP1 of the mask layer MA can overlap with the first hole HO1. The second opening OP2 of the mask layer MA can overlap with the second through-slit SL2.

[0117] The etching process can be performed by using a mask layer MA as an etching barrier. According to the etching process, the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, the second insulating layer 120 of the first bonding structure BDS1, and the first insulating layer 110 of the first connection structure CNS1 can be etched. According to the etching process, the first hole HO1 and the second through-slit SL2 can be extended.

[0118] The expanded first hole HO1 can be defined as the second hole HO2. The second hole HO2 can penetrate the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, the bonding interface BB, and the second insulating layer 120 of the first bonding structure BDS1, and extend downward to the first insulating layer 110 of the first connection structure CNS1. The first wiring ML1 of the first connecting conductor CB1 in the second region RG2 can be exposed through the second hole HO2.

[0119] The extended second through-slit SL2 can be defined as the first through-slit SL1. The first through-slit SL1 can penetrate the fourth insulating layer 140 of the second connection structure CNS2, the third insulating layer 130 of the second bonding structure BDS2, the bonding interface BB, and the second insulating layer 120 of the first bonding structure BDS1, and extend downward to the first insulating layer 110 of the first connection structure CNS1. The first protective component GP1 in the chip protection region CGR can be exposed through the first through-slit SL1.

[0120] After forming the second hole HO2 and the first through-slit SL1, the remaining mask layer MA can be removed. Subsequently, the third contact portion CT3 can be formed in the second hole HO2 (see...). Figure 1B And a second protective component GP2 can be formed in the first through-slit SL1 (see...) Figure 1B Subsequently, a source contact SC can be formed that connects to the source layer SA (see...). Figure 1B ).

[0121] A seventh insulating layer 170 (see) can be formed covering the source contact SC, the third contact CT3, and the second protective component GP2. Figure 1B The third wiring ML3 and the fourth wiring ML4 can be formed in the seventh insulating layer 170.

[0122] In the semiconductor device manufacturing method according to this embodiment, a contact sacrificial structure CFS and protective sacrificial structures GFS1, GFS2, and GFS3 are simultaneously formed, a wafer bonding process is performed, and then the third contact CT3 and the second protective component GP2 are formed by removing the contact sacrificial structure CFS and the protective sacrificial structures GFS1, GFS2, and GFS3. Therefore, the process of forming the third contact CT3 and the second protective component GP2 can be simplified.

[0123] Figure 8 This is a block diagram illustrating the configuration of a memory system 1100 according to one embodiment of the present disclosure.

[0124] Reference Figure 8 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0125] The memory device 1120 may include the semiconductor device described above. The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0126] Memory controller 1110 is configured to control memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction code (ECC) circuitry 1114, and memory interface 1115. SRAM 1111 serves as the operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. ECC circuitry 1114 detects and corrects errors in data read from memory device 1120, and memory interface 1115 interfaces with memory device 1120. Additionally, memory controller 1110 may also include ROM or similar components for storing code data for connection to the host interface.

[0127] The memory system 1100 configured as described above can be a memory card or solid-state drive (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external source (e.g., a host) through one of various interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0128] Figure 9 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0129] Reference Figure 9 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may further include a battery for providing operating voltage to the computing system 1200, and may further include an application chipset, a camera image processor (CIS), and mobile D-RAM, etc.

[0130] The memory system 1210 can be configured with a reference Figure 8 The memory device 1212 and memory controller 1211 are described.

[0131] According to this disclosure, a semiconductor device includes a contact portion penetrating the bonding interface between semiconductor structures and a chip protection member. Therefore, the arrangement freedom of the semiconductor device can be ensured, and the size of the semiconductor device can be reduced or minimized.

[0132] Embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for the purpose of explaining the embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0133] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms with dictionary definitions shall be understood to have a meaning consistent with the context of the relevant art. Unless explicitly defined in this application, terms should not be interpreted in an idealized or overly formal manner.

[0134] Cross-references to related applications

[0135] This application claims priority to Korean Patent Application No. 10-2020-0099316, filed on August 7, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: substrate; A first connection structure is disposed on the substrate, and the first connection structure includes a first connection conductor; A transistor disposed between the substrate and the first connection structure, the transistor being connected to the first connection conductor; A first bonding structure, the first bonding structure including a first bonding pad connected to the first connecting conductor, the first bonding structure being disposed on the first connecting structure; A second bonding structure, the second bonding structure including a second bonding pad connected to the first bonding pad, the second bonding structure being disposed on the first bonding structure; A second connection structure, the second connection structure including a second connection conductor connected to the second bonding pad, the second connection structure being disposed on the second bonding structure; A stacked structure is disposed on the second connecting structure, the stacked structure comprising alternating layers of insulating layers and conductive patterns; A channel structure that penetrates the stacked structure and is connected to the second connecting conductor; as well as A chip protection element that penetrates the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, and surrounds the stacked structure and the channel structure. The chip protection element includes a single continuous element that extends vertically through the second connection structure, the second bonding structure, and the first bonding structure, and extends into the first connection structure, wherein the single continuous element includes a flat sidewall.

2. The semiconductor device according to claim 1, wherein, The chip protection component includes: A plurality of first protective components, said plurality of first protective components being in the first connection structure; and The second protective component penetrates the second connecting structure, the second joining structure, and the first joining structure.

3. The semiconductor device according to claim 2, wherein, The second protective component includes: A conductive component, the conductive component penetrating the second connection structure, the second bonding structure, and the first bonding structure; and A barrier component surrounding the conductive component.

4. The semiconductor device according to claim 3, wherein, The conductive component and the barrier component are made of different materials.

5. The semiconductor device according to claim 3, wherein, The barrier component covers the sidewalls and bottom surface of the conductive component.

6. The semiconductor device according to claim 2, wherein, The second protective component fills the through-slit that penetrates the second connecting structure, the second joining structure, and the first joining structure.

7. The semiconductor device according to claim 6, wherein, The second protective component includes: A barrier component that covers the sidewalls and bottom surface of the through-slit; and A conductive component, wherein the conductive component is located within the barrier component.

8. The semiconductor device according to claim 7, wherein, The sidewall of the barrier component extends from the second connection structure to the first connection structure.

9. A semiconductor device comprising: transistor; A first connection structure, the first connection structure including a first connection conductor connected to the transistor; A first bonding structure, the first bonding structure including a first bonding pad, the first bonding pad being connected to the first connection conductor; A second bonding structure, the second bonding structure including a second bonding pad, the second bonding pad being connected to the first bonding pad; A second connection structure, the second connection structure including a second connection conductor, the second connection conductor being connected to the second bonding pad; A channel structure, the channel structure being connected to the second connecting conductor; as well as A chip protection component, comprising a first protective component and a second protective component on the first protective component. The second protective component surrounds the first bonding pad, the second bonding pad, the second connecting conductor, and the channel structure. The second protective component includes a single continuous member that extends vertically through the second connecting structure, the second joining structure, and the first joining structure, and extends into the first connecting structure, wherein the single continuous member includes a flat sidewall.

10. The semiconductor device according to claim 9, wherein, The second protective component penetrates the bonding interface between the first bonding pad and the second bonding pad.

11. The semiconductor device according to claim 9, wherein, The second protective component includes: Conductive components; and A barrier component that covers the sidewalls and bottom surface of the conductive component.

12. The semiconductor device according to claim 11, wherein, The conductive component and the barrier component penetrate the bonding interface between the first bonding pad and the second bonding pad.

13. The semiconductor device according to claim 11, wherein, The conductive component is spaced apart from the first protective component; and The barrier component is in contact with the first protective component.

14. A semiconductor device comprising: transistor; A first connection structure, the first connection structure including a first connection conductor connected to the transistor; A first bonding structure, the first bonding structure including a first bonding pad, the first bonding pad being connected to the first connection conductor; A second bonding structure, the second bonding structure including a second bonding pad, the second bonding pad being connected to the first bonding pad; A second connection structure, the second connection structure including a second connection conductor, the second connection conductor being connected to the second bonding pad; A channel structure, the channel structure being connected to the second connecting conductor; A stacked structure, the stacked structure surrounding the channel structure; as well as A chip protection element surrounding the first connection conductor, the first bonding pad, the second bonding pad, the second connection conductor, the channel structure, and the stack-up structure. The chip protection component includes a first protection component and a second protection component on the first protection component. The first bonding pad, the second bonding pad, the second connecting conductor, the channel structure, and the stack-up structure are positioned at a height higher than the bottom surface of the second protective component and lower than the top surface of the second protective component. The second protective component includes a single continuous member that extends vertically through the second connecting structure, the second joining structure, and the first joining structure, and extends into the first connecting structure, wherein the single continuous member includes a flat sidewall.

15. The semiconductor device according to claim 14, wherein, The second protective component includes a plurality of first components extending in a first direction, the plurality of first components being spaced apart from each other in a second direction intersecting the first direction. The stacked structure is disposed between the plurality of first components, and Wherein, the length of each of the plurality of first components in the first direction is greater than the length of the stacked structure in the first direction.

16. A semiconductor device comprising: substrate; A first connection structure is disposed on the substrate, and the first connection structure includes a first connection conductor; A transistor disposed between the substrate and the first connection structure, the transistor being connected to the first connection conductor; A first bonding structure, the first bonding structure including a first bonding pad connected to the first connecting conductor, the first bonding structure being disposed on the first connecting structure; A second bonding structure, the second bonding structure including a second bonding pad connected to the first bonding pad, the second bonding structure being disposed on the first bonding structure; A second connection structure, the second connection structure including a second connection conductor connected to the second bonding pad, the second connection structure being disposed on the second bonding structure; A stacked structure is disposed on the second connecting structure, the stacked structure comprising alternating layers of insulating layers and conductive patterns; A channel structure that penetrates the stacked structure and is connected to the second connecting conductor; as well as A chip protection element that penetrates the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, and surrounds the stacked structure and the channel structure. The chip protection element includes a single continuous element that extends vertically through the second connection structure, the second bonding structure, and the first bonding structure, and extends into the first connection structure, wherein the chip protection element is continuously disposed on a plane perpendicular to the vertical direction.

17. The semiconductor device according to claim 16, wherein, The chip protection component includes: A plurality of first protective components, said plurality of first protective components being in the first connection structure; and The second protective component penetrates the second connecting structure, the second joining structure, and the first joining structure.

18. The semiconductor device according to claim 17, wherein, The second protective component includes: A conductive component, the conductive component penetrating the second connection structure, the second bonding structure, and the first bonding structure; and A barrier component surrounding the conductive component.

19. The semiconductor device according to claim 18, wherein, The conductive component and the barrier component are made of different materials.

20. The semiconductor device according to claim 18, wherein, The barrier component covers the sidewalls and bottom surface of the conductive component.

21. The semiconductor device according to claim 17, wherein, The second protective component fills the through-slit that penetrates the second connecting structure, the second joining structure, and the first joining structure.

22. The semiconductor device according to claim 21, wherein, The second protective component includes: A barrier component that covers the sidewalls and bottom surface of the through-slit; and A conductive component, wherein the conductive component is located within the barrier component.

23. The semiconductor device according to claim 22, wherein, The sidewall of the barrier component extends from the second connection structure to the first connection structure.

24. A semiconductor device comprising: transistor; A first connection structure, the first connection structure including a first connection conductor connected to the transistor; A first bonding structure, the first bonding structure including a first bonding pad, the first bonding pad being connected to the first connection conductor; A second bonding structure, the second bonding structure including a second bonding pad, the second bonding pad being connected to the first bonding pad; A second connection structure, the second connection structure including a second connection conductor, the second connection conductor being connected to the second bonding pad; A channel structure, the channel structure being connected to the second connecting conductor; as well as A chip protection component, comprising a first protective component and a second protective component on the first protective component. The second protective component surrounds the first bonding pad, the second bonding pad, the second connecting conductor, and the channel structure. The second protective component includes a single continuous member that extends vertically through the second connecting structure, the second bonding structure, and the first bonding structure, and extends into the first connecting structure, wherein the chip protective component is continuously disposed on a plane perpendicular to the vertical direction.

25. The semiconductor device according to claim 24, wherein, The second protective component penetrates the bonding interface between the first bonding pad and the second bonding pad.

26. The semiconductor device of claim 24, wherein, The second protective component includes: Conductive components; and A barrier component that covers the sidewalls and bottom surface of the conductive component.

27. The semiconductor device of claim 26, wherein, The conductive component and the barrier component penetrate the bonding interface between the first bonding pad and the second bonding pad.

28. The semiconductor device according to claim 26, wherein, The conductive component is spaced apart from the first protective component; and The barrier component is in contact with the first protective component.

29. A semiconductor device comprising: transistor; A first connection structure, the first connection structure including a first connection conductor connected to the transistor; A first bonding structure, the first bonding structure including a first bonding pad, the first bonding pad being connected to the first connection conductor; A second bonding structure, the second bonding structure including a second bonding pad, the second bonding pad being connected to the first bonding pad; A second connection structure, the second connection structure including a second connection conductor, the second connection conductor being connected to the second bonding pad; A channel structure, the channel structure being connected to the second connecting conductor; A stacked structure, the stacked structure surrounding the channel structure; as well as A chip protection element surrounding the first connection conductor, the first bonding pad, the second bonding pad, the second connection conductor, the channel structure, and the stack-up structure. The chip protection component includes a first protection component and a second protection component on the first protection component. The first bonding pad, the second bonding pad, the second connecting conductor, the channel structure, and the stack-up structure are positioned at a height higher than the bottom surface of the second protective component and lower than the top surface of the second protective component. The second protective component includes a single continuous member that extends vertically through the second connecting structure, the second bonding structure, and the first bonding structure, and extends into the first connecting structure, wherein the chip protective component is continuously disposed on a plane perpendicular to the vertical direction.

30. The semiconductor device according to claim 29, wherein, The second protective component includes a plurality of first components extending in a first direction, the plurality of first components being spaced apart from each other in a second direction intersecting the first direction. The stacked structure is disposed between the plurality of first components, and Wherein, the length of each of the plurality of first components in the first direction is greater than the length of the stacked structure in the first direction.

Images