Laminated capacitor, preparation method thereof, high-voltage generation circuit and semiconductor memory device

Abstract

The invention discloses a laminated capacitor, a preparation method thereof, a high-voltage generation circuit and a semiconductor memory device, and aims to solve the problems that a high-voltage capacitor in the conventional SONOS (Silicon Oxide Nitride Oxide Semiconductor) process directly uses thin tunneling oxygen as a bottom medium, the withstand voltage is insufficient, and large-area series-parallel capacitor stacking is needed. The sacrificial oxide layer and the lower oxide layer on the sacrificial oxide layer jointly form a bottom oxide layer, a silicon nitride layer and an upper oxide layer are sequentially formed on the bottom oxide layer, the four layers of media form a dielectric structure of the laminated capacitor, conductive electrodes are formed on the upper portion and the lower portion of the dielectric structure, and therefore the laminated capacitor with the withstand voltage remarkably improved is obtained. The laminated capacitor can be used for a high-voltage generation circuit, provides programming and erasing internal high voltage for a storage unit array adopting a charge trapping gate structure, and gives consideration to high-voltage reliability and layout area and reduces manufacturing cost on the premise of not increasing an extra high-voltage process module.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multilayer capacitor, its fabrication method, a high-voltage generation circuit, and a semiconductor memory device. Background Technology

[0002] In charge-trapping flash memory products represented by SONOS technology, an ONO stack consisting of a lower oxide layer, a silicon nitride layer, and an upper oxide layer is typically used as the gate dielectric structure of the memory cell. By trapping and releasing charges in the silicon nitride layer, the threshold voltage can be repeatedly controlled for erasure and rewriting. In order to perform programming and erasure operations on the memory cell, the chip needs to generate an internal high voltage that is significantly higher than the external supply voltage. For example, based on the external supply voltage of a few volts, a high voltage generation circuit such as a charge pump is used to boost the voltage to a voltage of tens of volts or even higher, and this internal high voltage is applied to the nodes such as the word line, source, or substrate electrode of the memory cell.

[0003] In such high-voltage generation circuits, capacitors typically exist in the form of pump capacitors, coupling capacitors, etc., used for charging and discharging and potential rise under timing control, while also serving as charge storage and voltage smoothing functions at high-voltage nodes. Ideally, these capacitors need to have sufficient voltage margin and long-term reliability under high-voltage operating conditions to prevent dielectric breakdown or leakage degradation under high field strength; on the other hand, it is desirable to provide a large capacitance value within a limited chip area to ensure high-voltage generation efficiency and output voltage stability. However, under actual process constraints, developing a separate high-voltage capacitor process specifically for high-voltage circuits (e.g., adding an extra high-voltage oxide layer process step) would significantly increase process complexity and manufacturing costs, which is detrimental to mass production and yield control.

[0004] In existing technologies, for process reuse considerations, capacitors in high-voltage generation circuits often directly utilize existing ONO multilayer dielectrics from the manufacturing process as the capacitor dielectric structure. The bottom oxide layer typically shares the same process as the tunneling oxide layer of the memory cell. To meet the performance requirements of memory cell tunneling injection, erase speed, and data retention, this tunneling oxide layer is often designed to be relatively thin. For high-voltage capacitors, this thin bottom oxide layer structure, when subjected to voltages of tens of volts or even higher, tends to concentrate the electric field in the thinnest and lowest dielectric layer, causing the electric field strength of this layer to approach or exceed its breakdown limit. This leads to reliability issues such as breakdown, increased leakage, and dielectric degradation in the capacitor cell under high-voltage operation or long-term cyclic stress.

[0005] To mitigate these issues, circuit design typically employs multiple capacitors connected in series and then in parallel to form a structure that satisfies both the voltage withstand capability and capacitance value. While this can improve the equivalent voltage withstand capability to some extent, it significantly increases the number of capacitor cells and the layout area, making the high-voltage generation circuit a major consumer of silicon, thereby driving up the overall chip area and cost. Summary of the Invention

[0006] To address the problems of insufficient voltage withstand capability, poor reliability, and excessively large layout area and difficulty in reducing process costs caused by using a thin tunneling oxide layer as the bottom dielectric in existing high-voltage generation circuit capacitors, this invention proposes a multilayer capacitor scheme that reuses the sacrificial oxide layer based on the existing ONO process. In the capacitor region, instead of completely etching away the sacrificial oxide layer using conventional processes, it is retained and used together with the underlying oxide layer as the bottom oxide layer of the capacitor. This makes the high voltage withstand capability of the bottom oxide layer significantly greater than that of a capacitor composed solely of a thin tunneling oxide layer. Thus, without adding new high-voltage process modules, a multilayer capacitor structure with higher overall voltage withstand capability and suitable for use in high-voltage generation circuits and semiconductor memory devices is obtained.

[0007] According to a first aspect of the present invention, a multilayer capacitor is provided, formed in a multilayer capacitor region on a semiconductor substrate, comprising: A sacrificial oxide layer formed on the surface of the active region of the semiconductor substrate; A lower oxide layer, a silicon nitride layer, and an upper oxide layer are sequentially formed on the sacrificial oxide layer. The sacrificial oxide layer, the lower oxide layer, the silicon nitride layer, and the upper oxide layer together constitute the dielectric structure of the stacked capacitor. And a first conductive layer and a second conductive layer respectively disposed on the upper and lower sides of the dielectric structure and electrically insulated from each other by the dielectric structure; The sacrificial oxide layer, which is originally designed to be removed in the subsequent photolithography and etching steps of the ONO stacked dielectric layer in conventional processes, is retained in this stacked capacitor as part of the dielectric structure to increase the high voltage resistance of the bottom oxide layer.

[0008] In some technical solutions, the sacrificial oxide layer, the lower oxide layer, the silicon nitride layer, and the upper oxide layer each have a preset target thickness, wherein the target thickness of the sacrificial oxide layer is greater than the target thickness of the lower oxide layer; and the deviation between the actual thickness of each dielectric layer and its corresponding target thickness is controlled as follows: lower oxide layer 18±3Å, silicon nitride layer 80±3Å, and upper oxide layer 45±1Å.

[0009] In some technical solutions, the first conductive layer is an upper electrode located above the upper oxide layer, including at least one of a polycrystalline silicon electrode layer covering the upper oxide layer and a metal interconnect wire; The second conductive layer is a lower electrode located below the sacrificial oxide layer, including at least one of a doped active region in the semiconductor substrate, a well region, and a gate polysilicon layer formed below the sacrificial oxide layer.

[0010] According to a second aspect of the present invention, a method for preparing a multilayer capacitor is further provided, comprising the following steps: A sacrificial oxide layer is formed on the active region of the semiconductor substrate; An ONO stacked dielectric layer comprising a lower oxide layer, a silicon nitride layer, and an upper oxide layer is deposited on the sacrificial oxide layer. The ONO stacked dielectric layer is subjected to photolithography and etching processes. In the stacked capacitor region used to form the stacked capacitor, the sacrificial oxide layer and the lower oxide layer, silicon nitride layer and upper oxide layer thereon are retained. In the non-capacitor region different from the stacked capacitor region, the sacrificial oxide layer is removed, thereby forming the dielectric structure of the stacked capacitor including the sacrificial oxide layer, the lower oxide layer, the silicon nitride layer and the upper oxide layer in the stacked capacitor region. A first conductive layer and a second conductive layer are formed on the upper and lower sides of the dielectric structure, respectively, so that the first conductive layer and the second conductive layer are electrically insulated from each other through the dielectric structure to form a multilayer capacitor.

[0011] In some technical solutions, the photolithography and etching process for the ONO stacked dielectric layer includes: A photoresist pattern is formed on the ONO stacked dielectric layer, so that the stacked capacitor region is covered by the photoresist rather than the capacitor region is exposed. An etching process is performed on the non-capacitor region to remove the sacrificial oxide layer in the non-capacitor region, thereby retaining the sacrificial oxide layer and the ONO stacked dielectric layer in the stacked capacitor region.

[0012] In some technical solutions, the etch mask layer used to form the photoresist pattern is defined in the layout design. In the layout of the etch mask layer, the stacked capacitor region is defined as a non-opening region, and the non-capacitor region is defined as an open region.

[0013] In some technical solutions, the equivalent thickness of the bottom oxide layer, which is composed of the sacrificial oxide layer and the lower oxide layer in the stacked capacitor region, is greater than the thickness of the bottom oxide layer, which is composed of only the lower oxide layer in the non-capacitor region on the semiconductor substrate.

[0014] According to a third aspect of the present invention, a high-voltage generating circuit is further provided, including at least one of the above-described stacked capacitors, the stacked capacitors being connected between potential nodes of the high-voltage generating circuit for charge storage and voltage smoothing at an operating voltage higher than the external power supply voltage of the chip, so as to generate an internal high-voltage voltage.

[0015] According to a fourth aspect of the present invention, a semiconductor memory device is further provided, comprising an array of memory cells formed on a semiconductor substrate, each memory cell comprising a gate dielectric structure having a lower oxide layer, a silicon nitride layer and an upper oxide layer stacked sequentially, wherein the silicon nitride layer is a charge trapping layer; And the aforementioned high-voltage generating circuit, which is configured to provide the memory cell array with the internal high-voltage voltage for memory cell programming and / or erasing operations.

[0016] In some technical solutions, the stacked capacitors in the high-voltage generation circuit share the process for forming the sacrificial oxide layer and the ONO stacked dielectric layer deposition process with the gate dielectric structure of the memory cell array. By not opening the stacked capacitor region in the photolithography and etching steps of the ONO stacked dielectric layer to retain the sacrificial oxide layer, the high voltage resistance of the bottom oxide layer of the stacked capacitor is improved relative to the gate dielectric structure.

[0017] The present invention, by employing the above technical solution, has at least the following beneficial effects: 1. This invention, by retaining a sacrificial oxide layer in the region of the stacked capacitor and using the sacrificial oxide layer and the lower oxide layer above it together as the bottom oxide layer, makes the equivalent thickness of the bottom oxide layer in this region significantly greater than the thickness of the bottom oxide layer in the non-capacitor region which is composed only of the lower oxide layer. This significantly improves the dielectric breakdown voltage and withstand voltage margin of the stacked capacitor. Under the same target withstand voltage requirement, the area required for a single capacitor unit can be reduced, thereby reducing the number of capacitor branches while meeting the circuit capacitance value requirements. This simplifies the topology and layout routing of the high voltage generation circuit, and helps to reduce the layout area and manufacturing cost of the high voltage generation circuit and even the entire chip.

[0018] 2. The proposed method for fabricating multilayer capacitors only adjusts the layout definition and photolithographic mask opening area in existing ONO multilayer dielectric layer processes: In the multilayer capacitor region, the region is defined as a non-opening region by using photoresist patterning and etching mask, so that the sacrificial oxide layer and the ONO multilayer on it are not opened or removed during the etching step; in the non-capacitor region, the sacrificial oxide layer is removed according to conventional processes. Therefore, this invention does not require additional high-voltage oxide layer deposition, extra annealing, or independent high-voltage capacitor modules. It achieves the dielectric thickness difference between the capacitor region and the ordinary device region only through mask layout and etching differentiation, offering advantages such as minimal process modification, easy direct implementation on existing SONOS or similar process lines, and no significant increase in process cost and complexity.

[0019] 3. In semiconductor memory devices employing a stacked gate dielectric of lower oxide / silicon nitride / upper oxide layer with the silicon nitride layer as the charge trapping layer, this invention achieves differentiated thickness design for memory cells and high-voltage capacitors by maintaining the original thin tunnel oxide layer structure in the memory cell region to meet programming, erasing, and data retention performance, and only by thickening the bottom oxide layer in the high-voltage capacitor region by retaining the sacrificial oxide layer. This allows for differentiated thickness design of the memory cells and high-voltage capacitors while sharing the sacrificial oxide layer formation process and ONO stacked deposition process. Consequently, when providing the internal high voltage for programming and erasing the memory cell array, the high-voltage generation circuit can rely on the stacked capacitors with higher voltage margin and better reliability to obtain a more stable high-voltage output and a lower failure rate, thereby improving the overall write / erase life, data retention capability, product consistency, and yield of the memory device. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings and their markings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of a conventionally designed multilayer capacitor; Figure 2 This is a schematic diagram of the structure of the multilayer capacitor described in an embodiment of the present invention; Figure 3 This is a flowchart of the method for preparing the multilayer capacitor according to an embodiment of the present invention; The meanings of the symbols marked in the figure are as follows: 10—Semiconductor substrate, 20—Lower electrode, 30—Sacrificial oxide layer, 40—ONO stacked dielectric layer, 50—Upper electrode. Detailed Implementation

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0023] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and these do not represent the actual structure of the product. Furthermore, to facilitate understanding, in some figures, only one of components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0024] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] In typical SONOS or similar processes, a sacrificial oxide layer is often formed before or during the formation of the ONO stack dielectric layer 40. This sacrificial oxide layer is generally formed on the surface of the active region of the semiconductor substrate and, in conventional process designs, is only used as a process aid layer in the subsequent photolithography and etching steps of the ONO stack dielectric layer 40, for example, to improve the etching interface, protect the substrate surface, or improve interface quality. In subsequent photolithography and etching steps, this sacrificial oxide layer is usually etched away along with part or all of the ONO stack and is ultimately not retained in the final device structure (e.g., ...). Figure 1In practice, when the process requires forming different gate dielectrics or tunneling structures in different regions, this is often achieved by opening mask openings in the corresponding regions and completely removing the sacrificial oxide layer and the dielectric layer on top of it. This common practice does not consider the possibility of selectively retaining the sacrificial oxide layer in certain functional regions and using it as part of the final dielectric structure. Based on this conventional process background, this invention, without changing the existing process modules, differentiates the use of the sacrificial oxide layer in the stacked capacitor region.

[0028] According to one embodiment of the present invention, such as Figure 2 A multilayer capacitor is provided, which is formed in a multilayer capacitor region of a semiconductor substrate 10. The multilayer capacitor in this region includes a sacrificial oxide layer 30 formed on the surface of the active region of the semiconductor substrate, and a lower oxide layer, a silicon nitride layer, and an upper oxide layer sequentially formed on the sacrificial oxide layer 30. The sacrificial oxide layer 30, the lower oxide layer, the silicon nitride layer, and the upper oxide layer together constitute the dielectric structure of the multilayer capacitor. In a preferred embodiment, the lower oxide layer is a silicon oxide layer, the silicon nitride layer is a charge trapping dielectric, and the upper oxide layer is a high-quality silicon oxide or other dielectric layer. The four dielectric layers are continuously stacked on the surface of the active region, such that the bottom oxide layer is composed of the sacrificial oxide layer 30 and the lower oxide layer connected in series, and the overall equivalent thickness is greater than that of the case where only the lower oxide layer is formed. In a specific implementation, a first conductive layer and a second conductive layer are respectively disposed on the upper and lower sides of the dielectric structure, and electrical insulation between the two is achieved through the dielectric structure. The first conductive layer is the upper electrode 50 located above the upper oxide layer, which may include a polysilicon electrode layer or metal interconnect wires covering the upper oxide layer. The second conductive layer is the lower electrode 20 located below the sacrificial oxide layer 30, which may include a doped active region, a well region in the semiconductor substrate 10, or a gate polysilicon layer formed below the sacrificial oxide layer 30. Through such an arrangement of upper and lower electrodes and dielectric stacking, the stacked capacitor has a dielectric thickness combination and electric field distribution suitable for high-voltage applications.

[0029] In a preferred embodiment, to obtain more stable electrical characteristics and withstand voltage margin, the present invention performs target design and precise control on the thickness of each layer in the dielectric structure. Specifically, the sacrificial oxide layer 30, the lower oxide layer, the silicon nitride layer, and the upper oxide layer each have a preset target thickness, wherein the target thickness of the sacrificial oxide layer 30 is greater than the target thickness of the lower oxide layer to ensure a significant increase in the high voltage withstand capability of the bottom oxide layer. In specific implementation, the deviation of the actual thickness of the lower oxide layer, the silicon nitride layer, and the upper oxide layer from their respective target thicknesses is controlled within a preset thickness tolerance range. For example, the deviation of the lower oxide layer is controlled within ±3 Å, the deviation of the silicon nitride layer is controlled within ±3 Å, and the deviation of the upper oxide layer is controlled within ±1 Å. Through strict thickness tolerance control, the thickness of each dielectric layer is made uniform in the large-area stacked capacitor region, which is beneficial to obtaining a more controllable electric field distribution and dielectric reliability.

[0030] According to another embodiment of the present invention, such as Figure 3 This provides a fabrication method based on the aforementioned multilayer capacitor structure. The fabrication method includes: First, a sacrificial oxide layer 30 is formed on the active region of the semiconductor substrate 10. The sacrificial oxide layer 30 can be formed by thermal oxidation or other oxidation processes and will be used as part of the bottom dielectric of the capacitor.

[0031] Secondly, after the sacrificial oxide layer 30 is formed, an ONO stacked dielectric layer 40 comprising a lower oxide layer, a silicon nitride layer, and an upper oxide layer is deposited on it. The lower oxide layer can be formed by thermal oxidation or chemical vapor deposition, and the silicon nitride layer and the upper oxide layer can be formed by corresponding thin film deposition processes, thereby obtaining an overall ONO stacked layer covering the stacked capacitor area and other device areas.

[0032] Next, the ONO stacked dielectric layer 40 is subjected to photolithography and etching processes to form different dielectric structures in different regions: the sacrificial oxide layer 30 and its lower oxide layer, silicon nitride layer and upper oxide layer are retained in the stacked capacitor region used to form the stacked capacitor, and the sacrificial oxide layer 30 is removed in the non-capacitor region different from the stacked capacitor region, thereby forming a dielectric structure of a stacked capacitor including the sacrificial oxide layer 30, the lower oxide layer, the silicon nitride layer and the upper oxide layer in the stacked capacitor region.

[0033] In a specific embodiment, a photoresist pattern can be formed on the ONO stacked dielectric layer 40, so that the stacked capacitor region is covered by photoresist and the non-capacitor region is exposed. An etching process is performed in the non-capacitor region to remove the sacrificial oxide layer 30 in the corresponding region, thereby naturally retaining the sacrificial oxide layer 30 and the ONO stacked dielectric layer 40 in the stacked capacitor region.

[0034] In the specific design, at the layout level, the etching mask layer used to form the photoresist pattern can be defined. Within this etching mask layer layout, the locations corresponding to the stacked capacitor regions are defined as non-opening regions, while opening patterns are only set at locations corresponding to non-capacitor regions. In the actual implementation, during the photolithography step, the stacked capacitor regions corresponding to the non-opening regions of the etching mask layer will be continuously covered by photoresist and will not be exposed or removed during the etching process. This ensures the complete preservation of the sacrificial oxide layer 30 and its ONO stack in the capacitor regions. In the non-capacitor regions, the sacrificial oxide layer 30 is removed in a conventional manner, making the stacked capacitors compatible with the surrounding device structure in terms of process technology but different in terms of dielectric thickness design.

[0035] In a preferred embodiment, the equivalent thickness of the bottom oxide layer, which is composed of the sacrificial oxide layer 30 and the lower oxide layer, is designed to be greater than the thickness of the bottom oxide layer, which is composed of only the lower oxide layer, in the non-capacitor region of the semiconductor substrate 10, so as to distinguish the stacked capacitor region from the ordinary device region in terms of withstand voltage capability.

[0036] Finally, conductive electrodes are formed on the upper and lower sides of the dielectric structure. In specific implementations, a polysilicon layer can be deposited and patterned above the upper oxide layer, or metal wires can be laid out in subsequent metal interconnect processes to cover the stacked capacitor region as the upper electrode 50 of the stacked capacitor; at the same time, a doped active region or well region is formed in the semiconductor substrate 10 below the sacrificial oxide layer 30, or a gate polysilicon layer is formed in an earlier process step to serve as the lower electrode 20 of the stacked capacitor.

[0037] Through the above steps, a multilayer capacitor with a dielectric structure consisting of a sacrificial oxide layer 30, a lower oxide layer, a silicon nitride layer, and an upper oxide layer is finally obtained. The equivalent thickness of the bottom oxide layer is significantly increased compared to conventional structures, making it suitable for on-chip high voltage applications.

[0038] According to another embodiment of the present invention, a high voltage generating circuit is further provided, which includes at least one stacked capacitor connected between two potential nodes of the high voltage generating circuit. The stacked capacitor is periodically charged and discharged and its potential is raised under the drive of an external power supply voltage, so as to generate an internal high voltage at at least one node that is higher than the external power supply voltage of the chip.

[0039] In practical implementation, this type of high-voltage generation circuit can employ a charge pump structure, with multilayer capacitors serving as pump capacitors or coupling capacitors, in conjunction with switching transistors, diodes, or other rectifier components, to achieve a step-by-step increase in internal node voltage. Because the equivalent thickness of the bottom oxide layer of the multilayer capacitors is increased and the dielectric thickness tolerance is strictly controlled, it exhibits higher dielectric breakdown voltage and better reliability under high-voltage operating conditions. Therefore, under the same internal high-voltage conditions, it is possible to reduce the area of ​​a single capacitor cell or reduce the number of series capacitor stages, which helps to reduce the layout area and topological complexity of the high-voltage generation circuit.

[0040] According to another embodiment of the present invention, a semiconductor memory device is further provided, including a memory cell array formed on a semiconductor substrate 10. Each memory cell includes a gate dielectric structure having a lower oxide layer, a silicon nitride layer and an upper oxide layer stacked sequentially. The silicon nitride layer serves as a charge trapping layer for storing charge states. The device also includes the aforementioned high-voltage generation circuit, which is configured to provide an internal high-voltage voltage to the memory cell array for programming and erasing operations.

[0041] In the specific design, the multilayer capacitors in the high-voltage generation circuit share the process for forming the sacrificial oxide layer 30 and the ONO multilayer dielectric layer 40 deposition process with the gate dielectric structure of the memory cell array. Furthermore, by not opening the multilayer capacitor region during the photolithography and etching steps of the ONO multilayer dielectric layer 40 to preserve the sacrificial oxide layer 30, the equivalent thickness of the bottom oxide layer in the multilayer capacitor, composed of the sacrificial oxide layer 30 and the lower oxide layer, is greater than the thickness of the bottom oxide layer in the memory cell gate dielectric structure, which is composed solely of the lower oxide layer. In practice, this differentiated thickness design allows the memory cell to retain a thin tunneling layer suitable for programming and erasing, while the multilayer capacitors in the high-voltage generation circuit achieve higher voltage withstand capability and reliability. Thus, without adding an additional high-voltage process module, both memory performance and the stability of the high-voltage generation circuit are simultaneously achieved.

[0042] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention, including the best mode, and also to enable any person skilled in the art to practice the present invention, including manufacturing and using any device or system, and implementing any combined method. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multilayer capacitor, characterized in that, The multilayer capacitor region formed on the semiconductor substrate includes: A sacrificial oxide layer formed on the surface of the active region of the semiconductor substrate; A lower oxide layer, a silicon nitride layer, and an upper oxide layer are sequentially formed on the sacrificial oxide layer. The sacrificial oxide layer, the lower oxide layer, the silicon nitride layer, and the upper oxide layer together constitute the dielectric structure of the stacked capacitor. And a first conductive layer and a second conductive layer respectively disposed on the upper and lower sides of the dielectric structure and electrically insulated from each other by the dielectric structure; The sacrificial oxide layer, which is originally designed to be removed in the subsequent photolithography and etching steps of the ONO stacked dielectric layer in conventional processes, is retained in this stacked capacitor as part of the dielectric structure to increase the high voltage resistance of the bottom oxide layer.

2. The multilayer capacitor according to claim 1, characterized in that, The sacrificial oxide layer, the lower oxide layer, the silicon nitride layer, and the upper oxide layer each have a preset target thickness, wherein the target thickness of the sacrificial oxide layer is greater than the target thickness of the lower oxide layer; and the deviation between the actual thickness of each dielectric layer and its corresponding target thickness is controlled as follows: lower oxide layer 18±3Å, silicon nitride layer 80±3Å, and upper oxide layer 45±1Å.

3. The multilayer capacitor according to claim 1, characterized in that, The first conductive layer is an upper electrode located above the upper oxide layer, including at least one of a polycrystalline silicon electrode layer covering the upper oxide layer and a metal interconnect wire; The second conductive layer is a lower electrode located below the sacrificial oxide layer, including at least one of a doped active region in the semiconductor substrate, a well region, and a gate polysilicon layer formed below the sacrificial oxide layer.

4. A method for preparing a multilayer capacitor, characterized in that, Includes the following steps: A sacrificial oxide layer is formed on the active region of the semiconductor substrate; An ONO stacked dielectric layer comprising a lower oxide layer, a silicon nitride layer, and an upper oxide layer is deposited on the sacrificial oxide layer. The ONO stacked dielectric layer is subjected to photolithography and etching processes. In the stacked capacitor region used to form the stacked capacitor, the sacrificial oxide layer and the lower oxide layer, silicon nitride layer and upper oxide layer thereon are retained. In the non-capacitor region different from the stacked capacitor region, the sacrificial oxide layer is removed, thereby forming the dielectric structure of the stacked capacitor including the sacrificial oxide layer, the lower oxide layer, the silicon nitride layer and the upper oxide layer in the stacked capacitor region. A first conductive layer and a second conductive layer are formed on the upper and lower sides of the dielectric structure, respectively, so that the first conductive layer and the second conductive layer are electrically insulated from each other through the dielectric structure to form a multilayer capacitor.

5. The preparation method according to claim 4, characterized in that, The photolithography and etching process for the ONO stacked dielectric layer includes: A photoresist pattern is formed on the ONO stacked dielectric layer, so that the stacked capacitor region is covered by the photoresist rather than the capacitor region is exposed. An etching process is performed on the non-capacitor region to remove the sacrificial oxide layer in the non-capacitor region, thereby retaining the sacrificial oxide layer and the ONO stacked dielectric layer in the stacked capacitor region.

6. The preparation method according to claim 5, characterized in that, In the layout design, the etch mask layer used to form the photoresist pattern is defined in the layout. In the layout of the etch mask layer, the stacked capacitor region is defined as the non-opening region, and the non-capacitor region is defined as the opening region.

7. The preparation method according to claim 4, characterized in that, The equivalent thickness of the bottom oxide layer in the stacked capacitor region, which is composed of the sacrificial oxide layer and the lower oxide layer, is greater than the thickness of the bottom oxide layer in the non-capacitor region of the semiconductor substrate, which is composed of only the lower oxide layer.

8. A high-voltage generating circuit, characterized in that, Includes at least one multilayer capacitor according to any one of claims 1 to 3 or a multilayer capacitor prepared by the preparation method according to any one of claims 4 to 7, wherein the multilayer capacitor is connected between potential nodes of the high voltage generation circuit for charge storage and voltage smoothing at an operating voltage higher than the external power supply voltage of the chip, so as to generate an internal high voltage.

9. A semiconductor memory device, characterized in that, The array includes a memory cell array formed on a semiconductor substrate, each memory cell including a gate dielectric structure having a lower oxide layer, a silicon nitride layer and an upper oxide layer stacked sequentially, wherein the silicon nitride layer is a charge trapping layer; And the high-voltage generating circuit according to claim 8, wherein the high-voltage generating circuit is configured to provide the memory cell array with the internal high-voltage voltage for memory cell programming and / or erasing operations.

10. The semiconductor memory device according to claim 9, characterized in that, The multilayer capacitor in the high-voltage generation circuit shares the process of forming a sacrificial oxide layer and the ONO multilayer dielectric layer deposition process with the gate dielectric structure of the memory cell array. By not opening the multilayer capacitor region in the photolithography and etching steps of the ONO multilayer dielectric layer to retain the sacrificial oxide layer, the high voltage resistance of the bottom oxide layer of the multilayer capacitor is improved relative to the gate dielectric structure.

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