Longitudinal power device preparation method and longitudinal power device
By fabricating a base NiO thin film and multiple photoresist layers in a vertical power device to form a cavity structure that is wider at the bottom and narrower at the top, and combining this with the slope design of the intermediate NiO thin film, the problem of poor high-voltage performance of the vertical power device is solved, and the electric field is dispersed and the high-voltage performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-07
AI Technical Summary
The design structure of existing vertical power devices at the junction of the anode edge and the NiO edge is unreasonable, resulting in poor high-voltage performance of the diodes, which are prone to premature breakdown under high voltage conditions.
A base NiO thin film is prepared on a Ga2O3 substrate. By setting different baking temperatures for the first and second photoresist layers, a cavity structure with a wider bottom and a narrower top is formed. An intermediate NiO thin film is prepared in the cavity, and its edges form a sloping structure. Combined with temperature gradient control of multiple photoresist layers, a multi-level gentle slope structure is formed to reduce electric field concentration.
It effectively reduces the peak electric field at the edge of the anode and the edge of the NiO film in the substrate, avoids premature breakdown of the diode, and significantly improves the high voltage performance and breakdown voltage of the diode.
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Figure CN121815673A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power semiconductor diode technology, and more specifically, relates to a method for fabricating a vertical power device and a vertical power device. Background Technology
[0002] Power devices include various types such as diodes and transistors. Vertical power devices refer to power semiconductor devices that adopt a vertical current structure. Gallium oxide power diodes have extremely high band gaps and theoretical critical breakdown electric fields, so they have broad application prospects in power semiconductor diodes. Heterojunction diodes, such as the combination of p-type oxide and Ga2O3, attempt to create high-performance normally-off diodes through heterojunction.
[0003] In traditional technology, due to the abrupt change in geometry at the junction of the anode edge and the NiO edge of the diode, the high voltage performance of the diode is poor. That is, under high voltage conditions, electric field accumulation is prone to occur at the junction of the anode edge and the NiO edge, causing the diode to break down prematurely before reaching the theoretical breakdown limit of the material. Summary of the Invention
[0004] The purpose of this application is to provide a method for fabricating a vertical power device and a vertical power device, which aims to solve the problem that the design structure of existing vertical power devices at the junction of the anode edge and the NiO edge is unreasonable, resulting in poor high voltage performance of the diode.
[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, a method for fabricating a vertical power device is provided, comprising: S100. A NiO thin film is prepared on the upper surface of a Ga2O3 substrate; S200. A first photoresist layer and a second photoresist layer are sequentially prepared on the uppermost NiO thin film, and the first photoresist layer and the second photoresist layer are baked respectively, wherein the baking temperature of the first photoresist layer is lower than the baking temperature of the second photoresist layer; S300. Pattern the first photoresist layer and the second photoresist layer, develop the first photoresist layer and the second photoresist layer, and form a cavity structure that is wider at the bottom and narrower at the top between the first photoresist layer and the second photoresist layer. S400. An intermediate NiO thin film is prepared in the cavity structure using a magnetron sputtering process, wherein the edge of the intermediate NiO thin film near the inner wall of the cavity structure is a sloping structure; the remaining first photoresist layer and the remaining second photoresist layer are removed. S500. An anode is prepared on the upper surface of the uppermost intermediate NiO thin film.
[0006] Compared with the prior art, the scheme shown in the embodiments of the present application has the first photoresist layer and the second photoresist layer arranged in the preparation process, the baking temperature of the first photoresist layer is lower than that of the second photoresist layer, so that the cavity region formed by the first photoresist layer is larger than the cavity region formed by the second photoresist layer after the first photoresist layer is exposed and developed, and a cavity structure with a lower width and a narrower upper width is formed; On this basis, when the intermediate layer NiO film is prepared in the cavity structure, the intermediate layer NiO film can be adapted to the shape of the inner wall of the cavity structure near the edge of the inner wall of the cavity structure, and a lower-wide and upper-narrow intermediate layer NiO film is formed, so that the edge of the intermediate layer NiO film presents a slope structure, so that a gentle slope structure can be formed between the edge of the anode and the base layer NiO film when the anode is prepared on the intermediate layer NiO film, instead of the traditional step structure, thereby effectively reducing the problem of electric field concentration; In addition, in the present application, the base layer NiO film is covered on the Ga2O3 substrate, which can produce an electric field modulation effect, spread and disperse the high electric field originally concentrated at the junction edge to a wider area, and reduce the problem of electric field concentration; Therefore, the longitudinal power device preparation method proposed in the present application can disperse the high electric field at the junction edge through the electric field modulation effect, effectively reduce the peak electric field at the edge of the anode and the edge of the base layer NiO film, avoid the premature breakdown of the diode, and significantly improve the breakdown voltage of the diode and the high-voltage performance of the diode.
[0007] In combination with the first aspect, in a possible implementation manner, the first photoresist layer is sequentially arranged in multiple layers from top to bottom, the baking temperature of each two adjacent layers of the first photoresist layer gradually decreases from top to bottom, and the baking temperature of the multiple layers of the first photoresist layer is all lower than the baking temperature of the second photoresist layer.
[0008] By arranging the multiple layers of the first photoresist layer in an up-down interval, the thickness of the lower layer of the first photoresist layer can be adjusted, the lower region of the cavity structure is larger, the cross-sectional area of the lower part of the slope structure of the intermediate layer NiO film formed is also larger, and the slope of the slope structure is more gentle, which is beneficial to the reduction of the peak electric field.
[0009] In addition, by gradually arranging the baking temperatures of the multiple layers of the first photoresist layer, it is beneficial to build a baking temperature gradient between the adjacent first photoresist layers, so that the cavity regions formed by the multiple layers of the first photoresist layer gradually decrease from bottom to top, which is beneficial to the reduction of the slope between the multiple layers of the first photoresist layer and further reduces the peak electric field.
[0010] In some embodiments, the difference between the baking temperature of the first photoresist layer close to the base layer NiO film and the baking temperature of the second photoresist layer is 20-60℃, and the difference between the baking temperatures of each two adjacent layers of the first photoresist layer is equal.
[0011] By reasonably controlling the baking temperature difference between two adjacent first photoresist layers, the cavity regions of the first photoresist layers between the two adjacent layers can be avoided from being too different, thereby avoiding the problem of excessive slope in the gentle slope structure and helping to avoid the problem of high electric field accumulation.
[0012] In conjunction with the first aspect, in one possible implementation, multiple layers of the first photoresist layer are sequentially arranged vertically, the baking temperature of each pair of adjacent first photoresist layers is equal, and the baking temperature of each of the multiple layers of the first photoresist layer is lower than the baking temperature of the second photoresist layer.
[0013] By making the baking temperatures of the two adjacent first photoresist layers equal, the baking process can be simplified and the diode fabrication efficiency improved, while ensuring that the cavity structure between the first and second photoresist layers is generally wider at the bottom and narrower at the top. This is suitable for diodes with low high-voltage performance requirements.
[0014] For example, the spin coating speed and baking time of the first photoresist layer and the second photoresist layer are equal, the spin coating speed is 2000-5000 rpm, and the baking time is 2-5 min.
[0015] By controlling the spin coating speed, it is beneficial to ensure the uniformity of the first and second photoresist layers. By controlling the baking time, it is beneficial to ensure the bonding and fixing effect after baking. Furthermore, by making the spin coating speed and baking time of the first and second photoresist layers equal, it is beneficial to ensure that the difference between the first and second photoresist layers is controlled by the baking temperature, achieving a single variable, thereby ensuring that the cavity area of the first photoresist layer is larger than that of the second photoresist layer.
[0016] In some embodiments, in step S300, the patterning exposure time is 5-20 seconds; when developing the first photoresist layer and the second photoresist layer, the developing solution used is a 1%-5% TMAH solution, and the developing time is 10-40 seconds.
[0017] By further refining the exposure time, concentration, and time of the developing solution for the first and second photoresist layers, it is beneficial to control the relative size of the cavity regions within the first and second photoresist layers, avoiding excessive or insufficient difference between the cavity regions of the upper and lower layers, which would affect the shape of the gentle slope structure.
[0018] In conjunction with the first aspect, in one possible implementation, after completing the removal of the residual first photoresist layer and the residual second photoresist layer, steps S200-S400 are repeated to obtain multiple layers of the intermediate NiO film. In each pair of adjacent intermediate NiO films, the upper surface area of the lower intermediate NiO film is not less than the lower surface area of the upper intermediate NiO film.
[0019] By preparing multilayer intermediate NiO films, a multi-level gentle slope structure can be formed at the edge of the anode and the edge of the base NiO film. Furthermore, the upper surface area of the lower intermediate NiO film is not less than the lower surface area of the upper intermediate NiO film, which can effectively realize the downward increasing trend of the multi-level gentle slope structure, further reduce the risk of high electric field concentration, and improve the high voltage performance of the diode.
[0020] For example, the slope of the slope structure formed by two adjacent intermediate NiO thin films is equal.
[0021] By making the slope of the slope structure formed by the intermediate NiO thin film of two adjacent layers equal, the slope tendency of the multi-level slope structure can be made equal, which is conducive to achieving the uniformity of the electric field distribution at each level, and further improving the breakdown voltage of the diode and the high voltage performance of the diode.
[0022] In conjunction with the first aspect, in one possible implementation, the base NiO film is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the base NiO film is 10 nm-100 nm. The intermediate NiO thin film is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the intermediate NiO thin film is 10nm-200nm.
[0023] By rationally setting the preparation process and thickness of the base NiO film and the intermediate NiO film, it is beneficial to further optimize the internal structure of the diode. The relatively small thickness of the base NiO film mainly achieves the modulation effect of the electric field, which is conducive to the dispersion of the high electric field on the base NiO film. The relatively thick thickness of the intermediate NiO film is conducive to the buffering and dispersion of the enhanced slope structure, further avoiding the problem of electric field concentration.
[0024] Secondly, this application also provides a vertical power device, fabricated using the above-described vertical power device fabrication method, wherein the vertical power device comprises: A Ga2O3 matrix with a cathode at the bottom; A NiO thin film is disposed on the upper surface of the Ga2O3 substrate; An intermediate NiO film is disposed on the upper surface of the base NiO film, and the circumferential edge of the intermediate NiO film has a sloping structure that is wider at the bottom and narrower at the top. The anode is disposed on the upper surface of the intermediate NiO thin film.
[0025] The vertical power device provided in this application, because it is fabricated using the above-described vertical power device fabrication method, has all the beneficial effects of the above-described vertical power device fabrication method. It can effectively reduce the peak electric field at the edge of the anode and the edge of the NiO thin film, thereby effectively reducing the problem of electric field concentration and optimizing the high voltage performance of the diode. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the structure of the vertical power device fabrication method provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of a vertical power device provided in an embodiment of this application.
[0028] In the figure: 1. Ga2O3 substrate; 2. Ga2O3 epitaxial layer; 3. NiO thin film as the base layer; 4. First photoresist layer; 5. Second photoresist layer; 7. Cavity structure; 8. Intermediate NiO thin film; 9. Anode; 10. Cathode. Detailed Implementation
[0029] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0030] It should be noted that when an element is referred to as being "set on" another element, it can be directly on or indirectly on that other element. It should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0031] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0032] It should be noted that in the existing technology, the structure of the vertical power device forms a stepped structure at the edge of the formed anode 9 and the edge of the NiO thin film, which causes abrupt changes in geometry. Therefore, under high voltage, an electric field will accumulate at the stepped structure, causing the diode to break down prematurely. As a result, its actual breakdown voltage is low and its high voltage performance is poor.
[0033] For the sake of simplicity, the term "diode" is used in this application to refer to "vertical power device" for ease of description.
[0034] Please see Figure 1 The fabrication method and the vertical power device provided in this application are now described. The fabrication method of the vertical power device includes the following steps: S100. A NiO thin film 3 is prepared on the upper surface of a Ga2O3 substrate. For details, please refer to the appendix to this application. Figure 1 (a); S200. A first photoresist layer 4 and a second photoresist layer 5 are sequentially prepared on the uppermost NiO thin film. The first photoresist layer 4 and the second photoresist layer 5 are baked respectively, and the baking temperature of the first photoresist layer 4 is lower than that of the second photoresist layer 5. For details, please refer to the appendix to this application. Figure 1 (b); S300. Patterning exposure of the first photoresist layer 4 and the second photoresist layer 5, development of the first photoresist layer 4 and the second photoresist layer 5, forming a cavity structure 7 that is wider at the bottom and narrower at the top between the first photoresist layer 4 and the second photoresist layer 5, as detailed in the appendix to this application. Figure 1 (c); S400. An intermediate NiO film 8 is prepared within the cavity structure 7 using magnetron sputtering. The edge of the intermediate NiO film 8 near the inner wall of the cavity structure 7 has a sloping structure. For details, please refer to the appendix to this application. Figure 1 (d); Remove residual first photoresist layer 4 and residual second photoresist layer 5, as detailed in the appendix to this application. Figure 1 (e); S500. An anode 9 is fabricated on the upper surface of the uppermost intermediate NiO thin film 8, as detailed in the appendix to this application. Figure 1 (f).
[0035] It should be noted that the base NiO film 3 in this application is covered on the upper surface of the Ga2O3 substrate and its upper surface is fully covered to achieve the modulation effect of the electric field, so as to disperse the electric field to the coverage area of the base NiO film 3.
[0036] Specifically, the Ga2O3 substrate in this application includes a Ga2O3 substrate 1 and a Ga2O3 epitaxial layer 2, wherein the Ga2O3 substrate 1 is disposed below the Ga2O3 epitaxial layer 2, the Ga2O3 epitaxial layer 2 is located on the upper surface of the Ga2O3 substrate 1, and the lower surface of the Ga2O3 substrate 1 is used to deposit cathode metal to form a cathode 10.
[0037] Furthermore, the specific preparation time of the cathode 10 can be selectively set according to actual needs; for example, before performing step S100, the cathode 10 is first prepared on the lower surface of the Ga2O3 substrate 1; for example, after completing step S500, the cathode 10 is finally prepared on the lower surface of the Ga2O3 substrate 1.
[0038] It should be noted that, under their respective standard developing conditions, the development and etching rate of low-temperature photoresists in the exposed area is generally much higher than that of high-temperature photoresists. This is because low-temperature photoresists form simpler polymer chains, mostly linear structures, with weak intermolecular forces, while high-temperature photoresists have complex structures, high cross-linking degrees, and strong intermolecular forces. The simpler, looser chain structure is more easily penetrated and etched by the developer; therefore, the developer etches low-temperature photoresists faster than it etches high-temperature photoresists.
[0039] In addition, the purpose of baking the photoresist is to remove the solvent in the photoresist layer, improve the adhesion between the photoresist and the substrate and the resistance of the photoresist film to mechanical damage, thereby improving the adhesion of the photoresist on the substrate. Since the baking temperature of the first photoresist layer 4 is relatively low, the solvent removal is not thorough enough, and the adhesion to the Ga2O3 substrate is relatively weak. It is more easily etched during the development process. Therefore, the lower part of the cavity structure 7 formed by the first photoresist layer 4 is larger, so that the cavity structure 7 formed as a whole presents a shape that is wider at the bottom and narrower at the top.
[0040] In layman's terms, the cavity structure 7 has a narrow upper cavity and a wide lower cavity. The wide cavity is defined as including a central region and an annular region. The central region corresponds vertically to the narrow cavity, and the annular region is arranged around the outer edge of the central region. It should be noted that the NiO target material used for sputtering is often placed directly above the narrow cavity, and its cross-sectional area is often larger than the area of the narrow cavity. Furthermore, the specific process and principle of this sputtering process are existing technologies and will not be elaborated here.
[0041] When preparing the intermediate NiO film 8 using magnetron sputtering within the cavity structure 7, which is narrow at the top and wide at the bottom, the sputtered NiO molecules need to enter the lower wide cavity from the upper narrow cavity of the cavity structure 7, and the deposition path is often straight. Therefore, the NiO target material used for sputtering often deposits directly into the central region from the upper narrow cavity, while the deposition path of other parts of the NiO target material is inclined towards the annular region. Furthermore, when depositing NiO in the wide cavity, the cross-sectional area is smaller closer to the narrow cavity and larger farther away from the narrow cavity. Therefore, the edge of the formed intermediate NiO film 8 can be regarded as a slope shape or an approximate slope shape.
[0042] Specifically, in step S300, a lithography machine can be used to pattern and expose the first photoresist layer 4 and the second photoresist layer 5.
[0043] It should be noted that during the patterning exposure process, a photoresist pattern can be formed on the first photoresist layer 4 and the second photoresist layer 5 for development by a developing solution. When developing the photoresist pattern, the first photoresist layer 4 is baked at a low temperature, so it is easily etched by the developing solution and the lower wide portion of the cavity structure 7 can be formed quickly. However, the second photoresist layer 5 is baked at a high temperature, so the formation speed is slower. Therefore, the formation speed of the photoresist pattern is slower. Before the second photoresist layer 5 forms a photoresist pattern, the first photoresist layer has already formed a photoresist pattern. Therefore, a cavity structure 7 that is wider at the bottom and narrower at the top can be formed.
[0044] In addition, when there is only one intermediate NiO film 8 to be set, the "uppermost NiO film" in step S200 is the base NiO film 3, and the "uppermost intermediate NiO film 8" in step S500 is the only "intermediate NiO film 8".
[0045] Specifically, when preparing the anode 9, a photolithography process can be used to prepare the anode 9 pattern on the uppermost intermediate NiO thin film 8, and then evaporate the metal layer, which can be a Ni / Au metal layer with a Ni metal thickness of 20-100nm and an Au thickness of 50-400nm. Then, the anode 9 is stripped in a metal stripping solution to remove the adhesive.
[0046] For example, when preparing the cathode 10, a metal layer can be directly evaporated on the lower surface of the Ga2O3 substrate to form the cathode 10. Specifically, it can be a Ti / Au metal layer with a Ti metal thickness of 20-100 nm and an Au thickness of 50-400 nm.
[0047] In step S400, it is necessary to remove the residual first photoresist layer 4 and the residual second photoresist layer 5. The specific removal solution can be selected according to actual needs. Preferably, the residual first photoresist layer 4 and the residual second photoresist layer 5 are removed by a photoresist remover.
[0048] Compared with the prior art, the vertical power device fabrication method provided in this application includes a first photoresist layer 4 and a second photoresist layer 5 during the fabrication process. By making the baking temperature of the first photoresist layer 4 lower than that of the second photoresist layer 5, the cavity region formed at the first photoresist layer 4 after patterning exposure and development is larger than the cavity region formed at the second photoresist layer 5, thereby forming a cavity structure 7 that is wider at the bottom and narrower at the top.
[0049] Based on this, when preparing the intermediate NiO film 8 in the cavity structure 7, the edge of the intermediate NiO film 8 near the inner wall of the cavity structure 7 can be adapted to the shape of the inner wall of the cavity structure 7, forming an intermediate NiO film 8 that is wider at the bottom and narrower at the top. This makes the edge of the intermediate NiO film 8 present a sloping structure, so that when preparing the anode 9 on the intermediate NiO film 8, a gentle slope structure can be formed between the edge of the anode 9 and the base NiO film 3, replacing the traditional stepped structure, thereby effectively reducing the problem of electric field concentration.
[0050] In addition, in this application, a NiO thin film 3 is coated on the Ga2O3 substrate, which can generate an electric field modulation effect, spreading the high electric field that was originally concentrated at the junction edge to a wider area, thus reducing the problem of electric field concentration.
[0051] Therefore, the vertical power device fabrication method proposed in this application can disperse the high electric field at the junction edge through electric field modulation, and can effectively reduce the peak electric field at the edge of the anode 9 and the edge of the NiO thin film 3, thus avoiding premature breakdown of the diode and significantly improving the diode breakdown voltage and high voltage performance.
[0052] Please see Figure 1 (b)- Figure 1 (e) In some possible embodiments, multiple layers of the first photoresist layer 4 are sequentially disposed above and below each other, and the baking temperature of each two adjacent first photoresist layers 4 gradually decreases from top to bottom, and the baking temperature of each of the multiple first photoresist layers 4 is lower than the baking temperature of the second photoresist layer 5.
[0053] By setting multiple layers of first photoresist 4 at intervals, the thickness of the lower first photoresist layer 4 can be adjusted, resulting in a larger lower region of the cavity structure 7. The lower cross-sectional area of the slope structure of the intermediate NiO thin film 8 is also larger, and the slope of the slope structure is gentler, which is conducive to reducing the peak electric field.
[0054] In addition, by setting the baking temperature of the multilayer first photoresist layer 4 step by step, it is beneficial to build a baking temperature gradient between adjacent first photoresist layers 4, so that the cavity area formed by the multilayer first photoresist layer 4 gradually decreases from bottom to top, which helps to ease the slope between the multilayer first photoresist layers 4 and further reduce the peak electric field.
[0055] Optionally, the first photoresist layer 4 is provided with 2-5 layers to increase the thickness of the lower half of the cavity structure 7, thereby making the lower half of the intermediate NiO film 8 have a larger cross-sectional width.
[0056] Preferably, the first photoresist layer 4 has two layers and the second photoresist layer 5 has one layer.
[0057] Since the baking temperature of each pair of adjacent first photoresist layers 4 gradually decreases from top to bottom, and the baking temperature of multiple first photoresist layers 4 is lower than that of the second photoresist layer 5, the baking temperature of the second photoresist layer 5 is the highest, and the baking temperature of multiple first photoresist layers 4 gradually decreases in the direction close to the Ga2O3 substrate.
[0058] In some embodiments, the baking temperature difference between the first photoresist layer 4 near the base NiO thin film 3 and the baking temperature of the second photoresist layer 5 is 20-60°C; the baking temperature difference between any two adjacent first photoresist layers 4 is equal.
[0059] By reasonably controlling the baking temperature difference between two adjacent first photoresist layers 4, the cavity regions of the first photoresist layers 4 between the two adjacent layers can be avoided from being too different, thereby avoiding the problem of excessive slope in the gentle slope structure and helping to avoid the problem of high electric field accumulation.
[0060] It should be noted that the baking temperature of the second photoresist layer 5 in this application is the baking temperature of a conventional photoresist layer, typically between 90-110°C; the baking temperature of the first photoresist layer 4 is lower than that of the second photoresist layer 5, so as to form a temperature difference between the baking temperatures of the first photoresist layer 4 and the second photoresist layer 5.
[0061] In addition, the baking temperature difference between the first photoresist layer 4 and the second photoresist layer 5 near the NiO thin film 3 is 20-60℃, which can limit the lower limit of the baking temperature of the first photoresist layer 4, avoid the baking temperature being too low, which would affect the adhesion between the first photoresist layer 4 and the Ga2O3 substrate, and avoid the problem of forming failure due to the delamination of the first photoresist layer 4 during the formation of the cavity structure 7.
[0062] Furthermore, increasing the temperature of each layer at equal intervals may allow for a gradual release of stress, resulting in more optimized interfacial bonding. This prevents the multilayer structure from curling or delaminating due to thermal stress and avoids the development process being affected by quality issues with the first photoresist layer 4.
[0063] In some possible embodiments, multiple layers of the first photoresist layer 4 are sequentially disposed vertically, the baking temperature of each two adjacent first photoresist layers 4 is equal, and the baking temperature of each of the multiple first photoresist layers 4 is lower than the baking temperature of the second photoresist layer 5.
[0064] By making the baking temperatures of the two adjacent first photoresist layers 4 equal, the baking process can be simplified and the diode fabrication efficiency improved, while ensuring that the cavity structure 7 between the first photoresist layer 4 and the second photoresist layer 5 is generally wider at the bottom and narrower at the top. This is suitable for diodes with low high voltage performance requirements.
[0065] It should be noted that the main purpose of this application is to form a baking temperature difference between the first photoresist layer 4 and the second photoresist layer 5 to form a cavity structure 7 that is wider at the bottom and narrower at the top, so as to adjust the slope angle of the formed intermediate NiO thin film 8. As for the relative temperature difference between the first photoresist layers 4, a slope transition can be further formed between the multiple layers of first photoresist layers 4 to form a multi-slope transition structure, thereby further adjusting the edge electric field. This design method is mainly for diodes with higher high voltage performance requirements and more stringent requirements for edge electric field distribution.
[0066] In this embodiment, based on the cavity structure 7 that is wider at the bottom and narrower at the top already formed between the first photoresist layer 4 and the second photoresist layer 5, this embodiment provides multiple layers of the first photoresist layer 4 with equal baking temperatures. The thickness of the lower half of the cavity structure 7 can be adjusted, thereby changing the overall thickness of the intermediate NiO film 8. In this embodiment, the concentration of the edge electric field can still be effectively reduced, but it is more suitable for scenarios with general high voltage performance requirements.
[0067] For example, the spin coating speed and baking time of the first photoresist layer 4 and the second photoresist layer 5 are equal, with the spin coating speed being 2000-5000 rpm and the baking time being 2-5 min.
[0068] By controlling the spin coating speed, it is beneficial to ensure the uniformity of the first photoresist layer 4 and the second photoresist layer 5. By controlling the baking time, it is beneficial to ensure the bonding and fixing effect after baking. Furthermore, by making the spin coating speed and baking time of the first photoresist layer 4 and the second photoresist layer 5 equal, it is beneficial to ensure that the difference between the first photoresist layer 4 and the second photoresist layer 5 is controlled by the baking temperature, achieving a single variable, thereby ensuring that the cavity area of the first photoresist layer 4 is larger than the cavity area of the second photoresist layer 5.
[0069] Specifically, by controlling the spin-coating speed of the first photoresist layer 4 and the second photoresist layer 5 to be equal, it can be ensured that the first photoresist layer 4 and the second photoresist layer 5 have the same or very similar initial physical states, that is, consistent in film thickness, uniformity, and initial solvent content.
[0070] In addition, by controlling the baking time to be equal, the consistency of the heat budget in the time dimension can be ensured.
[0071] Therefore, controlling the baking time and spin coating speed can eliminate key variables affecting the development process, ensuring that the size change of the etched area during development is caused by the difference in baking temperature, rather than by the spin coating process itself or the baking time, thereby achieving controllability of the etched area.
[0072] In some embodiments, in step S300, the patterning exposure time of the lithography machine is 5-20 seconds; when developing the first photoresist layer 4 and the second photoresist layer 5, the developing solution used is 1%-5% TMAH solution, and the developing time is 10-40 seconds.
[0073] By further refining the exposure time, concentration and time of the developing solution of the first photoresist layer 4 and the second photoresist layer 5, it is beneficial to control the relative size of the cavity regions in the first photoresist layer 4 and the second photoresist layer 5, and avoid the cavity regions of the upper and lower layers being too different or too small, which would affect the shape of the gentle slope structure.
[0074] It should be noted that TMAH solution is an aqueous solution of tetramethylammonium hydroxide, a strongly alkaline organic compound that can be used in the semiconductor industry as a chemical polishing agent, developer, and cleaning agent.
[0075] Using 1%-5% diluted TMAH, instead of the standard 2.38%, and combined with a shorter development time of 10-40 seconds, high-contrast, low-defect-rate pattern transfer can be achieved. Specifically, the diluted developer slows down the reaction rate, resulting in a wider process window. Furthermore, at this concentration, the development process is less sensitive to minor fluctuations in exposure, making it easier to obtain steep, smooth sidewalls and reducing the risk of erosion of the underlying NiO film.
[0076] Furthermore, the aforementioned development environment needs to be precisely matched with the exposure time in the embodiments of this application. Insufficient exposure time may result in incomplete development under the aforementioned development conditions, while excessive exposure time may lead to pattern shrinkage or overdevelopment.
[0077] Furthermore, after developing the first photoresist layer 4 and the second photoresist layer 5, fixing and drying processes are performed on the first photoresist layer 4 and the second photoresist layer 5. The fixing solution used is deionized water, and the fixing time is 20-50 seconds. The drying process includes introducing nitrogen gas into the photoresist pattern to dry the residual liquid in the photoresist pattern.
[0078] In some possible embodiments, after removing the residual first photoresist layer 4 and the residual second photoresist layer 5, steps S200-S400 are repeated to obtain a multilayer intermediate NiO film 8; in each pair of adjacent intermediate NiO films 8, the upper surface area of the lower intermediate NiO film 8 is not less than the lower surface area of the upper intermediate NiO film 8.
[0079] It should be noted that after each cycle, a new, patterned intermediate NiO film 8 can be fabricated on the upper NiO film. This process is repeated n times to finally obtain n stacked intermediate NiO films 8.
[0080] Preferably, the total number of layers of the prepared intermediate NiO film 8 is 1-5; specifically, the specific number of layers of the intermediate NiO film 8 can be selectively set according to actual needs.
[0081] By preparing a multilayer intermediate NiO film 8, a multi-level gentle slope structure can be formed at the edge of the anode 9 and the edge of the base NiO film 3. Furthermore, the upper surface area of the lower intermediate NiO film 8 is not less than the lower surface area of the upper intermediate NiO film 8, which can effectively realize the downward increasing trend of the multi-level gentle slope structure, further reduce the risk of high electric field concentration, and improve the high voltage performance of the diode.
[0082] It should be understood that when repeating steps S200-S400, the "uppermost NiO film" in step S200 refers to the uppermost intermediate NiO film 8, which is the intermediate NiO film 8 furthest from the Ga2O3 substrate among the multiple intermediate NiO films 8; in addition, the "uppermost intermediate NiO film 8" in step S500 refers to the uppermost "intermediate NiO film 8" among the multiple intermediate NiO films 8, which can also be understood as the intermediate NiO film 8 furthest from the Ga2O3 substrate.
[0083] For example, the slope of the slope structure formed by the two adjacent intermediate NiO thin films 8 is equal.
[0084] By making the slope of the slope structure formed by the intermediate NiO thin film 8 of two adjacent layers equal, the slope tendency of the multi-level slope structure can be made equal, which is conducive to achieving the uniformity of the electric field distribution at each level, and is conducive to further improving the breakdown voltage of the diode and improving the high voltage performance of the diode.
[0085] By ensuring that the tilt angles of the multilayer intermediate NiO films 8 are equal, a stable and consistent interface can be provided for the subsequent coating process on the upper NiO film, which is the basis for achieving the repeatability of the multilayer process. In addition, it can ensure that the deformation and shrinkage of each intermediate NiO film 8 are consistent, thereby ensuring the consistency of stress distribution of the multilayer intermediate NiO films 8, and thus improving the overall stress uniformity of the diode.
[0086] In some possible embodiments, the base NiO film 3 is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the base NiO film 3 is 10nm-100nm; the intermediate NiO film 8 is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the intermediate NiO film 8 is 10nm-200nm.
[0087] By rationally setting the preparation process and thickness of the base NiO film 3 and the intermediate NiO film 8, it is beneficial to further optimize the internal structure of the diode. The relatively small thickness of the base NiO film 3 mainly achieves the modulation effect of the electric field, which is conducive to the dispersion of the high electric field on the base NiO film 3. The relatively thick thickness of the intermediate NiO film 8 is conducive to the buffering and dispersion of the enhanced slope structure, further avoiding the problem of electric field concentration.
[0088] It is important to understand that the NiO thin film 3 is the foundational platform and the first conductive functional layer of the entire diode. Its thickness is no less than the lower limit of 10 nm to ensure film continuity, absence of pinholes, and good electrical or functional properties, such as resistive switching and catalytic activity. Its thickness does not exceed the upper limit of 100 nm to control the stress of the substrate and prevent excessive thickness from leading to decreased adhesion to the substrate or self-cracking. At the same time, the thickness of the NiO thin film 3 also sets the initial height reference for subsequent stacking.
[0089] The intermediate NiO film 8 has a wider range of thicknesses, providing design flexibility. This means that functional gradients can be achieved by selecting different thicknesses for different layers. For example, the bottom intermediate NiO film 8 can be designed to be thicker to carry current, while the top intermediate NiO film 8 can be designed to be thinner to achieve fast switching.
[0090] Based on the same inventive concept, please refer to Figure 2This application also provides a vertical power device, which is fabricated using the above-described vertical power device fabrication method. The vertical power device includes a Ga2O3 substrate, a base NiO film 3, an intermediate NiO film 8, and an anode 9. A cathode 10 is disposed at the bottom of the Ga2O3 substrate. The base NiO film 3 is disposed on the upper surface of the Ga2O3 substrate. The intermediate NiO film 8 is disposed on the upper surface of the base NiO film 3, and the circumferential edge of the intermediate NiO film 8 has a sloping structure that is wider at the bottom and narrower at the top. The anode 9 is disposed on the upper surface of the intermediate NiO film 8.
[0091] Furthermore, the intermediate NiO film 8 is provided in multiple layers, with the multiple intermediate NiO films 8 arranged sequentially from bottom to top, and the anode 9 is disposed on the uppermost intermediate NiO film 8.
[0092] In addition, the tilt angles of the slope structures on the multilayer intermediate NiO thin film 8 can be equal or unequal, and the specific tilt angles of the slope structures can be selectively set according to actual needs.
[0093] The vertical power device provided in this application, because it is fabricated using the above-described vertical power device fabrication method, has all the beneficial effects of the above-described vertical power device fabrication method. It can effectively reduce the peak electric field at the edge of the anode 9 and the edge of the NiO thin film 3, thereby effectively reducing the problem of electric field concentration and optimizing the high voltage performance of the diode.
[0094] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for fabricating a vertical power device, characterized in that, include: S100. A base NiO thin film is prepared on the upper surface of a Ga2O3 substrate (3); S200. A first photoresist layer (4) and a second photoresist layer (5) are sequentially prepared on the uppermost NiO thin film, and the first photoresist layer (4) and the second photoresist layer (5) are baked respectively, and the baking temperature of the first photoresist layer (4) is lower than the baking temperature of the second photoresist layer (5); S300. Pattern the first photoresist layer (4) and the second photoresist layer (5), develop the first photoresist layer (4) and the second photoresist layer (5), and form a cavity structure (7) that is wider at the bottom and narrower at the top between the first photoresist layer (4) and the second photoresist layer (5). S400. An intermediate NiO film (8) is prepared in the cavity structure (7) by magnetron sputtering. The edge of the intermediate NiO film (8) near the inner wall of the cavity structure (7) is a slope structure. The remaining first photoresist layer (4) and the remaining second photoresist layer (5) are removed. S500. An anode (9) is prepared on the upper surface of the uppermost intermediate NiO thin film (8).
2. The method for fabricating a vertical power device as described in claim 1, characterized in that, The first photoresist layer (4) is arranged in multiple layers in sequence. The baking temperature of each two adjacent first photoresist layers (4) gradually decreases from top to bottom, and the baking temperature of each of the multiple first photoresist layers (4) is lower than the baking temperature of the second photoresist layer (5).
3. The method for fabricating a vertical power device as described in claim 2, characterized in that, The baking temperature difference between the first photoresist layer (4) near the base NiO film (3) and the baking temperature of the second photoresist layer (5) is 20-60°C; the baking temperature difference between any two adjacent first photoresist layers (4) is equal.
4. The method for fabricating a vertical power device as described in claim 1, characterized in that, The first photoresist layer (4) is arranged in multiple layers in sequence. The baking temperature of each two adjacent first photoresist layers (4) is equal, and the baking temperature of each of the multiple first photoresist layers (4) is lower than the baking temperature of the second photoresist layer (5).
5. The method for fabricating a vertical power device according to any one of claims 2-4, characterized in that, The spin coating speed and baking time of the first photoresist layer (4) and the second photoresist layer (5) are equal, the spin coating speed is 2000-5000 rpm, and the baking time is 2-5 min.
6. The method for fabricating a vertical power device as described in claim 5, characterized in that, In step S300, the patterning exposure time is 5-20 seconds; when developing the first photoresist layer (4) and the second photoresist layer (5), the developing solution used is 1%-5% TMAH solution, and the developing time is 10-40 seconds.
7. The method for fabricating a vertical power device as described in claim 1, characterized in that, After completing the removal of the residual first photoresist layer (4) and the residual second photoresist layer (5), repeat steps S200-S400 to obtain the multilayer intermediate NiO film (8). In each pair of adjacent intermediate NiO films (8), the upper surface area of the lower intermediate NiO film (8) is not less than the lower surface area of the upper intermediate NiO film (8).
8. The method for fabricating a vertical power device as described in claim 7, characterized in that, The slope of the slope structure formed by the two adjacent intermediate NiO thin films (8) is equal.
9. The method for fabricating a vertical power device as described in claim 1, characterized in that, The base NiO film (3) is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the base NiO film (3) is 10nm-100nm. The intermediate NiO film (8) is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the intermediate NiO film (8) is 10nm-200nm.
10. A vertical power device, characterized in that, The vertical power device is fabricated using the method described in any one of claims 1-9, wherein the vertical power device comprises: A Ga2O3 substrate with a cathode (10) at the bottom; A NiO thin film (3) is disposed on the upper surface of the Ga2O3 substrate; An intermediate NiO film (8) is disposed on the upper surface of the base NiO film (3), and the circumferential edge of the intermediate NiO film (8) is a sloping structure that is wider at the bottom and narrower at the top. The anode (9) is disposed on the upper surface of the intermediate NiO thin film (8).