Longitudinal power device preparation method and longitudinal power device
By fabricating multiple dielectric layers and forming a cavity structure in a vertical power device, the problem of electric field accumulation in the vertical power device is solved, and the high electric field is dispersed and the slope transition is achieved, thereby improving the breakdown voltage and high voltage performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-07
AI Technical Summary
In the prior art, vertical power devices have abrupt geometric changes at the junction of the anode edge and the NiO edge, which leads to electric field accumulation and limits the high voltage performance of the diode.
By preparing a multilayer dielectric layer on a Ga2O3 substrate and utilizing the difference in corrosion rate of different etchants to form a cavity structure between the multilayer dielectric layers, a NiO thin film in the middle layer is prepared to form a slope structure and alleviate the electric field accumulation.
It effectively reduces the peak electric field at the anode edge and NiO edge, avoids premature diode breakdown, and significantly improves the breakdown voltage and high voltage performance of vertical power devices.
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Figure CN121815674A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of power semiconductor diodes, and more particularly to a longitudinal power device preparation method and a longitudinal power device. BACKGROUND
[0002] Power semiconductor devices with vertical current structure are collectively referred to as longitudinal power devices. Gallium oxide power diodes have the advantages of high breakdown, low on-resistance and low cost, and are widely used in high-voltage and high-power power systems. Gallium oxide longitudinal power devices (such as p-NiO / n-Ga2O3) are mainly used in application scenarios with higher requirements for reliability, high-temperature performance and reverse recovery characteristics.
[0003] In the prior art, single-layer or multi-layer NiO is mainly used as a hetero p-type to form a p-NiO / n-Ga2O3 hetero PN junction. There is a geometric shape mutation at the junction between the anode edge of the diode and the NiO edge. Therefore, when high voltage is applied to the diode, electric field aggregation occurs at the junction edge. The local electric field at this point is much higher than the average electric field inside the diode, which causes the diode to break down prematurely before reaching the theoretical breakdown limit of the material, severely limiting the high-voltage performance of the diode. SUMMARY
[0004] The purpose of the present application is to provide a longitudinal power device preparation method and a longitudinal power device, which aims to solve the problem of geometric shape mutation at the junction between the anode edge and the NiO edge of the longitudinal power device in the prior art, and poor high-voltage performance of the diode.
[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present application is: In a first aspect, a longitudinal power device preparation method is provided, comprising: S100. Preparing a base layer NiO thin film on the upper surface of a Ga2O3 substrate; S200. Preparing a plurality of medium layers on the uppermost layer of the NiO thin film layer, which can be etched by a first etching liquid, and gradually reducing the etching rate of the plurality of medium layers away from the Ga2O3 substrate; S300. Preparing a photoresist pattern on the upper surface of the uppermost layer of the medium layer; S400. Injecting the first etching liquid into the photoresist pattern to etch the plurality of medium layers and form a lower-wide and upper-narrow cavity structure between the plurality of medium layers; S500. Preparing an intermediate layer NiO thin film in the cavity structure by a magnetron sputtering process, so that the edge of the intermediate layer NiO thin film close to the inner wall of the cavity structure is a slope structure; and removing the photoresist pattern and residual plurality of medium layers; S600. An anode is prepared on the upper surface of the uppermost intermediate NiO thin film.
[0006] Compared with the prior art, the solution shown in the embodiments of this application utilizes the characteristic that the multilayer dielectric layers have different corrosion rates under the action of the first etchant to form a cavity structure between the multilayer dielectric layers, so as to form an intermediate NiO film with a slope structure in the cavity structure, and form an anode on the intermediate NiO film. Therefore, in this application, a slope structure is formed between the upper surface of the intermediate NiO film and the upper surface of the base NiO film, that is, a gentle slope for transition. The gentle slope replaces the traditional step structure, avoiding abrupt changes in geometry and effectively reducing the electric field accumulation effect. In addition, the NiO thin film covering the upper surface of the Ga2O3 substrate can generate an electric field modulation effect, which disperses the high electric field originally concentrated at the junction edge to a wider area, and the process is simple and easy to implement. As can be seen, the vertical power device fabrication method provided in this application can achieve high electric field dispersion by modulating the electric field through the NiO thin film at the base layer. The NiO thin film in the middle layer can achieve a slope transition of the bonding shape, reduce the electric field accumulation effect caused by abrupt changes, effectively reduce the peak electric field at the anode edge and NiO edge, avoid premature diode breakdown, and significantly improve the diode breakdown voltage.
[0007] In conjunction with the first aspect, in one possible implementation, the base NiO film is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the base NiO film is 10 nm to 100 nm.
[0008] By using sputtering or thermal oxidation processes to prepare a base NiO film of suitable thickness, the modulation effect of the base NiO film can be guaranteed, and the high electric field can be dispersed.
[0009] In conjunction with the first aspect, in one possible implementation, the multilayer dielectric layer includes a silicon dioxide layer and a silicon nitride layer sequentially disposed on the base NiO film; The first corrosive solution is a BOE solution; Under the corrosive action of the BOE solution, the silicon nitride layer and the silicon dioxide layer are connected vertically to form the cavity structure.
[0010] By rationally designing the multilayer dielectric layers as silicon dioxide and silicon nitride layers, different corrosion rates can be obtained in BOE solution. Since the corrosion rate of silicon dioxide layer in BOE is greater than that of silicon nitride layer in BOE solution, a cavity structure that is narrow at the top and wide at the bottom can be formed.
[0011] In some embodiments, the thickness of the silicon dioxide layer is 50-2000 nm, and the thickness of the silicon nitride layer is 50-2000 nm.
[0012] By adjusting the thickness of the silicon dioxide layer and the silicon nitride layer, the tilt angle between the upper and lower parts of the cavity structure can be adjusted, thereby forming intermediate NiO films with different tilt angles.
[0013] For example, the removal of the photoresist pattern and residual multilayer dielectric layers includes: The photoresist pattern is stripped using a resist stripper. The residual silicon dioxide layer and silicon nitride layer are removed using a mixture of hot phosphoric acid and hydrofluoric acid.
[0014] The photoresist pattern is removed by stripping solution, residual silicon nitride is removed by hot phosphoric acid, and residual silicon dioxide is removed by hydrofluoric acid to avoid the influence of residual photoresist or dielectric layer on the diode.
[0015] In conjunction with the first aspect, in one possible implementation, the multilayer dielectric layer includes an indium tin oxide layer and an aluminum oxide layer sequentially disposed on the base NiO film; The first corrosive solution is a hydrochloric acid solution; Under the corrosive action of the hydrochloric acid solution, the indium tin oxide layer and the aluminum oxide layer are connected vertically to form the cavity structure.
[0016] By rationally designing the multilayer dielectric layer as an indium tin oxide layer and an aluminum oxide layer, different corrosion rates can be obtained in hydrochloric acid solution. Since the corrosion rate of the indium tin oxide layer in hydrochloric acid solution is greater than that of the aluminum oxide layer, a cavity structure that is narrow at the top and wide at the bottom can be formed.
[0017] In conjunction with the first aspect, in one possible implementation, the multilayer dielectric layer includes a zirconium oxide layer and a silicon dioxide layer sequentially disposed on the base NiO film; The first corrosive solution is a hot phosphoric acid solution; Under the corrosive action of the hot phosphoric acid solution, the zirconium oxide layer and the silicon dioxide layer are connected vertically to form the cavity structure.
[0018] Similarly, the zirconium oxide layer and the silicon dioxide layer have different corrosion rates in the hot phosphoric acid solution. Since the corrosion rate of the zirconium oxide layer in the hot phosphoric acid solution is greater than that of the silicon dioxide layer, a cavity structure that is narrow at the top and wide at the bottom can be formed.
[0019] In conjunction with the first aspect, in one possible implementation, steps S200-S500 are repeated sequentially on the intermediate NiO film obtained in step S500 to obtain multiple layers of the intermediate NiO film. Furthermore, in each pair of adjacent intermediate NiO films, the upper surface area of the lower intermediate NiO film is not less than the lower surface area of the upper intermediate NiO film.
[0020] By setting multiple intermediate NiO thin films, a transition structure with multiple sloping structures can be formed. By ensuring that the upper surface area of the lower intermediate NiO thin film is not less than the lower surface area of the upper intermediate NiO thin film, a large sloping structure composed of multiple sloping structures can be formed between the multiple intermediate NiO thin films. This is beneficial for the gradual dispersion of high electric fields and optimizes the performance of the diode.
[0021] In conjunction with the first aspect, in one possible implementation, the fabrication of a photoresist pattern on the upper surface of the uppermost dielectric layer includes: A photoresist layer is spin-coated onto the upper surface of the top dielectric layer and baked. The photoresist pattern is then obtained by patterning exposure using a photolithography machine, followed by development, fixing, and drying. The photoresist pattern extends downwards to the upper surface of the top dielectric layer.
[0022] The shape of the photoresist pattern determines the cross-sectional shape of the cavity structure etched downwards by the first etching solution. The photoresist pattern is obtained through patterning exposure, development, fixing and drying processes, which facilitates the etching of multiple dielectric layers downwards from the photoresist pattern.
[0023] Secondly, embodiments of this application also provide a vertical power device, fabricated using the above-described vertical power device fabrication method, wherein the vertical power device comprises: A Ga2O3 matrix with a cathode at the bottom; A NiO thin film is disposed on the upper surface of the Ga2O3 substrate; An intermediate NiO film is disposed on the upper surface of the base NiO film, and the circumferential edge of the intermediate NiO film has a sloping structure that is wider at the bottom and narrower at the top. The anode is disposed on the upper surface of the intermediate NiO thin film.
[0024] The vertical power device provided in this application, because it is fabricated using the above-described vertical power device fabrication method, has all the beneficial effects of the above-described vertical power device fabrication method. It can effectively reduce the peak electric field at the anode edge and NiO edge, avoid premature diode breakdown, significantly improve the breakdown voltage of the vertical power device, and optimize the high voltage performance of the vertical power device. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the structure of the vertical power device fabrication method provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of a vertical power device in the prior art.
[0027] In the figure: 1. Ga2O3 substrate; 2. Ga2O3 epitaxial layer; 3. Base layer NiO thin film; 4. Dielectric layer; 41. Silicon oxide layer; 42. Silicon nitride layer; 5. Photoresist layer; 7. Cavity structure; 8. Intermediate layer NiO thin film; 9. Anode; 10. Cathode; 11. First NiO thin film. Detailed Implementation
[0028] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0029] It should be noted that when an element is referred to as being "set on" another element, it can be directly on or indirectly on that other element. It should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0030] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0031] It should be noted that the appendix Figure 2The structure shown is the structure of a vertical power device in the prior art. After its fabrication, a stepped structure is formed at the edge of the anode 9 and the edge of the first NiO film 11. Therefore, when the diode is under high voltage, an electric field will accumulate at the junction edge of the diode, causing the diode to break down prematurely and resulting in poor high voltage performance.
[0032] For the sake of simplicity, the term "diode" is used in this application to refer to "vertical power device" for ease of description.
[0033] Please see Figure 1 The fabrication method and the vertical power device provided in this application are now described. The fabrication method of the vertical power device includes the following steps: S100. A NiO thin film 3 is prepared on the upper surface of a Ga2O3 substrate. (See Appendix for details.) Figure 1 (a); S200. A multi-layered dielectric layer 4, all of which can be etched by the first etchant, is prepared on the uppermost NiO thin film layer. The etching rate of the multi-layered dielectric layer 4 gradually decreases away from the Ga2O3 substrate. For details, please refer to the appendix. Figure 1 (b); S300. A photoresist pattern is prepared on the upper surface of the top dielectric layer 4. See Appendix for details. Figure 1 (c); S400. A first etchant is injected into the photoresist pattern to etch the multilayer dielectric layer 4, forming a cavity structure 7 that is wider at the bottom and narrower at the top between the multilayer dielectric layers 4. See Appendix for details. Figure 1 (d); S500. An intermediate NiO film 8 is prepared within the cavity structure 7 using magnetron sputtering, such that the edge of the intermediate NiO film 8 near the inner wall of the cavity structure 7 has a sloping structure. See Appendix for details. Figure 1 (e) Remove the photoresist pattern and residual multilayer dielectric layers 4. See Appendix for details. Figure 1 (f); S600. An anode 9 is fabricated on the upper surface of the uppermost intermediate NiO thin film 8, as detailed in the appendix. Figure 1 (g).
[0034] It should be noted that the Ga2O3 substrate used in this application actually includes a Ga2O3 substrate 1 and a Ga2O3 epitaxial layer 2; in addition, a cathode 10 is prepared on the lower surface of the Ga2O3 substrate. Optionally, the cathode 10 can be formed on the lower surface of the Ga2O3 substrate before the anode 9 is prepared, or it can be formed on the lower surface of the Ga2O3 substrate after the anode 9 is prepared. Specifically, the preparation time and specific steps of the cathode 10 can be selectively set according to actual needs.
[0035] A Ga2O3 epitaxial layer 2 is disposed on the upper surface of a Ga2O3 substrate 1; wherein, a base NiO thin film 3 is covered on the upper surface of the Ga2O3 epitaxial layer 2, and the base NiO thin film 3 completely covers the upper surface of the Ga2O3 epitaxial layer 2, so that the high electric field is completely dispersed on the Ga2O3 epitaxial layer 2, which can further alleviate the problem of electric field accumulation.
[0036] It should be noted that the selection of the multilayer dielectric layer 4 and the first etchant must meet two conditions: first, the multilayer dielectric layer 4 can be etched by the first etchant and form a cavity region; second, under the etchant action of the first etchant, the etch rate of the multilayer dielectric layer 4 gradually decreases in the direction away from the Ga2O3 substrate, so as to form etched regions of different sizes in each dielectric layer.
[0037] It is important to understand that, due to the different media in the multilayer dielectric layer 4 having different corrosion rates under the action of the first corrosive liquid, that is, some are fast and some are slow, the size of the corroded area in the same time period of different dielectric layers 4 is different. As the corrosion rate of the multilayer dielectric layer 4 gradually decreases in the direction away from the Ga2O3 substrate, this leads to the formation of multi-level corrosion areas of varying sizes in the different dielectric layers 4 in the direction away from the Ga2O3 substrate.
[0038] Specifically, when the corrosion rate of the multilayer dielectric layer 4 gradually decreases away from the Ga2O3 substrate, the corrosion area of the dielectric layer 4 near the Ga2O3 substrate is larger, while the corrosion area of the dielectric layer 4 away from the Ga2O3 substrate is smaller. Therefore, a cavity structure 7 with a large corrosion area at the bottom and a small corrosion area at the top can be formed between the multilayer dielectric layers 4, that is, a cavity structure 7 that is wider at the bottom and narrower at the top.
[0039] Based on this, when preparing the intermediate NiO film 8 in the cavity structure 7, due to the shape of the cavity structure 7 being wider at the bottom and narrower at the top, the intermediate NiO film 8 is also a solid that is wider at the bottom and narrower at the top after it is formed.
[0040] In fact, the formed entity can be understood as an entity with a sloping outer edge, or an entity with a sloping outer surface. Since the intermediate NiO film 8 is formed within the cavity structure 7, the shape of the cavity structure 7, which is narrower at the top and wider at the bottom, determines that the intermediate NiO film 8 is not a shape with equal cross-sectional area at the top and bottom during sputtering.
[0041] It is important to understand that the cavity structure 7 has a narrow upper cavity and a wide lower cavity. For ease of explanation, the wide cavity is defined as including a central region and an annular region, where the central region corresponds vertically to the narrow cavity, and the annular region is arranged around the outer edge of the central region. When preparing the intermediate NiO film 8 using magnetron sputtering within the upper-narrow and lower-wide cavity structure 7, the sputtered NiO molecules need to enter the lower wide cavity from the upper narrow cavity of the cavity structure 7, and the deposition path is often straight. Therefore, in the NiO target material used for sputtering, the part directly facing the upper narrow cavity is often deposited directly into the central region from the narrow cavity, while other parts of the NiO target material can often be sputtered at an angle into the annular region. Furthermore, in the formed intermediate NiO film 8, the cross-sectional area is smaller closer to the narrow cavity and larger farther away from the narrow cavity. Therefore, the edge of the formed intermediate NiO film 8 can be regarded as a slope shape or an approximate slope shape.
[0042] It should be noted that the NiO target used for sputtering is often placed directly above the narrow aperture, and its cross-sectional area is often larger than the area of the narrow aperture. Furthermore, the specific process and principle of this sputtering process are existing technologies and will not be elaborated here.
[0043] Since the prepared intermediate NiO film 8 can achieve a top-to-bottom sloping transition structure, it can effectively reduce the peak electric field between the edge of the anode 9 and the edge of the intermediate NiO film 8 under high voltage conditions, improve the breakdown voltage of the diode, and ensure its high voltage performance.
[0044] In addition, after the intermediate NiO film 8 is prepared, the remaining dielectric layer 4 and photoresist pattern no longer have any other functions. Their presence actually affects the realization of the diode function. Therefore, it is necessary to further remove the photoresist pattern and the remaining dielectric layer 4.
[0045] When removing the photoresist pattern, a photoresist remover can be used. When removing the residual dielectric layer 4, different etching solutions can be selected according to the material of the dielectric layer 4 to remove the residual dielectric layer 4.
[0046] Specifically, when preparing the anode 9, a photolithography process can be used to prepare the anode 9 pattern on the uppermost intermediate NiO thin film 8, and then evaporate the metal layer, which can be a Ni / Au metal layer with a Ni metal thickness of 20-100nm and an Au thickness of 50-400nm. Then, the anode 9 is stripped in a metal stripping solution to remove the adhesive.
[0047] For example, when preparing the cathode 10, a metal layer can be directly evaporated on the lower surface of the Ga2O3 substrate to form the cathode 10. Specifically, it can be a Ti / Au metal layer with a Ti metal thickness of 20-100 nm and an Au thickness of 50-400 nm.
[0048] It should be noted that when there is only one intermediate NiO film 8, the uppermost NiO film layer in step S200 is the base NiO film 3, and the uppermost intermediate NiO film 8 in step S600 is the only intermediate NiO film 8.
[0049] Compared with the prior art, the vertical power device fabrication method provided in this application utilizes the characteristics of different dielectric layers 4 having different corrosion rates under the action of the first etching solution to form a cavity structure 7 between the multiple dielectric layers 4. In order to form an intermediate NiO film 8 with a sloping structure in the cavity structure 7, and to form an anode 9 on the intermediate NiO film 8, a sloping structure is formed between the upper surface of the intermediate NiO film 8 and the upper surface of the base NiO film 3, i.e., a gentle slope for transition. The gentle slope replaces the traditional step structure, avoiding abrupt changes in geometry and effectively reducing the electric field accumulation effect.
[0050] In addition, the NiO thin film 3 covering the upper surface of the Ga2O3 substrate can generate an electric field modulation effect, which disperses the high electric field originally concentrated at the junction edge to a wider area, and the process is simple and easy to implement.
[0051] As can be seen, the vertical power device fabrication method provided in this application can achieve high electric field dispersion by modulating the electric field through the base layer NiO thin film 3. The intermediate layer NiO thin film 8 can achieve a slope transition of the bonding shape, reduce the electric field accumulation effect caused by abrupt changes, effectively reduce the peak electric field at the edge of the anode 9 and the edge of NiO, avoid premature diode breakdown, and significantly improve the diode breakdown voltage.
[0052] Specifically, the number of layers in the multilayer dielectric layer 4 can be selectively set according to actual needs. Optionally, the number of layers in the multilayer dielectric layer 4 can be 2-5.
[0053] For example, the number of multilayer dielectric layers 4 is two. The dielectric layer 4 near the base NiO film 3 is defined as the first dielectric layer 4, and the dielectric layer 4 disposed on the first dielectric layer 4 is defined as the second dielectric layer 4. The corrosion rates of the first etchant on the first dielectric layer 4 and the second dielectric layer 4 are different, and the corrosion rate of the first etchant on the first dielectric layer 4 is greater than that of the second dielectric layer 4. Therefore, the first corrosion zone formed by the first etchant corroding the first dielectric layer 4 is larger than the second corrosion zone formed by the second dielectric layer 4. The cavity structure 7 formed is a structure that is wider at the bottom and narrower at the top. When preparing the intermediate NiO film 8, the cross-sectional area of the portion located in the first corrosion zone is larger than the cross-sectional area of the portion in the second corrosion zone. The intermediate NiO film 8 forms a sloping transition structure at its edge. Therefore, when the anode 9 is prepared on the intermediate NiO film 8, the edge of the anode 9 and the edge of the intermediate NiO film 8 have a sloping transition structure, thus reducing the problem of electric field accumulation.
[0054] It should be noted that during the corrosion process, the corrosion path of the first corrosive liquid is divided into longitudinal and transverse directions. In the longitudinal direction, the second medium layer 4 is corroded first, and then the first medium layer 4 is corroded. When the corrosion reaches the second medium layer 4, it is accompanied by transverse expansion corrosion within the second medium layer 4. Similarly, when the corrosion reaches the first medium layer 4, it is accompanied by transverse expansion corrosion within the first medium layer 4.
[0055] Although in the vertical direction, the first corrosive liquid needs to corrode the second medium layer 4 first and then the first medium layer 4, so in the initial stage, the second corrosion zone in the second medium layer 4 is larger than the first corrosion zone in the first medium layer 4; and when the first corrosive liquid corrodes downward and penetrates the upper second medium layer 4 before corroding the lower first medium layer 4, however, because the corrosion rate of the first corrosive liquid on the first medium layer 4 is extremely fast, in the later stage of the corrosion process, the first corrosive liquid can quickly expand the first corrosion zone of the first medium layer 4 and surpass the area of the second corrosion zone, thus forming a cavity structure 7 that is narrow at the top and wide at the bottom.
[0056] Please see Figure 1 In some possible embodiments, the base NiO film 3 is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the base NiO film 3 is 10nm-100nm.
[0057] By using sputtering or thermal oxidation processes to prepare a base NiO film of suitable thickness, the modulation effect of the base NiO film can be guaranteed, and the high electric field can be dispersed.
[0058] Alternatively, the NiO thin film 3 can be prepared using other processes, or two or more processes can be selected simultaneously. The specific preparation method can be selectively set according to actual needs. For example, pulsed laser deposition or atomic layer deposition can be used to prepare the NiO thin film 3.
[0059] Specifically, if the NiO film 3 is too thin (<10nm), it may lead to film discontinuity, defect conductivity, and unstable diode performance. If the NiO film 3 is too thick (>100nm), it may introduce excessive resistance, increase stress, and is not beneficial to the vertical dimensions of the diode.
[0060] Please see Figure 1 In some possible embodiments, the multilayer dielectric layer 4 includes a silicon dioxide layer 41 and a silicon nitride layer 42 sequentially disposed on the base NiO film 3; the first etching solution is a BOE solution; under the etching action of the BOE solution, the silicon nitride layer 42 and the silicon dioxide layer 41 are connected vertically to form a cavity structure 7.
[0061] By rationally designing the multilayer dielectric layer 4 as a silicon dioxide layer 41 and a silicon nitride layer 42, different corrosion rates can be obtained in the BOE solution. Since the corrosion rate of silicon dioxide layer 41 in BOE is greater than that of silicon nitride layer 42 in BOE solution, a cavity structure 7 that is narrow at the top and wide at the bottom can be formed.
[0062] It should be noted that the BOE solution is essentially a buffer solution of HF (HF+NH4F), and its specific composition and corrosion principle are existing technologies, which will not be elaborated here. The silicon nitride layer 42 is actually a SiNx layer. The corrosion rate of the BOE solution on silicon dioxide and silicon nitride is different. Furthermore, the corrosion rate of the BOE solution on silicon dioxide is extremely fast, while the corrosion rate on silicon nitride is relatively slow.
[0063] Preferably, the concentration of the BOE solution is between 20% and 50%, and the relative corrosion rate of the BOE solution on the silicon dioxide layer 41 and the silicon nitride layer 42 can be controlled by controlling the concentration ratio of the BOE solution, thereby forming corrosion areas of different sizes in the silicon dioxide layer 41 and the silicon nitride layer 42, so as to change the edge shape of the cavity structure 7, and thus adjust the slope structure of the intermediate NiO film 8 to achieve edge slope structure with different tilt angles.
[0064] It should be noted that the higher the concentration of the BOE solution, the greater the corrosion rate of the silica layer 41. Therefore, in the formed cavity structure 7 that is narrow at the top and wide at the bottom, the lower half of the cavity structure 7 is corroded faster, the lower half of the cavity structure 7 is larger, and the angle between the slope and the horizontal plane in the formed sloping structure is smaller, and the slope tends to be gentler.
[0065] Please see Figure 1 In some embodiments, the thickness of the silicon dioxide layer 41 is 50-2000 nm, and the thickness of the silicon nitride layer 42 is 50-2000 nm.
[0066] By adjusting the thickness of the silicon dioxide layer 41 and the silicon nitride layer 42, the tilt angle between the upper and lower parts of the cavity structure 7 is adjusted, thereby forming intermediate NiO thin films 8 with different tilt angles.
[0067] The sum of the thickness of the silicon dioxide layer 41 and the silicon nitride layer 42 affects the upper limit of the thickness of the intermediate NiO film 8. Therefore, its thickness should not be too large. Furthermore, in order to ensure the controllability of its corrosion rate, the sum of the thickness of the silicon dioxide layer 41 and the silicon nitride layer 42 should not be too thick.
[0068] It is important to understand that during the corrosion process, although the first etchant corrodes downwards through the upper silicon nitride layer before corroding the lower silicon dioxide layer, the BOE solution corrodes the silicon dioxide layer 41 at an extremely fast rate. Therefore, it can rapidly expand the corrosion area of the silicon dioxide layer 41 and surpass the corrosion area of the silicon nitride layer, thereby forming a cavity structure 7 that is narrow at the top and wide at the bottom.
[0069] Please see Figure 1 For example, removing the photoresist pattern and residual multilayer dielectric layer 4 specifically includes the following steps: stripping the photoresist pattern using a photoresist stripper; and removing the residual silicon dioxide layer 41 and silicon nitride layer 42 using a mixture of hot phosphoric acid and hydrofluoric acid.
[0070] The photoresist pattern is removed by stripping solution, residual silicon nitride is removed by hot phosphoric acid, and residual silicon dioxide is removed by hydrofluoric acid, so as to avoid the influence of residual photoresist or dielectric layer 4 on the diode.
[0071] Specifically, the photoresist remover can be used to remove photoresist; the hot phosphoric acid solution can be used to remove silicon nitride and increase the etching rate of silicon nitride layer 42; and the hydrofluoric acid solution can be used to remove silicon dioxide and increase the etching rate of silicon dioxide layer 41. Therefore, the mixture of hot phosphoric acid and hydrofluoric acid can quickly remove the double dielectric layer 4 composed of silicon nitride layer 42 and silicon dioxide layer 41, improve the removal rate, and speed up the process.
[0072] In some possible embodiments, the multilayer dielectric layer 4 includes an indium tin oxide layer and an aluminum oxide layer sequentially disposed on the base NiO film 3; the first etching solution is a hydrochloric acid solution; under the etching action of the hydrochloric acid solution, the indium tin oxide layer and the aluminum oxide layer are interconnected to form a cavity structure 7.
[0073] By rationally designing the multilayer dielectric layer 4 as an indium tin oxide layer and an aluminum oxide layer, different corrosion rates can be obtained in hydrochloric acid solution. Since the corrosion rate of the indium tin oxide layer in hydrochloric acid solution is greater than that of the aluminum oxide layer in hydrochloric acid solution, a cavity structure 7 that is narrow at the top and wide at the bottom can be formed.
[0074] It is important to understand that hydrochloric acid solution has different corrosion rates on indium tin oxide (ITO) and aluminum oxide (Al2O3) layers. In diodes containing ITO and Al2O3 stacked structures, the corrosion areas of the indium tin oxide and aluminum oxide layers can be controlled by precisely controlling the concentration, temperature and etching time of hydrochloric acid, and cavity structures with different slope structures can be formed accordingly.
[0075] For example, by increasing the concentration of the hydrochloric acid solution, the corrosion area of the lower indium tin oxide layer by the hydrochloric acid solution can be further expanded, thereby making the corrosion area of the lower layer larger than that of the upper layer, and thus making the slope structure of the intermediate NiO film 8 with a smaller angle between the slope and the horizontal plane, and the slope becomes more gentle.
[0076] For example, removing the photoresist pattern and residual multilayer dielectric layer 4 includes the following steps: stripping the photoresist pattern using a stripper; and removing the residual indium tin oxide layer and aluminum oxide layer using hydrochloric acid.
[0077] The aluminum oxide layer can be etched by strong acid or strong alkali solutions. Considering the acidic environment required for the indium tin oxide layer, hydrochloric acid solution is selected for etching the aluminum oxide layer and the indium tin oxide layer in this application.
[0078] In some possible embodiments, the multilayer dielectric layer 4 includes a zirconium oxide layer and a silicon dioxide layer 41 sequentially disposed on the base NiO film 3; the first etching solution is a hot phosphoric acid solution; under the etching action of the hot phosphoric acid solution, the zirconium oxide layer and the silicon dioxide layer 41 are interconnected to form a cavity structure 7.
[0079] Similarly, the zirconium oxide layer and the silicon dioxide layer 41 have different corrosion rates in the hot phosphoric acid solution. Since the corrosion rate of the zirconium oxide layer in the hot phosphoric acid solution is greater than that of the silicon dioxide layer 41, a cavity structure 7 that is narrow at the top and wide at the bottom can be formed between the zirconium oxide layer and the silicon dioxide layer 41.
[0080] Specifically, a zirconium oxide layer (ZrO2) is disposed on the base NiO film 3, and a silicon dioxide layer 41 is disposed on the zirconium oxide layer.
[0081] The corrosion rates of the zirconium oxide layer and the silicon dioxide layer 41 by the hot phosphoric acid solution are quite different. Furthermore, the corrosion rates of the zirconium oxide layer and the silicon dioxide layer 41 can be adjusted by changing the concentration ratio of the hot phosphoric acid solution and the corrosion temperature. Due to the extremely high Si-O bond energy of SiO2, the corrosion rate of the silicon dioxide layer 41 by the hot phosphoric acid solution is relatively low. However, as an amphoteric oxide, ZrO2 undergoes a slow chemical reaction under high temperature and strong acid, resulting in a higher corrosion rate of the zirconium oxide layer by the hot phosphoric acid solution.
[0082] Generally speaking, the higher the concentration of the hot phosphoric acid solution, the greater the corrosion rate of the zirconia layer, the larger the corrosion zone formed by the zirconia layer, resulting in a larger lower half of the cavity. In the slope structure of the intermediate NiO film 8, the angle between the slope and the horizontal plane is smaller, and the slope is gentler, which can effectively avoid the problem of abrupt shape changes.
[0083] For example, removing the photoresist pattern and residual multilayer dielectric layer 4 includes the following steps: stripping the photoresist pattern using a stripper; and removing the residual zirconium oxide layer and silicon dioxide layer 41 using a mixture of hot phosphoric acid and hydrofluoric acid.
[0084] Please see Figure 1 In some possible embodiments, steps S200-S500 are repeated sequentially on the intermediate NiO film 8 obtained in step S500 to obtain multiple intermediate NiO films 8; and in each pair of adjacent intermediate NiO films 8, the upper surface area of the lower intermediate NiO film 8 is not less than the lower surface area of the upper intermediate NiO film 8.
[0085] By setting multiple intermediate NiO thin films 8, a transition structure with multiple sloping structures can be formed. By ensuring that the upper surface area of the lower intermediate NiO thin film 8 is not less than the lower surface area of the upper intermediate NiO thin film 8, a large sloping structure composed of multiple sloping structures can be formed between the multiple intermediate NiO thin films 8. This is beneficial for the gradual dispersion of high electric field and optimizes the performance of the diode.
[0086] For example, the number of intermediate NiO thin films 8 can be selectively set according to actual needs. Preferably, the number of intermediate NiO thin films 8 is 1-5 layers to avoid excessive thickness of intermediate NiO thin films 8, which would lead to a significant increase in process manufacturing costs and be detrimental to the overall performance optimization of the diode.
[0087] Optionally, in the slope structure between two adjacent intermediate NiO films 8, the angle between the slope of each layer and the corresponding horizontal plane is equal, that is, the slope angles are equal; alternatively, in the slope structure between two adjacent intermediate NiO films 8, the angle between the slope of each layer and the corresponding horizontal plane is unequal, that is, the slope angles are unequal; specifically, it can be selectively set according to actual needs.
[0088] Specifically, after preparing one intermediate NiO film 8, another intermediate NiO film 8 can be prepared.
[0089] For example, the prepared intermediate NiO film 8 forms the uppermost NiO film. Therefore, it is necessary to prepare a multilayer dielectric layer 4 on the upper surface of the intermediate NiO film 8. Under the action of the first etching solution, the etching rate of the multilayer dielectric layer 4 gradually decreases in the direction away from the Ga2O3 substrate. Then, a photoresist pattern is prepared on the upper surface of the uppermost dielectric layer 4. The first etching solution is injected into the photoresist pattern to etch the multilayer dielectric layer 4 and form a cavity structure 7 that is wider at the bottom and narrower at the top between the multilayer dielectric layers 4. A second intermediate NiO film 8 is prepared in the cavity structure 7 so that the edge of the second intermediate NiO film 8 near the inner wall of the cavity structure 7 is a slope structure. The photoresist pattern and the residual multilayer dielectric layer 4 are removed to obtain two intermediate NiO films 8. The second intermediate NiO film 8 forms the uppermost intermediate NiO film 8. At this time, an anode 9 is prepared on the intermediate NiO film 8, so that two intermediate NiO films 8 are formed between the anode 9 and the base NiO film 3.
[0090] Similarly, the above preparation process can be repeated to prepare three-layer or multi-layer intermediate NiO thin films.
[0091] Please see Figure 1 In some possible embodiments, the preparation of a photoresist pattern on the upper surface of the uppermost dielectric layer 4 specifically includes the following steps: spin-coating a photoresist layer 5 on the upper surface of the uppermost dielectric layer 4 and baking it, performing patterned exposure through a photolithography machine, and then performing development, fixing and drying to obtain a photoresist pattern; wherein, the photoresist pattern extends downward to the upper surface of the uppermost dielectric layer 4.
[0092] The shape of the photoresist pattern determines the cross-sectional shape of the cavity structure 7 that is etched downwards by the first etching solution. The photoresist pattern is obtained through patterning exposure, development, fixing and drying processes, which facilitates the etching of multiple dielectric layers 4 downwards from the photoresist pattern.
[0093] Specifically, the spin coating speed of the photoresist is 2000-5000 rpm; the baking process includes baking the photoresist layer on a hot plate at 80-200 degrees Celsius for 2-5 minutes. The lithography patterning exposure time is 5-20 seconds; the developing solution is 1%-5% TMAH solution, and the developing time is 10-40 seconds; the fixing solution is deionized water, and the fixing time is 20-50 seconds; the drying process includes introducing nitrogen gas into the photoresist pattern to dry the residual liquid in the photoresist pattern.
[0094] By further optimizing the parameters in the photoresist pattern preparation process, it is beneficial to control the shape of the photoresist pattern and ensure its accuracy.
[0095] In some possible embodiments, the intermediate NiO film 8 is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the intermediate NiO film 8 is 10 nm-200 nm.
[0096] By rationally setting the preparation process and thickness of the intermediate NiO thin film 8, it is beneficial to form a slope structure of appropriate height at the edge of the intermediate NiO thin film 8, thereby reducing the peak electric field at the edge of the anode 9 and the edge of NiO and improving the diode performance.
[0097] Alternatively, the intermediate NiO thin film 8 can also be prepared using other processes, or two or more processes can be selected simultaneously. The specific preparation method can be selectively set according to actual needs. For example, pulsed laser deposition or atomic layer deposition can be used to prepare the intermediate NiO thin film 8.
[0098] Based on the same inventive concept, this application also provides a vertical power device, which is prepared using the above-described vertical power device preparation method. The vertical power device includes a Ga2O3 substrate, a base NiO thin film 3, an intermediate NiO thin film 8, and an anode 9. A cathode 10 is disposed at the bottom of the Ga2O3 substrate. The base NiO thin film 3 is disposed on the upper surface of the Ga2O3 substrate. The intermediate NiO thin film 8 is disposed on the upper surface of the base NiO thin film 3, and the circumferential edge of the intermediate NiO thin film 8 has a sloping structure that is wider at the bottom and narrower at the top. The anode 9 is disposed on the upper surface of the intermediate NiO thin film 8.
[0099] The vertical power device provided in this application, because it is fabricated using the above-described vertical power device fabrication method, has all the beneficial effects of the above-described vertical power device fabrication method. It can effectively reduce the peak electric field at the edge of anode 9 and the edge of NiO, avoid premature breakdown of the diode, significantly improve the breakdown voltage of the vertical power device, and optimize the high voltage performance of the vertical power device.
[0100] Furthermore, in the fabricated vertical power device, multiple layers of intermediate NiO thin film 8 are arranged vertically and horizontally, and in each pair of adjacent intermediate NiO thin film 8, the upper surface area of the lower intermediate NiO thin film 8 is not less than the lower surface area of the upper intermediate NiO thin film 8.
[0101] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for fabricating a vertical power device, characterized in that, include: S100. A base NiO thin film is prepared on the upper surface of a Ga2O3 substrate (3); S200. Prepare multiple dielectric layers (4) that can be corroded by the first etchant on the uppermost NiO thin film layer, and gradually reduce the corrosion rate of the multiple dielectric layers (4) away from the Ga2O3 substrate. S300. A photoresist pattern is prepared on the upper surface of the uppermost dielectric layer (4); S400. The first etching solution is injected into the photoresist pattern to etch multiple layers of the dielectric layer (4) and to form a cavity structure (7) that is wider at the bottom and narrower at the top between the multiple layers of the dielectric layer (4); S500. An intermediate NiO film (8) is prepared in the cavity structure (7) by magnetron sputtering, so that the edge of the intermediate NiO film (8) near the inner wall of the cavity structure (7) is a slope structure; the photoresist pattern and residual multilayer dielectric layers (4) are removed. S600. An anode (9) is prepared on the upper surface of the uppermost intermediate NiO thin film (8).
2. The method for fabricating a vertical power device as described in claim 1, characterized in that, The base NiO film (3) is prepared by one or more of sputtering or thermal oxidation processes, and the thickness of the base NiO film (3) is 10nm-100nm.
3. The method for fabricating a vertical power device as described in claim 1, characterized in that, The multilayer dielectric layer (4) includes a silicon dioxide layer (41) and a silicon nitride layer (42) sequentially disposed on the base NiO film (3); The first corrosive solution is a BOE solution; Under the corrosive action of the BOE solution, the silicon nitride layer (42) and the silicon dioxide layer (41) are connected vertically to form the cavity structure (7).
4. The method for fabricating a vertical power device as described in claim 3, characterized in that, The thickness of the silicon dioxide layer (41) is 50-2000 nm, and the thickness of the silicon nitride layer (42) is 50-2000 nm.
5. The method for fabricating a vertical power device as described in claim 4, characterized in that, The process of removing the photoresist pattern and residual multilayer dielectric layers (4) includes: The photoresist pattern is stripped using a resist stripper. The residual silicon dioxide layer (41) and silicon nitride layer (42) are removed by using a mixture of hot phosphoric acid and hydrofluoric acid.
6. The method for fabricating a vertical power device as described in claim 1, characterized in that, The multilayer dielectric layer (4) includes an indium tin oxide layer and an aluminum oxide layer sequentially disposed on the base NiO film (3); The first corrosive solution is a hydrochloric acid solution; Under the corrosive action of the hydrochloric acid solution, the indium tin oxide layer and the aluminum oxide layer are connected vertically to form the cavity structure (7).
7. The method for fabricating a vertical power device as described in claim 1, characterized in that, The multilayer dielectric layer (4) includes a zirconium oxide layer and a silicon dioxide layer (41) sequentially disposed on the base NiO film (3); The first corrosive solution is a hot phosphoric acid solution; Under the corrosive action of the hot phosphoric acid solution, the zirconium oxide layer and the silicon dioxide layer (41) are connected vertically to form the cavity structure (7).
8. The method for fabricating a vertical power device as described in claim 1, characterized in that, Steps S200-S500 are repeated sequentially on the intermediate NiO film (8) obtained in step S500 to obtain multiple layers of the intermediate NiO film (8); Furthermore, in each pair of adjacent intermediate NiO films (8), the upper surface area of the lower intermediate NiO film (8) is not less than the lower surface area of the upper intermediate NiO film (8).
9. The method for fabricating a vertical power device as described in claim 1, characterized in that, The process of preparing a photoresist pattern on the upper surface of the uppermost dielectric layer (4) includes: A photoresist layer (5) is spin-coated onto the upper surface of the uppermost dielectric layer (4) and baked. The photoresist pattern is then obtained by patterning exposure using a photolithography machine and followed by development, fixing, and drying. The photoresist pattern extends downwards to the upper surface of the uppermost dielectric layer (4).
10. A vertical power device, characterized in that, The vertical power device is fabricated using the method described in any one of claims 1-9, wherein the vertical power device comprises: A Ga2O3 substrate with a cathode (10) at the bottom; A NiO thin film (3) is disposed on the upper surface of the Ga2O3 substrate; An intermediate NiO film (8) is disposed on the upper surface of the base NiO film (3), and the circumferential edge of the intermediate NiO film (8) is a sloping structure that is wider at the bottom and narrower at the top. The anode (9) is disposed on the upper surface of the intermediate NiO thin film (8).