Three-level neutral-point clamping bridge arm switch unit integrated structure

Abstract

The invention provides a three-level neutral-point-clamped bridge arm switch unit integrated structure, and relates to the technical field of multi-level bridge arm circuits. The circuit comprises a bottom copper-clad ceramic substrate, a top copper-clad ceramic substrate and a printed circuit board, the bottom copper-clad ceramic substrate bears half of the three-level bridge arm circuit, and the top copper-clad ceramic substrate bears the other half of the three-level bridge arm circuit; the printed circuit board bears a direct current bus capacitor and is electrically connected with the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate. Compared with a discrete component or a single-sided power module, the integrated structure provided by the invention has the advantages that the lead area is shortened, the occupied total area is smaller, and the magnetic field / inductance parameter induced by the circuit is lower, so that the parasitic inductance of the commutation loop is reduced by virtue of the extremely small integrated area and the commutation loop structure, and the safety of the three-level converter is further improved.

Description

Technical Field

[0001] This application belongs to the field of multilevel bridge arm circuit technology, specifically relating to an integrated structure of a three-level midpoint clamping bridge arm switch unit. Background Technology

[0002] In fields such as photovoltaic power generation, circuit topologies such as three-level NPC (Neutral Point Clasped) bridge arms are widely used. These multilevel bridge arm circuits are typically used in voltage source converters (VSCs), and their working principle involves switching controllable power semiconductor devices, thereby controlling the output voltage.

[0003] During a single switching process, branches with changing current connect end-to-end to form a loop with a capacitor or voltage source, known as the Current Commutation Loop (CCL). The CCL generates high parasitic inductance, which severely impacts the temperature and safety of circuits such as the three-level NPC bridge arms. Therefore, further optimization is needed to improve the safety of the three-level converter. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide an integrated structure for a three-level midpoint clamping bridge arm switch unit, which addresses the above-mentioned deficiencies in the existing technology. Using this integrated structure, the parasitic inductance of the converter circuit is reduced, and the safety of the three-level converter is improved.

[0005] This application provides an integrated structure for a three-level midpoint clamping bridge arm switch unit, including: Bottom copper-clad ceramic substrate, top copper-clad ceramic substrate, and printed circuit board; The bottom copper-clad ceramic substrate carries half of the three-level bridge arm circuit, and the top copper-clad ceramic substrate carries the other half of the three-level bridge arm circuit. The printed circuit board carries a DC bus capacitor and is electrically interconnected with the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate, respectively.

[0006] In some implementations, one half of the three-level bridge arm circuit includes: a switch S1, a switch S3, and a power diode D6; wherein the transistors in the switch S1 and the switch S3 are both metal-oxide-semiconductor field-effect transistors. The drain of the switching transistor S1 is connected to the node corresponding to the DC positive potential on the copper layer of the bottom copper-clad ceramic substrate. The power source of the switch S1 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively; wherein, the X potential is the common node potential of the power source of the switch S1, the cathode of the power diode D5 and the drain of the switch S2; the power diode D5 and the switch S2 belong to the other half of the three-level bridge arm circuit. The drain of the switching transistor S3 is connected to the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate. The power source of switch S3 is connected to the corresponding node of Y potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively; wherein, Y potential is the common node potential of the power source of switch S3, the anode of power diode D6 and the drain of switch S4; switch S4 belongs to the other half of the three-level bridge arm circuit. The cathode of power diode D6 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate. The anode of power diode D6 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively. The driving gate and driving source of switch S1, and the driving gate and driving source of switch S3, are all connected to the corresponding copper layer of the printed circuit board substrate by leading out pins.

[0007] In some implementations, half of the three-level bridge arm circuit also includes: four metal interposer blocks, namely metal interposer block MP1, metal interposer block MP3, metal interposer block MP6 and metal interposer block MP7. The metal interposer block MP1 is connected to the power source of the switching transistor S1, the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively. The metal interposer block MP3 is connected to the power source of the switching transistor S3, the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively. The metal interposer block MP6 is connected to the anode of the power diode D6, the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively. The metal interposer block MP7 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate.

[0008] In some implementations, the other half of the three-level bridge arm circuit includes: switch S2, switch S4 and power diode D5; wherein the transistors in switch S2 and switch S4 are metal-oxide-semiconductor field-effect transistors. The drain of the switching transistor S2 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate. The power source of the switching transistor S2 is connected to the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The drain of the switching transistor S4 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate. The power source of the switching transistor S4 is connected to the node corresponding to the DC negative potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The cathode of power diode D5 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate. The anode of power diode D5 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The driving gate and driving source of switch S2, and the driving gate and driving source of switch S4, are all connected to the corresponding copper layer of the printed circuit board substrate by leading out pins.

[0009] In some implementations, the other half of the three-level bridge arm circuit also includes: three metal interposer blocks, namely metal interposer block MP2, metal interposer block MP4 and metal interposer block MP5; The metal interposer block MP2 is connected to the power source of the switching transistor S2, the corresponding node of the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The metal interposer block MP4 is connected to the power source of the switching transistor S4, the node corresponding to the DC negative potential on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The metal interposer block MP5 is connected to the anode of the power diode D5, the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate.

[0010] In some implementations, all copper layers corresponding to the DC positive potential, DC negative potential, neutral point N potential, and output potential OUT in the bottom copper-clad ceramic substrate are connected to the corresponding copper layers in the printed circuit board. The copper layer corresponding to the neutral point N potential in the top copper-clad ceramic substrate is connected to the corresponding copper layer in the printed circuit board.

[0011] In some embodiments, the copper layers corresponding to the DC potential, the neutral point N potential, and the output potential OUT in the bottom copper-clad ceramic substrate are distributed in the vertical direction, in the order of the copper layer corresponding to the DC potential, the copper layer corresponding to the neutral point N potential, and the copper layer corresponding to the output potential OUT; wherein, the DC potential includes the DC positive potential and the DC negative potential. The copper layers corresponding to the DC positive and DC negative potentials are distributed horizontally, in the order of the copper layer corresponding to the DC positive potential and the copper layer corresponding to the DC negative potential.

[0012] In some implementations, the pin of the drive gate of the switch S1 is adjacent to the copper layer corresponding to the DC positive potential. The pin of the drive gate of the switching transistor S3 is adjacent to the copper layer corresponding to the output potential OUT.

[0013] In some embodiments, the copper layers corresponding to the Y potential, X potential, and neutral point N potential in the top copper-clad ceramic substrate are distributed horizontally, in the order of copper layer corresponding to Y potential, copper layer corresponding to X potential, and copper layer corresponding to neutral point N potential.

[0014] In some implementations, the pin of the drive gate of the switch S2 is adjacent to the copper layer corresponding to the X potential; The pin of the drive gate of the switching transistor S4 is adjacent to the copper layer corresponding to the Y potential.

[0015] According to the integrated structure of the three-level midpoint clamping bridge arm switch unit provided in this application embodiment, half of the three-level bridge arm circuit is carried by a bottom copper-clad ceramic substrate, the other half of the three-level bridge arm circuit is carried by a top copper-clad ceramic substrate, and the DC bus capacitor is carried by a printed circuit board. Compared with discrete components or single-sided power modules, this integrated structure reduces the lead area, occupies a smaller total area, and has lower magnetic field / inductance parameters induced by the lines. Thus, by relying on the extremely small integrated area and commutation circuit structure, the parasitic inductance of the commutation circuit is reduced, thereby improving the safety of the three-level converter. Attached Figure Description

[0016] Figure 1 This application shows a schematic diagram of a three-level circuit provided in an embodiment. Figure 2 This diagram shows the bottom copper-clad ceramic substrate structure of the integrated structure of the three-level midpoint clamping bridge arm switch unit provided in this application embodiment; Figure 3 This diagram shows a top copper-clad ceramic substrate structure of the integrated structure of the three-level midpoint clamping bridge arm switch unit provided in an embodiment of this application. Figure 4a This illustration shows a front view of a switching transistor provided in an embodiment of this application; Figure 4b This illustration shows a schematic diagram of the back side of a switching transistor according to an embodiment of this application; Figure 5 A side view of the switching unit structure provided in an embodiment of this application is shown. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions of this application, the application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0018] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0019] It should be noted that, in this document, relational terms such as first and second, A, B, and C, etc., are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0020] Currently, power electronic converters are widely used in new energy vehicles, renewable energy systems, and other fields. Power semiconductors, especially switching devices such as insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), are the core of power electronic converters and require packaging for application. The electrical parameters and thermal characteristics of the packaging play a crucial role in the performance of power semiconductor devices.

[0021] Three-level NPC bridge arm circuit topologies are commonly used in voltage source converters. These converters operate by switching controllable power semiconductor devices, thereby controlling the output voltage. During the switching process, the current flowing through a single bridge arm can be considered essentially constant due to the limitation of the external inductor, while the current flows to branches with different voltages depending on the switching state of the device. In a single switching process, the branches with changing currents connect end-to-end to form a loop with a capacitor or voltage source, i.e., a commutation circuit.

[0022] During this process, the changing direction of current in different branches will generate instantaneous rates of change of current. The rate of change of current in the conductor's physical structure will generate an additional induced voltage, which will act on the power semiconductor device in conjunction with the voltage source. At this point, power semiconductor devices with insufficient withstand voltage may be damaged by overvoltage, or even cause safety issues such as combustion. Currently, there are two common approaches to address this risk.

[0023] One approach is to use power semiconductor devices with higher rated voltage. However, the current-carrying capacity per unit area of ​​power semiconductor devices decreases as the voltage rating increases, and the price also increases with the voltage rating. Therefore, in most cases, using higher-grade and larger-area power devices to improve the induced overvoltage withstand performance of power devices in voltage source converters to switching transients is less economical.

[0024] Secondly, reducing the voltage of the voltage source itself allows power semiconductor devices to operate safely. However, since voltage source converters are often part of a power conversion system, their input and output voltages should be coordinated with the parameters of other equipment and should not be arbitrarily changed. This approach is not suitable for system applications.

[0025] To maintain stable operation and power conversion under rated voltage source support while keeping the power semiconductor chip level and area unchanged, current attempts are being made to reduce induced voltage by adjusting gate drive parameters and designing novel drive structures. This design can effectively control the rate of current change, thereby reducing induced voltage, but it requires sacrificing some switching speed or building a more complex system. Furthermore, it also leads to increased switching losses and a decrease in the overall performance of the power converter.

[0026] In terms of structural optimization and design, current methods mainly focus on optimizing individual components. For example, they involve designing power modules, buses, or connection terminals in the converter separately, reducing the parasitic inductance parameters within each component to ultimately reduce the overall parasitic inductance of the converter circuit, thereby reducing the induced voltage caused by the rate of change of current in this circuit. However, due to the complexity of the three-level bridge arm topology, optimizing these components individually has limited effect on mitigating switching transient overvoltages.

[0027] The main reason is that the physical structure of the commutation circuit in a three-level bridge arm not only includes the conventional half-bridge structure but also the connection between one half-bridge structure and the other. In practical applications, the planar layout of the traditional half-bridge structures and the operable connection terminals offer very limited room for reducing the parasitic inductance of the commutation circuit. In the smallest-scale three-level bridge arm power module applications, this inductance is above 10 nH (nanohenries), while in larger-scale busbars, it is tens of nH or even larger.

[0028] In addition, for power devices with such complex topologies, the power semiconductor chips in different locations within them generate different amounts of heat during actual operation. Macroscopically, this manifests as different temperatures in different areas of the three-level bridge arm substrate using a single power module integration method; that is, different temperatures exist between the modules of a three-level bridge arm integrated with three or two half-bridges, a diode rectifier bridge, and a busbar.

[0029] When the operating temperature of power devices exceeds a certain threshold temperature, they must cease operation to avoid safety risks. Therefore, this uneven temperature distribution causes chips with higher losses to reach the threshold temperature first, limiting the converter's performance.

[0030] Therefore, in the current integrated structure of the three-level midpoint clamp bridge arm switching unit, the commutation circuit generates a high parasitic inductance, which seriously affects the temperature and safety of circuits such as the three-level NPC bridge arm. Further optimization is needed to improve the safety of the three-level converter.

[0031] Example 1

[0032] The integrated structure of the three-level midpoint clamping bridge arm switch unit provided in this application embodiment may include the following structure: Bottom copper-clad ceramic substrate, top copper-clad ceramic substrate, and printed circuit board.

[0033] The bottom copper-clad ceramic substrate carries half of the three-level bridge arm circuit, while the top copper-clad ceramic substrate carries the other half.

[0034] The printed circuit board carries a DC bus capacitor and is electrically interconnected with the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate, respectively.

[0035] For example, both the bottom and top copper-clad ceramic substrates are Direct Bonded Copper (DBC) boards. A DBC board has a copper-ceramic-copper structure. By photolithography and etching on the top copper foil, precise circuit patterns can be fabricated for mounting chips (such as IGBTs and MOSFETs) and achieving electrical interconnections.

[0036] For example, the bottom copper-clad ceramic substrate refers to the copper-clad ceramic substrate at the bottom, and the top copper-clad ceramic substrate refers to the copper-clad ceramic substrate at the top. In some embodiments, the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate may be replaced with other thermally conductive insulating materials, which is not limited in this embodiment.

[0037] For example, the bottom copper-clad ceramic substrate carries half of the three-level bridge arm circuit. For instance, it can carry either switches S1 and S2 and power diode D5, or switches S1 and S3 and power diode D6. The choice of which half of the three-level bridge arm circuit is used depends on the specific application, and this embodiment does not limit this choice. Similarly, the top copper-clad ceramic substrate carries the other half of the three-level bridge arm circuit, which can be either switches S3 and S4 and power diode D6, or switches S2 and S4 and power diode D5. The switches can include transistors and anti-parallel freewheeling diodes.

[0038] For example, the printed circuit board can be electrically interconnected with the DC potential, neutral point potential, output potential, etc. on the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate.

[0039] For example, the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate can be connected to the printed circuit board using methods such as reflow soldering and nano-silver sintering.

[0040] For example, the sandwich structure of the top copper-clad ceramic substrate, the printed circuit board, and the bottom copper-clad ceramic substrate is a symmetrical structure, which provides more uniform current and heat distribution compared to an asymmetrical (or unilateral) structure.

[0041] According to the integrated structure of the three-level midpoint clamping bridge arm switch unit provided in the embodiments of this application, half of the three-level bridge arm circuit is carried by a bottom copper-clad ceramic substrate, the other half of the three-level bridge arm circuit is carried by a top copper-clad ceramic substrate, and the DC bus capacitor is carried by a printed circuit board. Compared with discrete components or single-sided power modules, this integrated structure shortens the lead area, occupies a smaller total area, and has lower magnetic field / inductance parameters induced by the line. Thus, it reduces the parasitic inductance of the commutation circuit by relying on the extremely small integrated area and the commutation circuit structure.

[0042] Example 2

[0043] The integrated structure of the three-level midpoint clamping bridge arm switch unit provided in this application embodiment is further described based on the integrated structure of the three-level midpoint clamping bridge arm switch unit provided in embodiment 1 of this application.

[0044] like Figure 1As shown, in this embodiment, there are a total of four switching transistors (S1, S2, S3, S4) and two power diodes (D5, D6). The switching transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), insulated-gate bipolar transistors (IGBTs), or vertical gallium nitride high electron mobility transistors (GaN HEMTs), etc., which are represented by the MOSFET designation in the figure, and are also exemplarily described using MOSFETs in this embodiment.

[0045] In the integrated structure of the three-level midpoint clamping bridge arm switch unit in this embodiment: like Figure 2 and Figure 3 As shown, the bottom copper-clad ceramic substrate supports one half of the three-level bridge arm circuit, which includes: switch S1, switch S3, and power diode D6. The transistors in switch S1 and switch S3 are both metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0046] The drain of the switching transistor S1 is connected to the node corresponding to the DC positive potential DC+ on the copper layer of the bottom copper-clad ceramic substrate.

[0047] The power source of switch S1 is connected to the node corresponding to potential X on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate. Potential X is the common node potential connecting the power source of switch S1, the cathode of power diode D5, and the drain of switch S2. Power diode D5 and switch S2 constitute the other half of the three-level bridge arm circuit.

[0048] The drain of the switching transistor S3 is connected to the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate.

[0049] The power source of switch S3 is connected to the corresponding node at the Y potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer on the bottom copper-clad ceramic substrate. The Y potential is the common node potential connecting the power source of switch S3, the anode of power diode D6, and the drain of switch S4. Switch S4 belongs to the other half of the three-level bridge arm circuit.

[0050] The cathode of power diode D6 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate.

[0051] The anode of the power diode D6 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate.

[0052] The driving gate and driving source of switch S1, and the driving gate and driving source of switch S3, are all connected to the corresponding copper layer of the printed circuit board substrate by leading out pins.

[0053] For example, the connection between the switching transistor, the power diode, and the copper layer can be achieved by bonding wires, by using a metal interposer, or by other connection methods. This embodiment does not limit the specific connection method.

[0054] In some implementations, half of the three-level bridge arm circuit also includes four metal interposer blocks, namely metal interposer block MP1, metal interposer block MP3, metal interposer block MP6 and metal interposer block MP7.

[0055] The metal interposer block MP1 is connected to the power source of the switching transistor S1, the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate.

[0056] The metal interposer block MP3 is connected to the power source of the switching transistor S3, the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate.

[0057] The metal interposer block MP6 is connected to the anode of the power diode D6, the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate.

[0058] The metal interposer block MP7 is connected to the node corresponding to the neutral point N (Neutra) potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate.

[0059] For example, the metal interposer is a wide, thin, and short planar conductor whose parasitic inductance is inversely proportional to its area and is far lower than that of a cylindrical bonding wire bundle of the same cross-sectional area, thereby significantly reducing the parasitic inductance of the commutation circuit. Simultaneously, the metal interposer itself is an excellent thermal conductor with a large contact area, providing a double-sided heat dissipation path. Connecting the bottom and top copper-clad ceramic substrates via the metal interposer greatly improves the double-sided heat dissipation effect, thereby enhancing the chip's overall heat dissipation performance.

[0060] For example, the power source corresponds to the power circuit, and the drive source corresponds to the drive circuit. By physically isolating the power source and the drive source, it can be ensured that the drive signal is not affected by power switching noise.

[0061] In some implementations, the other half of the three-level bridge arm circuit includes: switching transistor S2, switching transistor S4, and power diode D5. The transistors in switching transistors S2 and S4 are both metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0062] The drain of the switching transistor S2 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate.

[0063] The power source of the switching transistor S2 is connected to the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate.

[0064] The drain of the switching transistor S4 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate.

[0065] The power source of the switching transistor S4 is connected to the node corresponding to the DC negative potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate.

[0066] The cathode of power diode D5 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate.

[0067] The anode of power diode D5 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate.

[0068] The driving gate and driving source of switch S2, and the driving gate and driving source of switch S4, are all connected to the corresponding copper layer of the printed circuit board substrate by leading out pins.

[0069] For example, similar to the copper-clad ceramic substrate described above, the connection between the switching transistor, the power diode, and the copper layer can be achieved by bonding wires, by using a metal interposer, or by other connection methods. This embodiment does not limit the specific connection method.

[0070] In some implementations, the other half of the three-level bridge arm circuit also includes three metal interposer blocks, namely metal interposer block MP2, metal interposer block MP4 and metal interposer block MP5.

[0071] The metal interposer block MP2 is connected to the power source of the switching transistor S2, the corresponding node of the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate.

[0072] The metal interposer block MP4 is connected to the power source of the switching transistor S4, the node corresponding to the DC negative potential on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate.

[0073] The metal interposer block MP5 is connected to the anode of the power diode D5, the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate.

[0074] By connecting the bottom and top copper-clad ceramic substrates with a metal intermediate layer, the parasitic inductance of the commutation circuit can be greatly reduced, and the heat dissipation of the chip can be improved.

[0075] In some implementations, such as Figure 2 and Figure 3 As shown, all copper layers corresponding to the DC positive potential DC+, DC negative potential DC-, neutral point N potential, and output potential OUT in the bottom copper-clad ceramic substrate are connected to the corresponding copper layers in the printed circuit board.

[0076] The copper layer corresponding to the neutral point N potential in the top copper-clad ceramic substrate is connected to the corresponding copper layer in the printed circuit board.

[0077] For example, the connection location area is as follows Figure 2 and Figure 3 The image shows the corresponding soldering area on the PCB (Printed Circuit Board). The PCB soldering area includes the DC positive potential (DC+), the DC negative potential (DC-), the neutral point (N) potential, and the output potential (OUT).

[0078] By connecting all the copper layers corresponding to the DC positive potential DC+, DC negative potential DC-, neutral point N potential, and output potential OUT in the bottom copper-clad ceramic substrate to the corresponding copper layers in the printed circuit board, and connecting the copper layer corresponding to the neutral point N potential in the top copper-clad ceramic substrate to the corresponding copper layers in the printed circuit board, and connecting the drive source and gate leads of each switching transistor to the corresponding copper layers in the printed circuit board, electrical interconnection between the printed circuit board, the bottom copper-clad ceramic substrate, and the top copper-clad ceramic substrate can be achieved.

[0079] In some implementations, such as Figure 2 As shown, the copper layers corresponding to the DC potential, neutral point N potential, and output potential OUT in the bottom copper-clad ceramic substrate are distributed vertically, in the following order: the copper layer corresponding to the DC potential, the copper layer corresponding to the neutral point N potential, and the copper layer corresponding to the output potential OUT. The DC potential includes both positive and negative DC potentials.

[0080] The copper layers corresponding to the DC positive and DC negative potentials are distributed horizontally, in the order of the copper layer corresponding to the DC positive potential and the copper layer corresponding to the DC negative potential.

[0081] In some implementations, the pin of the drive gate of the switch S1 is adjacent to the copper layer corresponding to the DC positive potential.

[0082] The pin of the drive gate of the switching transistor S3 is adjacent to the copper layer corresponding to the output potential OUT.

[0083] By distributing the copper layers corresponding to the DC potential, neutral point N potential, and output potential OUT in the bottom copper-clad ceramic substrate along the vertical direction, the vertical current path can be optimized, achieving a compact side-by-side layout.

[0084] In some embodiments, the copper layers corresponding to the Y potential, X potential, and neutral point N potential in the top copper-clad ceramic substrate are distributed horizontally, in the order of copper layer corresponding to Y potential, copper layer corresponding to X potential, and copper layer corresponding to neutral point N potential.

[0085] In some implementations, the pin of the drive gate of the switch S2 is adjacent to the copper layer corresponding to the X potential.

[0086] The pin of the drive gate of the switching transistor S4 is adjacent to the copper layer corresponding to the Y potential.

[0087] By distributing the copper layers corresponding to the Y-potential, X-potential, and neutral point N-potential in the top copper-clad ceramic substrate along the horizontal direction, the horizontal current path can be optimized. Furthermore, the symmetrical configuration allows for equipotential interconnection between the copper layers at the neutral point N-potential of the bottom and top copper-clad ceramic substrates.

[0088] The integrated structure of the three-level midpoint clamping bridge arm switching unit in this embodiment achieves extremely low parasitic inductance in the commutation loop by connecting the three-level bridge arm circuit to a printed circuit board carrying the bus capacitor using two copper-clad ceramic substrates or other thermally conductive insulating materials. This is achieved through a very small integrated area and commutation loop structure. Furthermore, the double-sided heat dissipation characteristic and symmetrical configuration of this integrated structure provide relatively uniform DC thermal resistance and extremely low high-frequency thermal resistance to each switching transistor, improving heat dissipation and thus enhancing the safety of the three-level converter.

[0089] Example 3

[0090] To better understand the integrated structure of the three-level midpoint clamping bridge arm switch unit provided in this application embodiment, an exemplary description is given below in conjunction with a specific application implementation.

[0091] The three-level midpoint clamping bridge arm switch unit in this embodiment is generated by potting through the following steps.

[0092] Step 1: Connect the power semiconductor chip to the corresponding copper-clad ceramic substrate.

[0093] In step one, the power semiconductor chip should be sintered onto the top and bottom copper-clad ceramic substrates. This can be done by high-temperature soldering. At the same time, the heat sink can also be soldered to the top and bottom copper-clad ceramic substrates.

[0094] The overall switch unit structure is as follows Figure 1As shown in the figure. In this embodiment, there are a total of 4 switching transistors (S1, S2, S3, S4) and 2 power diodes (D5, D6). The switching transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), insulated-gate bipolar transistors (IGBTs), or vertical gallium nitride high electron mobility transistors (GaN HEMTs), which are represented by the MOSFET symbol in the figure.

[0095] The specific link location is as follows: Figure 2 and Figure 3 As shown. Switch 1, switch 3, and power diode 6 are soldered or sintered to their corresponding positions on the bottom copper-clad ceramic substrate, and switch 2, switch 4, and power diode 5 are soldered or sintered to their corresponding positions on the top copper-clad ceramic substrate.

[0096] In this configuration, the drain of switch 1 is connected to the node corresponding to the DC+ potential on the copper layer of the bottom copper-clad ceramic substrate. The drain of switch 2 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate. The drain of switch 3 is connected to the node corresponding to the OUT potential on the copper layer of the bottom copper-clad ceramic substrate. The drain of switch 4 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate. The cathode of power diode 5 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate. The cathode of power diode 6 is connected to the node corresponding to the N potential on the copper layer of the bottom copper-clad ceramic substrate.

[0097] Step 2: Perform ultrasonic bonding to bring out the gate pins of the power semiconductor chip.

[0098] In step two, ultrasonic bonding is typically performed using a bonding wire via an ultrasonic bonding machine. The starting position of the bonding wire is located at... Figure 4a and Figure 4b The gate surface and drive source surface of the chip structure shown, the termination position and trajectory reference Figure 2 and Figure 3 The diagram shows the gate leads for each switching transistor. Switches 1, 2, 3, and 4 all require the above operation.

[0099] Step 3: Weld the metal interlayer.

[0100] In step three, all power semiconductor chips must be connected to the metal interposer at a lower temperature. This lower temperature refers to a temperature not exceeding the high-temperature soldering temperature in step one. The height of the metal interposer should be a reasonable value to ensure mechanical fit. Six metal interposer blocks need to be connected to the sources of switching transistors 1, 2, 3, and 4, and the anodes of power diodes 5 and 6. Additionally, one extra metal interposer block should be connected to the copper layer corresponding to the N-potential of the underlying copper-clad ceramic substrate.

[0101] Step 4: Assemble and solder the PCB substrate and the copper-clad ceramic substrate.

[0102] In step four, a metal or graphite mold is used to align the printed circuit board substrate (PCB substrate) and the treated copper-clad ceramic substrate, so that the areas corresponding to the gate leads and the soldering areas corresponding to each voltage level on the PCB substrate coincide with the reserved PCB soldering areas on the copper-clad ceramic substrate. Soldering is performed at a lower temperature than in the previous steps.

[0103] This step simultaneously completes multiple electrical connections: connecting the source metal interposer of switch 1 to the top copper-clad ceramic substrate at the X potential; connecting the source metal interposer of switch 2 to the bottom copper-clad ceramic substrate at the OUT potential; connecting the source metal interposer of switch 3 to the top copper-clad ceramic substrate at the Y potential; connecting the source metal interposer of switch 4 to the bottom copper-clad ceramic substrate at the DC- potential; connecting the anode metal interposer of power diode 5 to the bottom copper-clad ceramic substrate at the N potential; connecting the anode metal interposer of power diode 6 to the top copper-clad ceramic substrate at the Y potential; connecting the metal interposer at the N potential to the top copper-clad ceramic substrate; connecting the drive gate leads of switches 1, 2, 3, and 4 to the printed circuit board substrate; connecting the drive source leads of switches 1, 2, 3, and 4 to the printed circuit board substrate; and connecting the copper layers of the copper-clad ceramic substrates and the printed circuit board copper layers corresponding to the DC+, DC-, N, and OUT levels. This completes the electrical connections of the three-level midpoint clamping bridge arm switch unit.

[0104] Step 5: Encapsulate the integrated structure to enhance insulation.

[0105] In step five, the electrical components are further reinforced with insulation protection. First, epoxy sealant or other sealing materials are used to seal the gap between the bottom copper-clad ceramic substrate and the printed circuit board. Then, a potting compound such as silicone gel is poured into the top of the switch unit and, after vacuum degassing, allowed to cure for 24 hours. A side view of the switch unit's structure is shown below. Figure 5 As shown in the figure, the housing is the external enclosure that contains the potting material. This completes the manufacturing of the three-level midpoint clamping bridge arm switch unit.

[0106] In this embodiment, during potting, the switching unit structure is sealed with epoxy resin and a housing at locations with lower electric field strength, while potting material is used for insulation at locations with higher electric field strength. Low-field-strength locations are any locations other than high-field-strength locations, where contact with or without potting material is acceptable. High-field-strength locations are areas with significant potential differences within the entire structure but close together, such as chip edges, copper layer edges and the contact points with the ceramic substrate, and gaps between different copper layers on the PCB. These locations require contact with potting material to ensure safe and stable electrical performance.

[0107] With appropriate processes, the potting process does not contaminate the heat dissipation surface. Potted switching units can be used reliably for extended periods. This process is compatible with classic power module manufacturing procedures. In the design example, the parasitic inductance of each loop can be reduced to below 10nH, with the commutation loop of the two modules (excluding the busbar section) below 4nH. This inductance induces only 40V at 10A / ns, significantly outperforming conventional busbar-power module switching units. Thanks to the double-sided heat dissipation design, thermal resistance can be reduced by one-third compared to the classic single-sided heat dissipation solution. The maximum chip-built thermal resistance coupling coefficient is 0.26, a significant increase compared to the coupling coefficient below 0.02 of conventional busbar-power module switching units, resulting in a substantial increase in the average temperature between chips.

[0108] It is understood that the various method embodiments mentioned above in this application can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0109] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of this application, and this application is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this application, and these modifications and improvements are also considered to be within the scope of protection of this application.

Claims

1. An integrated structure for a three-level midpoint clamping bridge arm switch unit, characterized in that, include: Bottom copper-clad ceramic substrate, top copper-clad ceramic substrate, and printed circuit board; The bottom copper-clad ceramic substrate carries half of the three-level bridge arm circuit, and the top copper-clad ceramic substrate carries the other half of the three-level bridge arm circuit. The printed circuit board carries a DC bus capacitor and is electrically interconnected with the bottom copper-clad ceramic substrate and the top copper-clad ceramic substrate, respectively.

2. The integrated structure according to claim 1, characterized in that, The half of the three-level bridge arm circuit includes: a switch S1, a switch S3, and a power diode D6; wherein the transistors in the switch S1 and the switch S3 are metal-oxide-semiconductor field-effect transistors. The drain of the switching transistor S1 is connected to the node corresponding to the DC positive potential on the copper layer of the bottom copper-clad ceramic substrate. The power source of the switch S1 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively; wherein, the X potential is the common node potential of the power source of the switch S1, the cathode of the power diode D5 and the drain of the switch S2; the power diode D5 and the switch S2 belong to the other half of the three-level bridge arm circuit. The drain of the switching transistor S3 is connected to the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate. The power source of the switch S3 is connected to the corresponding node of the Y potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively; wherein, the Y potential is the common node potential of the power source of the switch S3, the anode of the power diode D6 and the drain of the switch S4; the switch S4 belongs to the other half of the three-level bridge arm circuit. The cathode of the power diode D6 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate. The anode of the power diode D6 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively. The driving gate and driving source of the switching transistor S1, and the driving gate and driving source of the switching transistor S3, all have pins connected to the corresponding copper layer of the printed circuit board substrate.

3. The integrated structure according to claim 2, characterized in that, The half of the three-level bridge arm circuit also includes: 4 metal interposer blocks, namely metal interposer block MP1, metal interposer block MP3, metal interposer block MP6 and metal interposer block MP7. The metal interposer block MP1 is connected to the power source of the switch S1, the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate. The metal interposer block MP3 is connected to the power source of the switch S3, the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate. The metal interposer block MP6 is connected to the anode of the power diode D6, the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate, and the corresponding copper layer of the bottom copper-clad ceramic substrate, respectively. The metal interposer block MP7 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate.

4. The integrated structure according to claim 3, characterized in that, The other half of the three-level bridge arm circuit includes: switch S2, switch S4 and power diode D5; wherein, the transistors in switch S2 and switch S4 are metal-oxide-semiconductor field-effect transistors. The drain of the switching transistor S2 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate. The power source of the switching transistor S2 is connected to the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The drain of the switching transistor S4 is connected to the node corresponding to the Y potential on the copper layer of the top copper-clad ceramic substrate. The power source of the switching transistor S4 is connected to the node corresponding to the DC negative potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The cathode of the power diode D5 is connected to the node corresponding to the X potential on the copper layer of the top copper-clad ceramic substrate. The anode of the power diode D5 is connected to the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate and the corresponding copper layer of the top copper-clad ceramic substrate, respectively. The driving gate and driving source of the switching transistor S2, and the driving gate and driving source of the switching transistor S4, all have pins connected to the corresponding copper layer of the printed circuit board substrate.

5. The integrated structure according to claim 4, characterized in that, The other half of the three-level bridge arm circuit also includes: three metal interposer blocks, namely metal interposer block MP2, metal interposer block MP4 and metal interposer block MP5; The metal interposer block MP2 is connected to the power source of the switching transistor S2, the node corresponding to the output potential OUT on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate. The metal interposer block MP4 is connected to the power source of the switch S4, the node corresponding to the DC negative potential on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate. The metal interposer block MP5 is connected to the anode of the power diode D5, the node corresponding to the neutral point N potential on the copper layer of the bottom copper-clad ceramic substrate, and the corresponding copper layer of the top copper-clad ceramic substrate.

6. The integrated structure according to claim 4, characterized in that, The copper layers corresponding to the DC positive potential, DC negative potential, neutral point N potential, and output potential OUT in the bottom copper-clad ceramic substrate are connected to the corresponding copper layers in the printed circuit board. The copper layer corresponding to the neutral point N potential in the top copper-clad ceramic substrate is connected to the corresponding copper layer in the printed circuit board.

7. The integrated structure according to claim 6, characterized in that, The copper layers corresponding to the DC potential, the neutral point N potential, and the output potential OUT in the bottom copper-clad ceramic substrate are distributed vertically, and are in the following order: the copper layer corresponding to the DC potential, the copper layer corresponding to the neutral point N potential, and the copper layer corresponding to the output potential OUT; wherein, the DC potential includes the DC positive potential and the DC negative potential; The copper layers corresponding to the DC positive potential and the DC negative potential are distributed horizontally, and are, in order, the copper layer corresponding to the DC positive potential and the copper layer corresponding to the DC negative potential.

8. The integrated structure according to claim 7, characterized in that, The pin of the driving gate of the switching transistor S1 is adjacent to the copper layer corresponding to the DC positive potential. The pin of the driving gate of the switching transistor S3 is adjacent to the copper layer corresponding to the output potential OUT.

9. The integrated structure according to claim 6, characterized in that, The copper layers corresponding to the Y potential, X potential, and neutral point N potential in the top copper-clad ceramic substrate are distributed horizontally, and are in the following order: the copper layer corresponding to the Y potential, the copper layer corresponding to the X potential, and the copper layer corresponding to the neutral point N potential.

10. The integrated structure according to claim 9, characterized in that, The pin of the driving gate of the switching transistor S2 is adjacent to the copper layer corresponding to the X potential. The pin of the driving gate of the switching transistor S4 is adjacent to the copper layer corresponding to the Y potential.

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