ELECTRONIC CHIP WITH LOCALLY PATTERNED PERIPHERAL AREA intended to be adhered to A SUBSTRATE

Abstract

The present disclosure relates to an electronic chip having a locally patterned peripheral region intended to be bonded to a substrate. An electronic chip includes a first main surface intended to be bonded to a substrate, a second main surface, and a side surface. The second major surface includes a central region and a locally patterned peripheral region. The locally patterned peripheral region sequentially forms a first portion having a first thickness and a second portion having a second thickness from the central region. The first thickness is less than a thickness of the central region. The second thickness is greater than the first thickness and less than a thickness of the central region.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. FR2410574, filed on October 1, 2024, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to the field of electronic (integrated circuit) chips, and more specifically, to electronic chips to be bonded to a support. Background Technology

[0004] Electronic chips are sometimes assembled onto a support using an adhesive layer. However, the adhesive often flows up the sides of the chip, even covering part of the front surface, which can degrade its performance, contaminate the bonding pads on the front surface, and / or contaminate the tools used to handle it (e.g., pick-and-place tools). To avoid these drawbacks, the adhesive should not cover more than 80% of the chip thickness.

[0005] Currently, adhesive management is difficult to control during chip bonding due to various factors: the nature of the adhesive, the type of chip and the dicing performed, the chip thickness, and the substrate design.

[0006] There is a need to at least partially improve certain aspects of known methods for bonding electronic chips to external components (such as substrates). Summary of the Invention

[0007] The embodiments of this article include: an electronic chip including a first main surface, a second main surface and side surfaces, the first main surface being intended to be bonded to a substrate, the second main surface including a central region and a peripheral region, the peripheral region being locally patterned at a first edge, thereby sequentially forming a first portion having a first thickness and a second portion having a second thickness from the central region, the first thickness being less than the thickness of the central region, and the second thickness being greater than the first thickness and less than the thickness of the central region.

[0008] According to a particular embodiment, the chip further includes a third portion having a third thickness, the third thickness being less than the second thickness, the second portion being located between the first portion and the third portion.

[0009] According to a specific embodiment, the first thickness is less than the third thickness.

[0010] According to a particular embodiment, the peripheral region is patterned at a second edge, wherein the patterning at the first edge and the patterning at the second edge may be the same or different, and the second edge is preferably opposite to the first edge.

[0011] According to a specific embodiment, the peripheral region is patterned at the four edges of the chip, and the patterning of the four edges is preferably the same.

[0012] According to a specific embodiment, the second thickness is 40% to 90% of the thickness of the central region, preferably 50% to 80% of the thickness of the central region.

[0013] According to a specific embodiment, the central region has a thickness in the range of 50 μm to 250 μm, preferably 50 μm to 150 μm, and more preferably 50 μm to 80 μm.

[0014] According to a specific embodiment, the thickness difference between the first portion and the second portion is at least 2 μm and / or the width of the first portion is at least 5 μm, so as to be able to contain solvent before evaporation.

[0015] The embodiments of this document also include an assembly method comprising the steps of assembling the chip, as defined above, to the external component using an adhesive layer disposed between the chip and the external component.

[0016] Embodiments herein also include an assembly comprising a chip and external components, such as a substrate, as defined above, with an adhesive layer disposed between the chip and the external components. Attached Figure Description

[0017] In the remainder of the disclosure of the specific embodiments given by way of example and not limitation, the foregoing features and advantages, as well as other features and advantages, will be described in detail with reference to the accompanying drawings, wherein:

[0018] Figure 1 A side view and a cross-sectional view of a portion of an electronic chip according to a specific embodiment are schematically shown;

[0019] Figure 2 A schematic three-dimensional diagram of an electronic chip according to another specific embodiment is shown;

[0020] Figure 3 A side view and a cross-sectional view of a portion of an electronic chip according to another specific embodiment are schematically shown;

[0021] Figure 4 A side view and a cross-sectional view of a portion of an electronic chip according to another specific embodiment are schematically shown;

[0022] Figure 5 A side view and cross-sectional view of a portion of an assembly including an electronic chip and a substrate assembled by an adhesive layer, according to another specific embodiment, are schematically shown.

[0023] Figure 6 The image is a portion of an assembly comprising an electronic chip and a substrate assembled by an adhesive layer, according to another specific embodiment, obtained by an optical microscope.

[0024] Figure 7 The image is a portion of an assembly comprising an electronic chip and a substrate assembled by an adhesive layer, according to a comparative example, obtained by optical microscopy. Detailed Implementation

[0025] The components are not necessarily shown at a uniform scale to make the accompanying drawings more readable.

[0026] In the various figures, the same features are indicated by the same reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0027] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail.

[0028] For clarity, electronic components formed inside or on top of the substrate are not shown.

[0029] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than conductors; and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0030] In the following description, when referring to absolute positional qualifiers such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative positional qualifiers such as “upper,” “lower,” “above,” “below,” etc., or orientational qualifiers such as “horizontal,” “vertical,” etc., the direction is referred to in the accompanying drawings unless otherwise stated.

[0031] Unless otherwise stated, “about,” “approximately,” “basically,” and “around” indicate plus or minus 10%, preferably plus or minus 5%.

[0032] Unless otherwise stated, for the range X to Y, it is intended to include endpoints X and Y within that range.

[0033] Electronic components are used in a wide range of industrial sectors, particularly in the fields of microelectromechanical systems (MEMS), power amplifiers, proximity sensors, and optical modules.

[0034] Reference Figures 1 to 5 A more detailed description of the electronic (integrated circuit) chip 1000.

[0035] Chip 1000 includes a first main surface 100 and a second main surface 200.

[0036] The first primary surface 100 is the rear surface. It is the surface intended to be bonded to external components.

[0037] The second main surface 200 is the front surface. It is the active side. The chip 1000 may include one or more discrete components. Discrete components are selected from transistors, diodes, thyristors, triac switches, filters, etc. The chip may include one or more integrated electronic circuits. The chip enables the implementation of different electronic functions and can have a variety of applications. For illustration, the chip may be a MEMS, a power amplifier, an optical sensor, or a microcontroller. The second surface 200 also includes electrical connection pads (not shown).

[0038] The main surfaces 100 and 200 are, for example, rectangles.

[0039] Chip 1000 also includes sidewalls, typically four sidewalls 301, 302, 303, and 304, which are created by dicing a semiconductor wafer. The sidewalls couple the first main surface 100 to the second main surface 200.

[0040] The second main surface 200 includes a central region 210 and a peripheral region 220. The peripheral region 220 surrounds the central region 210.

[0041] The active area and connection pads of chip 1000 are located in the central area 210.

[0042] The central region 210 has a thickness corresponding to the thickness of the chip substrate.

[0043] The peripheral region 220 is located on the edge of the second main surface 200. In the case of a rectangular main surface, the peripheral region is located on the four edges of the main surface.

[0044] The surrounding area 220 does not include components: it is a sacrifice area.

[0045] The surrounding area is locally patterned. This localized patterning does not hinder the chip's operation.

[0046] Patterning allows for the creation of multiple interfaces on one or more edges of the chip 1000. During the bonding of the chip 1000 to the external component 300 via its rear surface 100, these interfaces slow down (hinder) or even stop the adhesive and prevent the adhesive from completely covering the sidewalls of the chip 1000.

[0047] At least one edge of the peripheral region 220 is patterned. Preferably, two edges of the peripheral region are patterned, with the patterned edges facing each other. All edges of the peripheral region can be patterned. In other words, patterning is performed all around the second surface 200.

[0048] According to alternative embodiments, such as Figures 1 to 3 and Figure 5 As shown, the patterning of one or more edges of the peripheral region 220 from the central region 210 to the edge of the chip 1000 includes: a first portion 221 having a first thickness, a second portion 222 having a second thickness, and a third portion 223 having a third thickness.

[0049] According to another embodiment, for example, Figure 4 As shown, the patterning of one or more edges of the peripheral region from the central region 210 toward the edge of the chip 1000 includes: a first portion 221 having a first thickness and a second portion 222 having a second thickness.

[0050] Thickness refers to the dimension along the z-axis.

[0051] The width of a given portion is defined along the y-axis.

[0052] According to these alternative embodiments, either the second portion 222 or the third portion 223 forms a shoulder on one of the side surfaces 301, 302, 303, 304. This shoulder allows for slowing down the progress of the adhesive 400.

[0053] The second portion 222 enables the progress of the adhesive 400 to be stopped. The second portion has a width, for example, greater than 2 μm. The second thickness is, for example, at least 40% of the thickness of the central region 210, or even at least 50% of the thickness of the central region 210. The second thickness is, for example, at most 90% of the thickness of the central region 210, or even at most 80% of the thickness of the central region 210.

[0054] The thickness of the first portion 221 is less than the thickness of the central portion 210 and less than the thickness of the second portion 222. The first portion 221 is formed between the central region 210 and the second portion 222. The first portion 221 forms a groove in the peripheral region 220. During assembly with an external component 300 (e.g., a substrate) via the adhesive layer 400, this groove will allow for the containment of adhesive solvent. It also prevents the adhesive from advancing toward the central region 210 because the thickness of the first portion 221 is less than the thickness of the central region 210.

[0055] The thickness difference between the first portion 221 and the second portion 222 is, for example, at least 2 μm. The width of the first portion is, for example, at least 5 μm. The formed chamber allows for the containment of the adhesive solvent before the adhesive evaporates.

[0056] Using such a chip, adhesive 400 does not cover more than 80% of the chip thickness. It covers, for example, between 20% and 80% of the thickness of chip 1000.

[0057] As a non-restrictive statement, such as Figure 1 The patterning of chips with a thickness greater than 50 μm (e.g., 70 μm or 80 μm) can have the characteristics given in Table 1:

[0058]

[0059] As a non-restrictive statement, such as Figure 4 The patterning of chips with a thickness greater than 50 μm (e.g., 70 μm or 80 μm) can have the characteristics given in Table 2:

[0060]

[0061] One or more edges of portions 221, 222, and 223 of the surrounding area 220 may be beveled, such as, for example Figure 5 As shown. In other words, they can have bevels or chamfers.

[0062] Such a chip 1000 can be formed by performing one or more laser cutting and / or mechanical cutting and / or plasma etching steps.

[0063] Chip 1000 can be assembled to external component 300 via adhesive layer 400. Adhesive layer 400 is disposed between the first surface 100 of chip and external component 300.

[0064] Due to the patterning of the chip's periphery 220, the travel of the adhesive 400 stops at the second portion 222. Even for chips with low thickness (typically less than 100 μm), the adhesive layer 400 does not rise to more than 80% of the chip thickness (i.e., the thickness of the central region).

[0065] Using such a chip, not only can a wide range of devices be used, especially cheaper ones, but also a wider selection of adhesives can be applied.

[0066] This reduces the number of control steps required for assembly, thus improving efficiency.

[0067] The adhesives that can be used in this assembly method are, for example, epoxy or silicone adhesives. The adhesive may contain particles, such as insulating or conductive particles. The insulating particles may be alumina or silica particles. The conductive particles may be silver and / or copper particles.

[0068] In the test, a 70μm thick chip was patterned and bonded to a substrate as previously described. The adhesive traveled upwards along the chip's sidewalls, but covered less than 80% of the sidewall thickness. Figure 6 ).

[0069] If the chip is not patterned, the adhesive can travel upwards until it completely covers the sidewalls of the chip, even for chips with very large thicknesses (typically greater than 200 μm, e.g., 230 μm). Figure 7 ).

[0070] The 1000 chip can be applied to a wide range of industrial sectors, particularly the automotive industry, and in personal electronics, especially in communication equipment, computers, and peripherals. It can also be used in new GaN technologies, power packaging, and electronic amplifiers.

[0071] These can be, for example, 5G connectivity devices or more general connectivity devices.

[0072] They can also be advanced driver assistance systems (ADAS).

[0073] The electronic chip 1000 can be used in smartphones or for the Internet of Things (IoT). The device can connect via, for example, 5G, Wi-Fi, or ultra-wideband (UWB).

[0074] Electronic Chip 1000 may also be of interest in other fields, such as industrial applications, particularly in green energy.

[0075] Such applications are given as illustrations and are not restrictive.

[0076] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will be readily apparent to those skilled in the art.

[0077] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An electronic chip, comprising: A first main surface, the first main surface being configured for adhesion to a substrate; Second primary surface; Side surface; The second main surface includes a central area and a peripheral area; The peripheral area has a partial pattern at the first edge, and the partial pattern is formed sequentially from the central area: A first portion of the surrounding area, the first portion having a first thickness; The second part of the surrounding area, the second part having a second thickness; and The third portion of the surrounding area, said third portion having a third thickness; The second part is located between the first and third parts; The first thickness is less than the thickness of the central region; Wherein, the second thickness is greater than the first thickness and less than the thickness of the central region; and The third thickness is less than the second thickness.

2. The chip according to claim 1, wherein, Each of the first, second, and third portions includes a surface that defines a first thickness, a second thickness, and a third thickness, respectively, the surfaces extending parallel to the first and second main surfaces.

3. The chip according to claim 1, wherein, The first thickness is less than the third thickness.

4. The chip according to claim 1, wherein, The surrounding area is patterned at the second edge, wherein the patterning at the first edge is the same as the patterning at the second edge, and the second edge is preferably opposite to the first edge.

5. The chip according to claim 1, wherein, The surrounding area is patterned at the second edge, wherein the patterning at the first edge is different from the patterning at the second edge, and the second edge is preferably opposite to the first edge.

6. The chip according to claim 1, wherein, The surrounding area is patterned at all edges of the chip, and the patterning is the same at all edges.

7. The chip according to claim 1, wherein, The second thickness is 40% to 90% of the thickness of the central region.

8. The chip according to claim 1, wherein, The second thickness is 50% to 80% of the thickness of the central region.

9. The chip according to claim 1, wherein, The central region has a thickness ranging from 50 μm to 250 μm.

10. The chip according to claim 1, wherein, The central region has a thickness ranging from 50 μm to 150 μm.

11. The chip according to claim 1, wherein, The central region has a thickness ranging from 50 μm to 80 μm.

12. The chip according to claim 1, wherein, The thickness difference between the first part and the second part is at least 2 μm.

13. The chip according to claim 1, wherein, The width of the first part must be at least 5 μm.

14. An assembly method comprising the step of assembling the chip of claim 1 to an external element by means of an adhesive layer disposed between a first main surface of the chip and an external element during said step.

15. An assembly comprising: The chip according to claim 1; as well as External components forming the substrate; as well as An adhesive layer disposed between the first main surface of the chip and external components.

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