Method and system for manufacturing integrated circuit device and non-transitory computer readable medium

Abstract

A method of generating a layout of an integrated circuit (IC) device includes receiving a layout of the IC device, the IC layout including a gate region having a first width across an active region and a first gate via at a first location along the first width; constructing a gate resistance compact network, the compact network comprising at least four nodes of the three-dimensional transistor architecture represented by the layout map and at least five equivalent resistances between respective ones of the at least four nodes; determining the effective resistance of the gate region based on the equivalent resistance; and determining whether the effective resistance meets the design specification. The embodiment of the invention also provides a method, a system and a non-transitory computer readable medium for manufacturing the integrated circuit device.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to methods and systems for manufacturing integrated circuit devices and non-transitory computer-readable media. Background Technology

[0002] The mainstream trend towards miniaturization of integrated circuits (ICs) has led to the development of increasingly compact devices that consume less power while delivering enhanced functionality at a faster pace than previous technologies. This miniaturization is enabled by advancements in design and manufacturing that adhere to increasingly stringent specifications. Various electronic design automation (EDA) tools are employed to create, modify, and verify semiconductor device designs, ensuring compliance with design and manufacturing specifications. Summary of the Invention

[0003] One embodiment of the present invention provides a method for manufacturing an integrated circuit (IC) device, the method comprising: receiving a layout of the integrated circuit (IC) device, the layout including: a gate region having a first width spanning an active region, and a first gate via located at a first position along the first width; constructing a gate resistor compact network, the gate resistor compact network including at least four nodes of a three-dimensional transistor architecture represented by the layout and at least five equivalent resistances between corresponding nodes of the at least four nodes; determining an effective resistance of the gate region based on the equivalent resistances in the gate resistor compact network; determining whether the effective resistances conform to design specifications; and modifying the layout to facilitate compliance when the effective resistances are non-compliant.

[0004] Another embodiment of the present invention provides a system for manufacturing an integrated circuit (IC) device, the system including a processor and a non-transitory computer-readable storage medium containing computer program code for one or more programs, the non-transitory computer-readable storage medium, the computer program code, and the processor being configured to cause the system to perform at least the following operations: receiving a layout of the IC device, the layout including: a gate region having a first width spanning a first isolation region, an active region, and a second isolation region; a first gate via located at a first position along a second width spanning the active region; and a second gate via located at a first edge of the gate region; constructing a gate resistor compact network including at least four nodes of a three-dimensional transistor architecture represented by the layout and at least five equivalent resistances between corresponding nodes of the at least four nodes; determining an effective resistance of the gate region based on the equivalent resistances in the gate resistor compact network; and performing circuit simulation based on the effective resistances.

[0005] Another embodiment of the present invention provides a non-transitory computer-readable medium having stored thereon computer-executable instructions representing a method for generating an IC layout of an integrated circuit (IC) device, the computer-executable instructions being executable by at least one processor to perform the method, the method comprising: receiving a layout of the IC device, the layout including: a gate region having a first width spanning an active region, and a first gate via located at a first position along the first width; selecting at least four nodes and a gate structure of the IC device; modeling the gate region using a gate resistor compact network, the gate resistor compact network including the at least four nodes and corresponding at least five equivalent resistances located between each pair of nodes in the at least four nodes; and determining whether the layout conforms to design specifications based on the gate resistor compact network. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best provide a comprehensive understanding of all aspects of this disclosure. It should be emphasized that, in accordance with industry standard practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments of the present disclosure.

[0008] Figure 2A This is a layout diagram of an integrated circuit device showing multiple locations on the gate region according to some embodiments of the present disclosure.

[0009] Figure 2B It is based on Figure 2A The embodiment illustrates a layout diagram of an integrated circuit device with gate vias arranged on the gate region.

[0010] Figure 3A and Figure 3B This is a semiconductor structure diagram of a FinFET according to some embodiments of the present disclosure.

[0011] Figure 4A and Figure 4B This is a semiconductor structure diagram of a nanosheet field-effect transistor (FET) according to some embodiments of the present disclosure.

[0012] Figure 5A This is a schematic diagram of four nodes within a three-dimensional transistor architecture according to some embodiments of the present disclosure.

[0013] Figure 5B This is a schematic diagram of a 5-resistor diamond gate resistor network according to some embodiments of the present disclosure.

[0014] Figures 6A to 6F This is a diagram illustrating different networks equivalent to a 5-resistor rhombic gate resistor network using Δ-Y (triangle-star) transformation technology according to some embodiments of this disclosure.

[0015] Figures 7A to 7D These are simplified diagrams of different networks illustrated according to some embodiments of this disclosure.

[0016] Figures 8A to 8C This is a layout diagram illustrating, according to some embodiments of the present disclosure, an extension spanning the gate regions of two transistor devices and gate vias disposed at different locations thereon.

[0017] Figures 9A to 9F This is a layout diagram of various arrangements of gate vias according to different embodiments of the present disclosure.

[0018] Figures 10A to 10F They correspond to respectively Figures 9A to 9F A cross-sectional view of the layout diagram.

[0019] Figures 11A to 11H These are layout diagrams illustrating different gate via arrangements according to some embodiments of this disclosure.

[0020] Figure 12 This is a block diagram of an integrated circuit device design system 1200 according to some embodiments of the present disclosure.

[0021] Figure 13 This is a block diagram of an integrated circuit manufacturing system 1300 and an associated integrated circuit manufacturing process according to some embodiments of the present disclosure. Detailed Implementation

[0022] The following disclosure provides various embodiments or examples for implementing different features of the provided subject matter. To simplify this disclosure, examples of specific components and arrangements are described below. These are, of course, merely examples and not limiting descriptions. For example, in the subsequent description, a first component may be formed on or above a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetitions are for the purpose of brevity and clarity only and do not in themselves constitute an association between the discussed embodiments and / or configurations.

[0023] Furthermore, to facilitate the description of the relationship between the elements or components shown in the accompanying drawings and other elements or components, spatial relative terms may be used herein, such as "below," "under," "lower," "above," "on top," "upper," "on," etc. In addition to the orientations shown in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0024] Furthermore, it should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected to or coupled to that other element, or there may be an intermediary element.

[0025] The embodiments or examples shown in the accompanying drawings are disclosed below in specific language. However, it should be understood that these embodiments and examples are not limiting descriptions. Those skilled in the art will recognize that any changes or modifications made to the disclosed embodiments, and any further application of the principles disclosed in this document, are within the conventional scope.

[0026] Furthermore, it should be understood that some processing steps and / or components of the device may be described only briefly. Additional processing steps and / or components may be added, or certain processing steps and / or components described below may be removed or modified, while still fulfilling the claims. Therefore, it should be understood that the following description is merely illustrative and does not imply that one or more steps or components must be included.

[0027] Additionally, reference numerals and / or letters may be repeated in various examples. Such repetitions are for the purpose of brevity and clarity only and do not in themselves constitute an association between the various embodiments and / or configurations discussed.

[0028] According to some embodiments, the effective gate resistance of an IC device is modeled using a gate resistance compact network, which includes at least four nodes of a three-dimensional transistor architecture represented by a layout diagram and at least five equivalent resistances between corresponding nodes of the at least four nodes. The gate resistance compact network of at least some embodiments is based on one or more gate via locations along the gate width in the IC device layout diagram. Another method for determining the effective gate resistance uses at least four nodes, but uses fewer than five equivalent resistances between corresponding nodes of the at least four nodes. Compared to the other method, the gate resistance compact network of at least some embodiments can estimate the gate resistance value more accurately.

[0029] In various embodiments, the symbols A, B, C, and G may refer to different locations within different layout diagrams, or to different nodes within different semiconductor structure cross sections.

[0030] Figure 1This is a flowchart of an IC device manufacturing method according to some embodiments of the present disclosure. According to some embodiments, manufacturing the IC device includes generating a layout pattern of the IC device. According to some embodiments, generating the layout pattern of the IC device includes modeling the IC device based on an initial layout pattern of the IC device, the initial layout pattern including a gate region having a width spanning an active region and at least one gate via located along the width. According to some embodiments, modeling the IC device includes modeling the gate region using a 5-resistor diamond gate resistor network.

[0031] According to some embodiments, modeling the IC device includes modeling transistors, such as planar transistors, FinFETs, nanosheet FETs, nanowire FETs, or other suitable types of transistors. According to some embodiments, the transistor is one of a plurality of transistors included in the IC device, and non-limiting examples include memory circuits, logic devices, processing devices, signal processing circuits, etc.

[0032] According to some embodiments, method 100 is partially or entirely executed by a computer processor. According to some embodiments, method 100 is partially or entirely executed by the method described below. Figure 12 The processor 1202 of the EDA system 1200 discussed is executed. Some or all of the operations of method 100 can be performed as a design (e.g., in conjunction with the following). Figure 13 The design process implemented in the design room (1320) is discussed in part.

[0033] According to some embodiments, the operation of method 100 is as follows: Figure 1 The steps are executed in the order shown. According to some embodiments, the operation of method 100 differs from... Figure 1 The operations are executed sequentially as shown. According to some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 100. The operations of method 100 use the methods discussed below. Figures 2A to 2B , Figures 3A to 3B , Figures 4A to 4B , Figures 5A to 5B , Figures 6A to 6F , Figures 7A to 7D , Figures 8A to 8C , Figures 9A to 9F , Figures 10A to 10F as well as Figures 11A to 11H Please provide an explanation.

[0034] Figure 2A This is an IC device layout diagram according to some embodiments of the present disclosure, which shows multiple locations on the gate region. Figure 2B It is based on Figure 2A An IC device layout diagram of an embodiment shows a gate via disposed on the gate region.

[0035] According to some embodiments, layout diagram 200A has a direction X and a direction Y perpendicular to direction X. The orientations of layout diagrams 200A and 200B relative to directions X and Y are merely non-limiting examples for illustrative purposes. According to some embodiments, the orientations of layout diagrams 200A and 200B relative to directions X and Y may differ. Figure 2A and Figure 2B The orientation shown.

[0036] According to some embodiments, layout diagram 200A includes an active region 204, a gate region 206, and isolation regions 220 and 222. The active region (AR) 204 is a region included in the layout diagram as a portion of an active region (also referred to as oxide diffusion or definition (OD)) in a semiconductor substrate in which one or more IC device components (e.g., source / drain regions) are formed within a manufacturing process. In various embodiments, the active region is an N-type or P-type active region of a planar transistor, a fin field-effect transistor, or a nanosheet FET. According to some embodiments, the gate region 206 is a region included in the layout diagram as a portion of a gate structure in an IC device comprising at least one of a conductive material and a dielectric material within a manufacturing process. In various embodiments, the gate structure corresponding to gate region 206 includes at least one conductive material (e.g., a metal and / or polysilicon) overlying at least one dielectric material (e.g., silicon dioxide and / or a high-k dielectric material).

[0037] According to some embodiments, an active region 204 is formed between isolation regions 220 and 222, which may be a shallow trench isolation (STI) region. An edge EG1 exists between the active region 204 and the isolation region 220, while an edge EG2 exists between the active region 204 and the isolation region 222. According to some embodiments, position A may be disposed on a first edge where the gate region 206 overlaps with the isolation region 220, and position C may be disposed on a second edge of the gate region 206 that overlaps with the isolation region 222, the second edge being opposite to the first edge. Furthermore, a plurality of positions P1 to Pn may be disposed on the portion of the gate region 206 that overlaps with the active region 204. Positions P1 and Pn may be located at the first edge of the active region 204 and the second edge opposite to the first edge. Gate region 206 extends from position A (located at the first edge of gate region 206) to position C (located at the second edge of gate region 206 opposite to the first edge), spanning active region 204 and isolation regions 220 and 222, thereby defining a width W1 along the Y direction. Specifically, gate region 206 has widths W2, d1, and d2 along the Y direction, spanning active region 204 and isolation regions 220 and 222, respectively. Furthermore, widths d1 and d2 may be substantially equal. According to some embodiments, position Pm (also referred to as position G) is the midpoint along width W1 between position A and position C. According to some embodiments, gate region 206 extends beyond one or both positions A and C.

[0038] According to some embodiments, one or more gate vias may be formed on the gate region 206, for example... Figure 2B The gate via VG1 is shown. For example, gate via VG1 may be disposed on the portion where gate region 206 overlaps with active region 204. Furthermore, depending on design requirements, gate via VG2 may be disposed at location A of gate region 206, and gate via VG3 may be disposed at location C of gate region 206. Each gate via VG1 to gate via VG3 is a region included in a layout diagram as part of one or more segments defining one or more conductive layers in an IC device within the manufacturing process. This segment is configured to form an electrical connection between a gate structure corresponding to gate region 206 and a conductive layer segment covering the gate structure. In various embodiments, the one or more conductive layer segments formed based on each gate via contain metal (e.g., copper) and form an electrical connection with metal layer 0, metal layer 1, or metal layer 2 of the IC device.

[0039] In various embodiments, layouts 200A and 200B, in addition to the active region 204, gate region 206, and gate vias VG1 to VG3, also include areas not in... Figure 2A and Figure 2BAdditional components shown (such as one or more additional active regions, gate regions and / or gate vias, and / or one or more isolation regions, source / drain regions, well regions and / or interconnect components) are not illustrated for clarity.

[0040] Figure 3A and Figure 3B This is a semiconductor structure diagram of a finned field-effect transistor according to some embodiments of this disclosure. Please also refer to... Figure 2B as well as Figures 3A to 3B .

[0041] According to some embodiments, Figure 3A The semiconductor structure 300 shown corresponds to Figure 2B The layout diagram 200B shows a cross-sectional view of a finned field-effect transistor, which is a top view of a semiconductor structure 300. For example, the semiconductor structure 300 includes a substrate 302 containing upwardly projecting fins 304. According to some embodiments, the semiconductor structure 300 also includes an isolation region 308 separated by the fins 304, a gate dielectric layer 301 (e.g., silicon dioxide) disposed over the fins 304 and the isolation region 308, a gate electrode 306 disposed over the gate dielectric layer 301, and a gate via (or gate contact) 310 disposed on the gate electrode 306. Specifically, Figure 3A The gate electrode 306, fin 304, and gate via 310 can respectively correspond to Figure 2B The fin 304, active region 204, and gate via VG1 are shown in the diagram. It should be noted that the total width of the fin 304 and the isolation region 308 is approximately equal to... Figure 2B The width W1 in layout diagram 200B. For simplicity, the gate via 310 is disposed on the gate electrode 306 at the midpoint of the width W1 (e.g., position Pm or position G).

[0042] According to some embodiments, the gate dielectric layer 301 may be made of a high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, other suitable materials, or any combination thereof, and may be fabricated by chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable techniques, or any combination thereof. According to some embodiments, the gate electrode 306 may be made of titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, other suitable materials, or any combination thereof, and may be fabricated by physical vapor deposition (PVD), other suitable techniques, or any combination thereof.

[0043] According to some embodiments, when the gate via 310 receives a voltage signal to activate the fin field-effect transistor corresponding to the semiconductor structure 300, a signal path CP1 is established from the gate via 310 to a first side of the fin 304, and a signal path CP2 is established from the gate via 310 to a second side of the fin 304 opposite to the first side, thereby forming a channel around the fin 304. Furthermore, for descriptive purposes, Figure 3B The diagram illustrates the equivalent (or effective) resistances 322 (e.g., solid black rectangles) corresponding to multiple segments within the gate electrode 306, as well as the transistors formed on different sides of the fin 304. These equivalent resistances 322 can be simplified and modeled using a 5-resistor diamond gate resistor network, the details of which will be discussed later. Figure 5A and Figure 5B The embodiments are described below.

[0044] Figure 4A and Figure 4B This is a schematic diagram of a nanosheet FET semiconductor structure according to some embodiments of this disclosure. Please also refer to... Figure 2B as well as Figures 4A to 4B .

[0045] According to some embodiments, Figure 4A The semiconductor structure 400 shown corresponds to Figure 2B The layout diagram 200B shows a cross-sectional portion of a nanosheet FET or nanowire FET, which is a top view of a semiconductor structure 400. For example, the semiconductor structure 400 includes a substrate 402 containing upwardly projecting fins 403. According to some embodiments, the semiconductor structure 400 also includes isolation regions 408 separated by the fins 403, a plurality of nanostructures 404 disposed above the substrate 402 and the fins 403, a plurality of gate dielectric layers 401 disposed above the substrate 402 and the fins 403 and surrounding the nanostructures 404, and a gate electrode 406 disposed above the gate dielectric layers 401. Specifically, Figure 4A The gate electrode 406, nanostructure 404, and gate via 410 can respectively correspond to Figure 2B The nanostructure 404 comprises the gate region 206, the active region 204, and the gate via VG1. It should be noted that the total width of the nanostructure 404 and the isolation region 408 is approximately equal to... Figure 2B The width W1 in layout diagram 200B. For simplicity, the gate via 410 is disposed on the gate electrode 406 at the midpoint of the width W1 (e.g., position Pm or position G).

[0046] According to some embodiments, the gate dielectric layer 401 may be made of a high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, other suitable materials, or any combination thereof, and may be fabricated by chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable techniques, or any combination thereof. According to some embodiments, the gate electrode 406 may be made of titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, other suitable materials, or any combination thereof, and may be fabricated by physical vapor deposition (PVD), other suitable techniques, or any combination thereof.

[0047] According to some embodiments, when the gate via 410 receives a voltage signal to activate the nanosheet FET or nanowire FET corresponding to the semiconductor structure 400, a signal path CP3 is established from the gate via 410 to a first side of the fin 403, and a signal path CP4 is established from the gate via 410 to a second side of the fin 403 opposite to the first side. Since the gate electrode 406 surrounds the nanostructure 404, a channel is formed within each nanostructure 404. Furthermore, for descriptive purposes, Figure 4B The diagram illustrates the equivalent resistances 422 (e.g., solid black rectangles) corresponding to multiple segments within the gate electrode 406, as well as the transistors formed on different sides of each nanostructure 404. These equivalent resistances 422 can be simplified and modeled using a 5-resistor diamond gate resistor network, the details of which will be discussed later. Figure 5A and Figure 5B The embodiments are described below.

[0048] Figure 5A This is a schematic diagram of four nodes within a three-dimensional transistor architecture according to some embodiments of the present disclosure. Figure 5B This is a schematic diagram of a 5-resistor diamond gate resistor network according to some embodiments of the present disclosure.

[0049] According to some embodiments, four nodes A, B, C, and G can be constructed within a semiconductor structure of a three-dimensional transistor (e.g., semiconductor structure 300 or semiconductor structure 400), wherein nodes A, B, and C can be considered as non-gate nodes, and node G is a gate node. Figure 5A As shown in Figure 500A. According to some embodiments, node B may refer to… Figure 3A The position of the gate via 310 shown or Figure 4A The location of the gate via 410 is shown. Nodes A and C can refer to locations on two opposite edges of the gate region, while node G can refer to the device gate, depending on the semiconductor structure of the transistor device.

[0050] According to some embodiments, a 5-resistor diamond gate resistor network 500B is constructed using nodes A, B, C, and G to estimate the gate resistance of a fin field-effect transistor or nanosheet FET. For example, the principle of constructing the 5-resistor diamond gate resistor network 500B is as follows: Each non-gate node A, B, and C has at least two resistors connected to it, while the gate node G has three resistors connected to it. Furthermore, the gate node G is connected to each non-gate node A through node C. Therefore, a 5-resistor diamond gate resistor network 500B with four nodes can be constructed. Specifically, if "degree" represents the number of edges connected to a vertex or node, then the degrees of nodes A, B, C, and G are 2, 3, 2, and 3, respectively.

[0051] According to some embodiments, utilizing graph theory concepts, nodes A, B, and G can be considered as vertices of triangular mesh 501, where resistor R2 represents the equivalent resistance between nodes A and B, resistor R4 represents the equivalent resistance between nodes A and G, and resistor R1 represents the equivalent resistance between nodes B and G. Similarly, nodes B, C, and G can be considered as vertices of triangular mesh 502, where resistor R3 represents the equivalent resistance between nodes B and C, resistor R5 represents the equivalent resistance between nodes C and G, and resistor R1 represents the equivalent resistance between nodes B and G.

[0052] According to some embodiments, in three-dimensional transistor architectures (e.g., semiconductor structure 300 of a fin field-effect transistor or semiconductor structure 400 of a nanosheet FET), one or more gate vias are allowed on top of the transistor device, thus significantly increasing the number of transient signal paths (e.g., 10 paths or electrical requirements) compared to planar transistor architectures. Therefore, EDA tools must consider horizontal gate resistance, vertical gate resistance, and inter-chip gate resistance, resulting in a significant difference in the process target for effective gate resistance compared to planar transistor devices. Five of the 10 electrical requirements are selected as representative signal paths affecting circuit performance. According to some embodiments, these 10 electrical requirements may include, but are not limited to, the equivalent resistance R. A-G ,R B-G ,R C-G ,R AB-G ,R BC-G ,R AC-G ,R ABC-G ,R A-B ,R B-C , and R A-C .

[0053] For example, R A-G This can represent the equivalent resistance of the gate region, where node A receives the input voltage signal and node G acts as the output node. Similarly, R AC-GThis can represent the equivalent resistance of the gate region, where nodes A and C are short-circuited and receive the same or different voltage signals, and node G serves as the output node. Other equivalent resistances in the 10 electrical requirements can be derived in a similar manner.

[0054] Therefore, a 5-resistor rhombic gate resistor network 500B can be expressed as a half-side data structure of two non-overlapping triangular meshes 501 and 502 sharing a common edge (e.g., resistor R1). It should be noted that the 5-resistor rhombic gate resistor network 500B is a "compact" network, meaning that in this network structure, no node or resistor can be simplified by other nodes or resistors due to redundancy. Therefore, 5 electrical requirements, such as resistor R... B-G R AB-G R BC-G R ABC-G and R A-C This can be selected for layouts that include contacts (e.g., gate vias, abbreviated as VG) falling on active regions (e.g., OD or AR). The proposed 5-resistor diamond gate resistor network can be used to solve the five process objectives of the five equations.

[0055] According to some embodiments, the resistor R B-G R AB-G R BC-G R ABC-G and R A-C The following model can be modeled using equations (1) to (5).

[0056] R B-G = R1 / / (R2+R4) / / (R3+R5) = Rg / a (1)

[0057] R AB-G =R1 / / R4 / / (R3+R5)=Rg / b(2)

[0058] R BC-G =R5 / / R1 / / (R2+R4)=Rg / c(3)

[0059] R ABC-G = R1 / / R4 / / R5 = Rg / d (4)

[0060] R A-C = F2+(R2+F1) / / (R4+F3) = Rg / e (5)

[0061] In equations (1) to (5), Rg represents the effective gate resistance or the effective resistance of the gate region. The parameters F1, F2, and F3 used in equation (5) can be calculated using equations (6) to (8) as follows.

[0062] F1=R1*R3 / (R1+R3+R5)(6)

[0063] F2 = R3*R5 / (R1+R3+R5) (7)

[0064] F3 = R1*R5 / (R1+R3+R5) (8)

[0065] Therefore, the EDA tool can calculate at least one effective set Ri (i = 1 to 5) of the five process objectives of the five equations, indicating that the values ​​a to e in equations (1) to (5) can be calculated to obtain the effective gate resistance Rg.

[0066] Figures 6A to 6F Different networks, 600A to 600F, are shown, which use the Δ-Y transform technique equivalent to... Figure 5B The 5-resistor diamond gate resistor network 500B shown is illustrated, where nodes A, B, C, and G are labeled. According to some embodiments, a Δ-Y transformation is used from... Figure 5B Any equivalent network obtained from the 5-resistor rhombic gate resistor network 500B shown is also within the scope of this disclosure. The Δ-Y transformation is a mathematical technique used in circuit analysis to simplify complex resistor networks. It allows conversion between delta (Δ) and star (Y) configurations, making it easier to analyze circuits that cannot be simplified using only series and parallel combinations. In a delta configuration, the three resistors are connected in a delta configuration, while in a star configuration, the three resistors are connected in a Y configuration with a common central node. This transformation involves calculating the equivalent resistance for each configuration such that the electrical behavior (with respect to the resistance between any two terminals) remains the same.

[0067] According to some embodiments, networks with redundant resistors that can be simplified using Δ-Y transform techniques cannot be considered "compact networks." For example, although Figure 7A The network 700A shown includes four nodes A, B, C, and G. Network 700A includes redundant resistors and can be simplified to... Figure 7B Network 700B is shown in the diagram. For example, since there is no equivalent resistance between node B and node G, node B is simplified and eliminated from network 700A to obtain network 700B. However, Figure 7B The network 700B shown is not yet a compact network because two resistors are connected in parallel between nodes A and G, and two resistors are connected in parallel between nodes C and G. Therefore, network 700B can be simplified to network 700C with three nodes A, C, and G, and three resistors, as shown. Figure 7CAs shown. Furthermore, since the resistor between nodes A and C in network 700C is not on the shortest path between nodes A and C, network 700C can be further simplified to... Figure 7D The network 700D is shown in the diagram. Network 700D can be considered as a metric space, which is topologically compact. However, due to the absence of node B, network 700D is not equivalent to the 5-resistor diamond gate resistor network 500B.

[0068] Now attention is being redirected Figure 2B A single gate via VG1 is disposed at location G in the gate region 206 (e.g., excluding gate vias VG2 and VG3). For illustrative purposes, layout diagram 200B may correspond to Figure 3A The semiconductor structure 300 of the finFET shown is... Figure 4A The semiconductor structure 400 of the nanosheet FET is shown. For simplicity, it is assumed that the gate region 206 has a fixed resistance of approximately 1000 ohms from position A to position C. Geometrically, the equivalent resistance R from position A to position G is... A-G It is approximately 500 ohms. Furthermore, using the proposed 5-resistor rhombic gate resistor network, this EDA tool can also calculate the equivalent resistance R from position A to position G. A-G It is approximately 500 ohms, and for a finFET, the resistance R from position B to position G is... B-G It is approximately 300 ohms, or approximately 450 ohms for a nanosheet FET.

[0069] According to some other embodiments, two gate vias VG1 and VG2 are respectively disposed at position G and position A of the gate region 206 (e.g., excluding gate via VG3). Geometrically, the equivalent resistance R from position A to position G is... A-G It is approximately 500 ohms. Furthermore, utilizing the proposed 5-resistor rhombic gate resistor network, this EDA tool can calculate the equivalent resistance R from position A to position G. A-G It is approximately 300 ohms, and for a finFET, the resistance R from position B to position G is... B-G Approximately 100 ohms, or approximately 250 ohms for a nanosheet FET. Specifically, when two gate vias 812 and 811 located at different positions in the gate region 806 are simultaneously supplied with the same voltage signal, the equivalent resistance R is approximately 100 ohms based on the proposed 5-resistance diamond gate resistor network. A-G and R B-G This is reduced accordingly, thus accurately reflecting the actual equivalent gate resistance of the finFET or nanosheet FET.

[0070] Figures 8A to 8CThis is a layout diagram according to some embodiments of the present disclosure, showing a gate region extending across two transistor devices, on which gate vias are disposed at different locations.

[0071] According to some embodiments, Figures 8A to 8C The layouts 800A to 800C are similar, differing only in the positions of the gate vias B1 and B2 disposed on the gate region 806. (See reference...) Figure 8A Layout 800A includes two transistor devices T1 and T2 arranged in a cascaded structure, which can be a FinFET or a nanosheet FET. Transistor device T1 includes an active region 804 and a gate region 806, while transistor device T2 includes an active region 805 and the gate region 806, which extends from position A1 of transistor device T1 to position C2 of transistor device T2. For descriptive purposes, A1 and C1 represent the edge positions of the gate region 806 within transistor device T1, G1 represents the intermediate position between position A1 and position C1, and B1 represents the position of a first gate via 811 disposed on the gate region 806, for example, a position of 3 / 4 width of the gate region 806 within transistor device T1 starting from position A1. Similarly, A2 and C2 represent the edge positions of the gate region 806 within the transistor device T2, G2 represents the midpoint between positions A2 and C2, and B2 represents the position of the second gate via 812 disposed on the gate region 806, for example, at a position representing 3 / 4 of the width of the gate region 806 within the transistor device T2, starting from position A2. Furthermore, the distance from position A1 to position C1 is substantially equal to the distance from position A2 to position C2.

[0072] According to some embodiments, for the sake of simplicity, it is assumed that the gate region 806 has a... Figures 8A to 8C The approximately 2000-ohm fixed resistor from position A1 to position C2 indicates that the resistance from position A1 to position C1 and from position A2 to position C2 are both approximately 1000 ohms. (Reference) Figure 8A Geometrically, the equivalent resistance R from position B1 to position G1 B1-G1 It is approximately 250 ohms, and the equivalent resistance R from position B2 to position G2 is... B2-G2 It is also approximately 250 ohms. According to some embodiments, transistor devices T1 and T2 share the common gate region 806 and simultaneously supply the same voltage signal to the first gate via 811 located at position B1 and the second gate via 812 located at position B2 to turn on transistor devices T1 and T2. Therefore, using the proposed 5-resistor diamond gate resistor network, this EDA tool can calculate the equivalent resistance R. B1-G1 and R B2-G2 It is approximately 200 ohms.

[0073] refer to Figure 8B Positions B3 and G1 overlap, and position B4 and G2 overlap, indicating that the first gate via 811 of transistor device T1 is located at the middle position of the gate region 806 within transistor device T1, and the second gate via 812 of transistor device T2 is located at the middle position of the gate region 806 within transistor device T2. Geometrically, the equivalent resistance R from position B3 to position G1... B3-G1 It is approximately 0 ohms, and the equivalent resistance R from position B4 to position G2 is approximately 0 ohms. B4-G2 It is also approximately 0 ohms. According to some embodiments, transistor devices T1 and T2 share the common gate region 806, and simultaneously supply the same voltage signal to the first gate via at location B3 and the second gate via at location B4 to turn on transistor devices T1 and T2. Therefore, using the proposed 5-resistor diamond gate resistor network, this EDA tool can calculate the equivalent resistance R. B1-G1 and R B2-G2 It is approximately 100 ohms, which differs from the equivalent resistance estimated geometrically.

[0074] refer to Figure 8C A first gate via 811 is provided at position B1, and a second gate via 812 is absent. Geometrically, the equivalent resistance R from position B1 to position G1 is... B1-G1 It is approximately 250 ohms, and the equivalent resistance R from position B1 to position C2 is... B1-C2 It is also approximately 1250 ohms. According to some embodiments, transistor devices T1 and T2 share the common gate region 806, and a voltage signal is supplied to the first gate via located at position B1 to turn on transistor devices T1 and T2. Therefore, using the proposed 5-resistor diamond gate resistor network, this EDA tool can calculate the equivalent resistance R. B1-G1 and R A2-C2 They are approximately 200 ohms and 800 ohms respectively.

[0075] Therefore, it can be understood that the equivalent resistance may depend on the number and location of the gate vias disposed on the gate region, such as... Figures 8A to 8C As described in the embodiments.

[0076] Figures 9A to 9F This is a layout diagram illustrating various arrangements of gate vias according to different embodiments of the present disclosure. Figures 10A to 10F It corresponds to Figure 9A Figure 9F A cross-sectional view of the layout diagram in the image. Figure 10A Corresponding to Figure 9A The cross-section line is 10A-10A'. Figure 10B Corresponding to Figure 9BThe cross-section line is 10B-10B'. Figure 10C Corresponding to Figure 9C The cross-section line is 10C-10C'. Figure 10D Corresponding to Figure 9D The cross-section line is 10D-10D'. Figure 10E Corresponding to Figure 9E The cross-section line is 10E-10E'. Figure 10F Corresponding to Figure 9F The cross-section line is 10F-10F'.

[0077] According to some embodiments, Figures 9A to 9F The layout diagrams 900A to 900F shown correspond to Figures 10A to 10F The semiconductor structures shown are 1000A to 1000F. Layouts 900A to 900F can be similar, differing only in the number of gate vias disposed on the gate region 906. (Reference) Figure 9A Layout 900A includes an active region 904 and a gate region 906. The active region 904 is formed between isolation regions 920 and 922 (which may be shallow trench isolation (STI) regions). Edge EG1 exists between the active region 904 and the isolation region 920, while edge EG2 exists between the active region 904 and the isolation region 922. According to some embodiments, position A may be located on a first edge of the gate region 906 that overlaps with the isolation region 920, and position C may be located on a second edge of the gate region 906 that overlaps with the isolation region 922 and is opposite to the first edge. Gate vias 910 and 911 are located at positions Pm(G) and A, respectively. Position Pm(G) may refer to an intermediate position of the gate region 906 from position A to position C. Reference Figure 10A The semiconductor structure 1000A is similar to Figure 3A The semiconductor structure 300 is described herein, therefore its details will not be repeated here. From Figure 10A As can be seen from the semiconductor structure 1000A, the gate vias 910 and 911 are separated along the Y direction.

[0078] refer to Figure 9B Gate vias 910, 911, and 912 are located at positions Pm(G), A, and C, respectively. Furthermore, from... Figure 10B As can be seen from the semiconductor structure 1000B, the gate vias 910, 911 and 912 are separated along the Y direction.

[0079] refer to Figure 9C Gate vias 910 and 912 are located at positions P1 and C, respectively. Position P1 can refer to a position that is 1 / 4 the width of the gate region 906, located from position A. Furthermore, from... Figure 10CAs can be seen from the semiconductor structure 1000C, the gate vias 910 and 912 are separated along the Y direction.

[0080] refer to Figure 9D Gate vias 910 and 911 are located at positions P1 and A, respectively. Furthermore, from... Figure 10D As can be seen from the semiconductor structure 1000D, the gate vias 910 and 911 are separated along the Y direction.

[0081] refer to Figure 9E A gate via 910 is located at position P2. Position P2 can refer to a position that is 3 / 4 of the width away from position A from the gate region 906. Furthermore, from... Figure 10E As can be seen from the semiconductor structure 1000E, the gate via 910 is set at the corresponding position.

[0082] refer to Figure 9F Gate vias 910 and 911 are located at positions P2 and A, respectively. Furthermore, from... Figure 10F As can be seen from the semiconductor structure 1000F, the gate vias 910 and 911 are separated along the Y direction.

[0083] It should be noted that the different arrangements of the gate vias in layouts 900A to 900F have gate vias falling on top of the active region (e.g., VG on OD), and the proposed 5-resistance diamond gate resistor network can be used to calculate different equivalent resistances based on the positions of the gate vias in the layout, thereby satisfying the five process objectives of the five equations (as shown in equations (1) to (5)).

[0084] According to some embodiments, the EDA tool may have to consider layouts with a gate via falling on the active region and two different conditions, such as... Figure 9E As shown. Position P2 can refer to node B in the proposed 5-resistor rhombic gate resistor network. Condition 1 can indicate that the input voltage signal comes from one side (e.g., position B), and the equivalent resistance R is to be calculated. B-G Condition 2 can indicate that the input voltage signal comes from both sides (e.g., position A and position B), and the equivalent resistance R needs to be calculated. AB-G Conditions 1 and 2 may occur independently during the simulation. However, in some methods, fewer than five resistors are used in the network model, and the equivalent resistance R... B-G and R AB-G The resistors might be set to the same value, leading to significant differences compared to the process target. Utilizing the proposed 5-resistor diamond gate resistor network, this EDA tool can independently and accurately process the equivalent resistance R based on different analog signal conditions. B-G and R AB-GTherefore, the proposed 5-resistor rhombic gate resistor network can generate a gate resistor (Rg) topology that provides accurate effective resistance for all corresponding signal paths, thus better representing the physical results of Rg-sensitive designs.

[0085] Figures 11A to 11H The following are layout diagrams illustrating different arrangements of gate vias according to some embodiments of the present disclosure.

[0086] According to some embodiments, Figures 11A to 11H Layout diagrams 1100A to 1100H can refer to layouts 1 through 8, respectively. For simplicity, the active region AR, the gate region GR, and positions A, B, C, and G are labeled in layout diagrams 1100A to 1100H. (Reference) Figure 11A In layout 1, no gate via is provided on the gate region GR. (See reference...) Figures 11B to 11D Individual gate vias (CTs) are respectively located at positions A, B, and C in layouts 1100B to 1100D. (Reference) Figures 11E to 11G Two gate vias, CT1 and CT2, are located at different positions on the gate region GR. (Reference) Figure 11H The three gate vias CT1, CT2, and CT3 are located at positions A, G, and C, respectively. It should be noted that... Figure 11C , Figure 11E , Figure 11F and Figure 11H (These correspond to layouts 3, 5, 6, and 8, respectively) and have gate vias located on the active region AR.

[0087] According to some embodiments, reference Figure 11A , Figure 11B , Figure 11D and Figure 11G (These correspond to layouts 1, 2, 4, and 7, respectively). Since there is no contact with node B, the signal paths associated with node B are not considered.

[0088] According to some embodiments, reference Figure 11C (This corresponds to layout 3), where a voltage signal enters the device gate (e.g., node G) from the gate via CT. In these embodiments, when a voltage signal enters the device gate (e.g., node G) from the gate via CT, it indicates an effective resistance R. B-G It has relatively greater importance, and the voltage of other nodes is less than the voltage of the gate via at node B. Therefore, according to some embodiments, this EDA tool can process other effective resistors R with lower priority. A-G R C-G R AC-G R A-B and R B-C.

[0089] According to some embodiments, reference Figure 11E and Figure 11F (These correspond to layouts 5 and 6, respectively), the voltage signal enters the device gate from the two gate vias, and the EDA tool can respectively convert the effective resistance R AB-G and R BC-G These are the electrical conditions of interest for layouts 5 and 6. For example, the effective resistance R... B-G Equivalent to effective resistance R AB-G This is because node A and node B are at the same voltage potential. Furthermore, other signal paths R... A-G R C-G R AC-G and R BC-G (R AB-G This may have a limited impact on cell delay because the voltage at nodes A and C is less than the voltage at node B.

[0090] refer to Figure 11H (This corresponds to layout 8), the voltage signal enters the device gate from the three gate vias, and the EDA tool can take into account the effective resistance R. ABC-G As for the electrical conditions of interest. For example, the effective resistance R. B-G R AB-G and R BC-G Equivalent to effective resistance R ABC-G This is because nodes A through C are at the same voltage potential. Furthermore, other electrical conditions (R...) A-G R C-G and R AC-G The effect of the cell delay on the effective resistance R is much smaller than that on the effective resistance R. ABC-G This is because the voltages at nodes A to C are equal.

[0091] Therefore, according to some embodiments, among 10 electrical requirements depending on the gate via arrangement in 8 layout cases, the effective gate resistance with the most important relative impact on performance is selected, and the selected effective gate resistance is monitored during simulation.

[0092] Now attention is being redirected Figure 1 The operation of method 100 is described below. Method 100 includes operations 110 to 170.

[0093] In operation 110, a layout diagram of the IC device is received. This layout diagram includes a gate region having a width spanning an active region and a first gate via (e.g., for a “VG on OD” scenario) positioned along that width. The width extends from a first edge of the active region to a second edge opposite to the first edge. According to some embodiments, the width extends beyond the active region from location A to location C, where locations A and C are located at opposite edges of a gate region extending from a first isolation region through the active region to a second isolation region.

[0094] The first location is situated between the first and second edges of the active region. According to some embodiments, one or more additional gate vias (e.g., a second gate via and / or a third gate via) are disposed at opposite edge locations (e.g., location A, location C, or a combination thereof) of the gate region overlapping the first and second isolation regions.

[0095] Receiving the layout diagram includes using a computer's processor, such as processor 1202 of EDA system 1200, which will be discussed below. Figure 12 discuss.

[0096] In operation 120, a gate resistor network is constructed. This compact gate resistor network includes at least four nodes of a three-dimensional transistor architecture represented by the layout diagram, and at least five equivalent resistances between every two nodes. According to some embodiments, the four nodes include a gate node (e.g., G) and first to third non-gate nodes (e.g., B, A, and C). The gate node is located at a fin structure within the three-dimensional transistor architecture. The first non-gate node is located at a first location of the first gate via. The second non-gate node is located at a first edge of the gate region overlapping a first isolation region. The third non-gate node is located at a second edge of the gate region overlapping a second isolation region, wherein the second edge is opposite to the first edge.

[0097] In operation 130, the effective resistance of the gate region is calculated based on the equivalent resistance in the gate resistor compact network. This effective resistance is represented by the expected resistance of the gate structure manufactured according to the gate region. According to some embodiments, this expected resistance is the expected resistance Rg corresponding to the gate structure of the gate region G along width W1 between positions A and C, such as... Figures 2A to 5B As described in [the text].

[0098] In operation 140, according to some embodiments, the effective resistance is used to determine whether the layout conforms to design specifications. According to some embodiments, determining whether the layout conforms to the design specifications includes performing a simulation based on the layout.

[0099] In various embodiments, the design specifications include the speed of the IC, the noise performance of the IC, the transient response time of the IC, the cutoff frequency of the IC, or other circuit characteristics that may be affected by the gate resistance.

[0100] In operation 150, according to some embodiments, the layout is modified in response to determining that the layout does not conform to the design specification. In various embodiments, modifying the layout includes one or more of the following: changing the position of the first gate via along the first width, or adding a second gate via and / or a third gate via, which are respectively located at the first edge and the second edge of the gate region.

[0101] In operation 160, according to some embodiments, the layout diagram is stored in a storage device. In various embodiments, storing the layout diagram in the storage device includes storing the layout diagram in a non-volatile computer-readable storage medium or a cell library (e.g., a database), and / or includes storing the layout diagram via a network. According to some embodiments, storing the layout diagram in the storage device includes storing the layout diagram via network 1214 of the EDA system 1200, which will be discussed in conjunction with [the following text]. Figure 12 discuss.

[0102] In operation 170, according to some embodiments, one or more semiconductor masks and at least one component in a layer of a semiconductor IC are fabricated, or one or more fabrication operations are performed based on the layout. Fabricating one or more semiconductor masks and at least one component in a layer of a semiconductor IC, and performing one or more fabrication operations (e.g., one or more photolithographic exposures) based on the layout, will be described below in conjunction with... Figure 13 discuss.

[0103] By performing some or all of the operations of method 100, the effective gate resistance of the IC device is modeled using a 5-resistor diamond gate resistance compact network (which includes at least four nodes and five equivalent resistances in between) as part of generating the layout diagram of the IC device, thereby improving accuracy and avoiding incorrect estimation of gate resistance values ​​due to different electrical conditions, compared to gate resistance modeling methods that use fewer than five equivalent resistances for four nodes.

[0104] Figure 12 This is a block diagram of an IC device design system 1200 according to some embodiments of the present disclosure. According to some embodiments, the above description of... Figure 1 One or more operations of the method 100 discussed can be implemented using the IC device design system 1200.

[0105] According to some embodiments, the IC device design system 1200 is a computing device including a hardware processor 1202 and a non-transitory computer-readable storage medium 1204. The non-transitory computer-readable storage medium 1204, among other things, is encoded with (i.e., stores) computer program code 1206, i.e., a set of executable instructions. The hardware processor 1202 executes the instructions 1206 to represent (at least partially) implementing, for example, the above-described... Figure 1 The IC device design system of part or all of the method 100 discussed (hereinafter referred to as the process and / or method).

[0106] Processor 1202 is electrically coupled to non-transitory computer-readable storage medium 1204 via bus 1208. Processor 1202 is also electrically coupled to I / O interface 1210 via bus 1208. Network interface 1212 is also electrically connected to processor 1202 via bus 1208. Network interface 1212 is connected to network 1214, enabling processor 1202 and non-transitory computer-readable storage medium 1204 to be connected to external components via network 1214. Processor 1202 is configured to execute computer program code 1206 encoded in non-transitory computer-readable storage medium 1204 to make IC device design system 1200 available for performing part or all of the processes and / or methods. In one or more embodiments, processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0107] In one or more embodiments, the non-transitory computer-readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the non-transitory computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the non-transitory computer-readable storage medium 1204 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video disc (DVD).

[0108] In one or more embodiments, the non-transitory computer-readable storage medium 1204 stores computer program code 1206 configured to enable the IC device design system 1200 to perform part or all of the processes and / or methods. In one or more embodiments, the non-transitory computer-readable storage medium 1204 also stores information facilitating the performance of part or all of the processes and / or methods. In various embodiments, the non-transitory computer-readable storage medium 1204 stores at least one of at least one layout drawing 1220 or at least one design specification 1222 or a combination thereof, each relating to method 100 and Figures 1 to 1 1. This has been discussed.

[0109] IC device design system 1200 includes I / O interface 1210. I / O interface 1210 is coupled to external circuitry. In various embodiments, I / O interface 1210 includes one or a combination of a keyboard, keypad, mouse, trackball, touchpad, display, touchscreen, and / or cursor arrow keys for communicating information and commands with processor 1202.

[0110] The IC device design system 1200 also includes a network interface 1212 coupled to a processor 1202. The network interface 1212 allows the system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. The network interface 1212 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 1200.

[0111] The IC device design system 1200 is configured to receive information via I / O interface 1210. The information received via I / O interface 1210 includes at least one design rule instruction, at least one set of standards, at least one design rule, at least one DRM and / or other parameters, or a combination thereof, for processing by processor 1202. This information is transmitted to processor 1202 via bus 1208. The IC device design system 1200 is configured to transmit and / or receive user interface-related information via I / O interface 1210.

[0112] According to some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. According to some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of an additional software application. According to some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. According to some embodiments, at least one process and / or method is implemented as a software application that is part of an EDA tool. According to some embodiments, tools (e.g., from CADENCE DESIGN SYSTEMS, Inc.) are used... Use other suitable layout generation tools to generate layout diagrams.

[0113] According to some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, etc.

[0114] Through one or more operations that can be used to implement method 100 (as mentioned above) Figures 1 to 1 As discussed in 1), the IC device design system 1200 and the non-transitory computer-readable recording medium (e.g., non-transitory computer-readable recording medium 1204) achieve the advantages discussed above regarding method 100.

[0115] Figure 13 This is a block diagram of an IC manufacturing system 1300 and its associated IC manufacturing process according to some embodiments of the present disclosure. According to some embodiments, based on the layout diagram, the manufacturing system 1300 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0116] exist Figure 13In this IC manufacturing system 1300, entities such as design room 1320, mask room 1330, and IC manufacturer / fab (“fab”) 1350 interact with each other in design and development, as well as manufacturing cycles and / or services related to the manufacture of IC devices 1360. The entities in system 1300 are connected via a communication network. According to some embodiments, this communication network is a single network. According to some embodiments, this communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. According to some embodiments, two or more of design room 1320, mask room 1330, and IC fabrication plant 1350 are owned by a single, larger company. According to some embodiments, two or more of design room 1320, mask room 1330, and IC fabrication plant 1350 coexist in a common facility and use common resources.

[0117] Design studio (or design team) 1320 generates design layout diagram 1322 based on method 100, which is mentioned above regarding... Figures 1 to 1 As described in the discussion of 1. Design layout 1322 includes various geometric patterns corresponding to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1360 to be manufactured. Various layers are combined to form various IC components. For example, a portion of design layout 1322 includes various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which are to be formed on a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design room 1320 implements appropriate design processes, including method 100, which is described above in relation to Figures 1 to 1 As described in section 1, a design layout diagram 1322 is formed. This design process includes one or more of logical design, physical design, or placement and routing. The design layout diagram 1322 is presented in one or more data files containing information about the geometric pattern. For example, the design layout diagram 1322 may be expressed in GDSII or DFII file format.

[0118] Mask chamber 1330 includes data preparation 1332 and mask fabrication 1344. Mask chamber 1330 fabricates one or more masks 1345 using a design layout 1322, which will be used to fabricate layers of IC device 1360 according to the design layout 1322. Mask chamber 1330 performs mask data preparation 1332, in which the design layout 1322 is converted into a representative data file (“RDF”). Mask data preparation 1332 provides the RDF to mask fabrication 1344. Mask fabrication 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1345 or a semiconductor wafer 1353. The design layout 1322 is processed by mask data preparation 1332 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 1350. Figure 13 In this illustration, mask data preparation 1332 and mask manufacturing 1344 are shown as separate elements. According to some embodiments, mask data preparation 1332 and mask manufacturing 1344 may be collectively referred to as mask data preparation.

[0119] According to some embodiments, mask data preparation 1332 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjustment design layout diagram 1322. According to some embodiments, mask data preparation 1332 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. According to some embodiments, inverse lithography (ILT) is also employed, which treats OPC as an inverse imaging problem.

[0120] According to some embodiments, mask data preparation 1332 includes a mask rule checker (MRC) that checks the design layout 1322 processed by OPC using a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin and take into account variability in semiconductor manufacturing processes, etc. According to some embodiments, the MRC modifies the design layout 1322 to compensate for limitations during mask fabrication 1344, which may undo some modifications performed by OPC to meet the mask creation rules.

[0121] According to some embodiments, mask data preparation 1332 includes a lithography process check (LPC), which simulates the process to be implemented by IC manufacturing plant 1350 to manufacture IC device 1360. The LPC simulates this process based on design layout 1322 to create a simulated manufactured device, such as IC device 1360. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. According to some embodiments, after the LPC creates the simulated manufactured device, if the simulated device is not close enough in shape to meet design rules, optical proximity correction (OPC) and / or mask rule checker (MRC) are repeated to further refine the design layout 1322.

[0122] It should be understood that the above description of mask data preparation 1332 has been simplified for clarity. According to some embodiments, data preparation 1332 includes additional components, such as logic operations (LOPs), to modify the design layout 1322 according to manufacturing rules. Furthermore, the processes applied to the design layout 1322 during data preparation 1332 can be performed in various different sequences.

[0123] Following mask data preparation 1332 and during mask fabrication 1344, a mask 1345 or a set of masks 1345 is fabricated based on a modified design layout 1322. According to some embodiments, mask fabrication 1344 includes performing one or more photolithographic exposures based on the design layout 1322. According to some embodiments, a pattern is formed on the mask (photomask or intermediate mask) 1345 using an electron beam (e-beam) or multi-electron beam mechanism based on the modified design layout 1322. The mask 1345 can be formed using various techniques. According to some embodiments, the mask 1345 is formed using a binary technique. According to some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque regions and passes through the transparent regions. In one example, a binary mask version of mask 1345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1345 is formed using a phase-shifting technique. In the phase-shifting mask (PSM) version of mask 1345, various components in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1344 is used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1353, etching processes to form various etched regions in semiconductor wafer 1353, and / or other suitable processes.

[0124] IC manufacturing plant 1350 includes manufacturing tools 1352. IC manufacturing plant 1350 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. According to some embodiments, IC manufacturing plant 1350 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end manufacturing of production lines (FEOL)) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end manufacturing of production lines (BEOL)) for the interconnection and packaging of IC products, and a third manufacturing facility may provide other services for foundry operations.

[0125] IC fabrication plant 1350 uses a mask 1345, fabricated by mask chamber 1330, to fabricate IC device 1360. Therefore, IC fabrication plant 1350 uses design layout 1322 at least indirectly to fabricate IC device 1360. According to some embodiments, semiconductor wafer 1353 is fabricated by IC fabrication plant 1350 using mask 1345 to form IC device 1360. According to some embodiments, IC fabrication includes performing one or more photolithography exposures, which are at least indirectly based on design layout 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1353 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0126] One aspect of this disclosure provides a method for generating an integrated circuit (IC) layout of an IC device. The method includes receiving a layout of the IC device, the layout including a gate region having a first width spanning an active region and a first gate via located at a first position along the first width. A gate resistor compact network is constructed, the network including at least four nodes of a three-dimensional transistor architecture represented by the layout and at least five equivalent resistances between corresponding nodes of the at least four nodes. The effective resistance of the gate region is calculated using the equivalent resistances in the gate resistor compact network, and the effective resistances are used to determine whether the layout conforms to design specifications.

[0127] Another aspect of this disclosure provides an integrated circuit (IC) layout generation system, the system including a processor and a non-transitory computer-readable storage medium containing computer program code of one or more programs. The non-transitory computer-readable storage medium and the computer program code are configured, together with the processor, to cause the system to: receive a layout including a gate region having a first width sequentially spanning a first isolation region, an active region, and a second isolation region; a first gate via located at a first position along a second width spanning the active region; and a second gate via located at a first edge of the gate region; construct a gate resistor compact network including at least four nodes of a three-dimensional transistor architecture represented by the layout and at least five equivalent resistances between corresponding nodes of the at least four nodes; calculate an effective resistance of the gate region using the equivalent resistances in the gate resistor compact network; and perform circuit simulation based on the effective resistances.

[0128] Another aspect of this disclosure provides a method for generating an integrated circuit (IC) layout of an IC device, the method comprising receiving a layout of the IC device. The layout includes a gate region having a first width spanning an active region and a first gate via located at a first position along the first width. At least four nodes of the layout and the gate structure of the IC device are obtained; the gate region is modeled using a gate resistor network, which is equivalent to a compact network including the at least four nodes of the layout and at least five corresponding equivalent resistances between every two nodes of the at least four nodes; and the compact network is used to determine whether the layout conforms to design specifications.

[0129] According to some embodiments, a method of manufacturing an integrated circuit (IC) device includes: receiving a layout of the integrated circuit (IC) device, the layout including: a gate region having a first width spanning an active region, and a first gate via located at a first position along the first width; and constructing a gate resistor compact network including at least four nodes of a three-dimensional transistor architecture represented by the layout and at least five equivalent resistances between corresponding nodes of the at least four nodes; determining an effective resistance of the gate region based on the equivalent resistances in the gate resistor compact network; determining whether the effective resistance conforms to design specifications; and modifying the layout to facilitate compliance if the effective resistance does not conform.

[0130] According to some embodiments, the gate region extends from the first isolation region through the active region to the second isolation region; and the gate region has a second width spanning the first isolation region, the active region, and the second isolation region.

[0131] According to some embodiments, the at least four nodes include: a gate node located at the gate structure of the three-dimensional transistor architecture; a first non-gate node located at the first location of the first gate via; a second non-gate node located at the first edge of the gate region, the first edge overlapping the first isolation region; and a third non-gate node located at the second edge of the gate region, the second edge overlapping the second isolation region, the second edge being opposite to the first edge.

[0132] According to some embodiments, constructing a gate resistor compact network includes: simplifying the precursor of the gate resistor compact network using a Δ-Y transformation to obtain the gate resistor compact network.

[0133] According to some embodiments, the gate resistor compact network is equivalent to a half-side structure with two non-overlapping triangular meshes sharing a common edge; and the common edge represents the equivalent resistance between the first non-gate node and the gate node.

[0134] According to some embodiments, the layout includes a second gate via located at a first edge or a second edge of the gate region.

[0135] According to some embodiments, the layout includes a second gate via and a third gate via, which are located at a first edge and a second edge of the gate region, respectively.

[0136] According to some embodiments, the method further includes, based on the layout, at least one of the following steps: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor devices; or (C) fabricating at least one component in a layer of a semiconductor integrated circuit.

[0137] According to some embodiments, determining whether the specification is compliant includes performing a simulation based on the layout diagram.

[0138] According to some embodiments, the design specification includes the speed of the IC device.

[0139] According to some embodiments, the modification of the layout includes: changing the first position of the first gate; and one or more steps: (i) adding a second gate via at a second position along the first width or at the first edge of the gate region, or (ii) adding a third gate via at the second edge of the gate region.

[0140] According to some embodiments, a system for manufacturing an integrated circuit (IC) device includes a processor and a non-transitory computer-readable storage medium containing computer program code of one or more programs. The non-transitory computer-readable storage medium, the computer program code, and the processor are configured to cause the system to perform at least the following operations: receiving a layout of the IC device, the layout including: a gate region having a first width spanning a first isolation region, an active region, and a second isolation region; a first gate via located at a first position along a second width spanning the active region; and a second gate via located at a first edge of the gate region; constructing a gate resistor compact network including at least four nodes of a three-dimensional transistor architecture represented by the layout and at least five equivalent resistances between corresponding nodes of the at least four nodes; determining an effective resistance of the gate region based on the equivalent resistances in the gate resistor compact network; and performing circuit simulation based on the effective resistances.

[0141] According to some embodiments, the at least four nodes include: a gate node located at the gate structure of the three-dimensional transistor architecture; a first non-gate node located at the first location of the first gate via; a second non-gate node located at the first edge of the gate region, the first edge overlapping the first isolation region; and a third non-gate node located at the second edge of the gate region, the second edge overlapping the second isolation region, the second edge being opposite to the first edge.

[0142] According to some embodiments, the computer-readable storage medium, computer program code, and processor are further configured to cause the system to perform at least the following operations: simplifying the precursor of the gate resistor network using a Δ-Y transformation to obtain the gate resistor compact network.

[0143] According to some embodiments, the execution circuit simulation includes: applying a first input voltage signal to the first gate via to estimate a first effective resistance of the gate region; and applying the first input voltage signal to the first gate via and the second gate via to estimate a second effective resistance of the gate region; and the computer-readable storage medium, computer program code, and processor are further configured to cause the system to perform at least the following operation: determining whether each of the first effective resistance and the second effective resistance conforms to design specifications.

[0144] According to some embodiments, the layout also includes a third gate via located at a second edge of the gate region, and the second edge being opposite to the first edge.

[0145] According to some embodiments, the execution circuit simulation includes applying an input voltage signal to the first gate via, the second gate via, and the third gate via.

[0146] According to some embodiments, the system further includes at least one of the following facilities: a mask facility configured to manufacture one or more semiconductor masks based on the layout; or a manufacturing facility configured to manufacture at least one component in a layer of a semiconductor integrated circuit based on the layout.

[0147] According to some embodiments, a non-transitory computer-readable medium stores computer-executable instructions representing a method for generating an integrated circuit (IC) layout diagram of an IC device. The computer-executable instructions are executable by at least one processor to perform the method, which includes: receiving a layout diagram of the IC device, the layout diagram including: a gate region having a first width spanning an active region, and a first gate via located at a first position along the first width; selecting at least four nodes and a gate structure of the IC device; modeling the gate region using a gate resistance compact network, the gate resistance compact network including the at least four nodes and at least five equivalent resistances corresponding to each pair of the at least four nodes; and determining whether the layout diagram conforms to design specifications based on the gate resistance compact network.

[0148] According to some embodiments, the gate region extends from the first isolation region through the active region to the second isolation region; and the gate region has a second width spanning the first isolation region, the active region, and the second isolation region.

[0149] The methods and components of this disclosure have been fully described in the provided examples and descriptions. It should be understood that any modifications or variations that do not depart from the spirit of this disclosure are intended to be covered within the scope of this disclosure.

[0150] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. As will be readily understood by those skilled in the art from this disclosure, processes, machines, manufactures, material compositions, means, methods, or steps that exist now or will be developed in the future and perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized under this disclosure.

[0151] Therefore, the appended claims are intended to encompass processes, machines, manufactures, material compositions, means, methods, or steps within their scope. Furthermore, each claim constitutes a separate embodiment, and combinations of various claims and embodiments are within the scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit (IC) device, the method comprising: A layout diagram of a receiving integrated circuit (IC) device, the layout diagram including: A gate region having a first width spanning the active region and a first gate via located at a first position along the first width; Construct a gate resistor compact network, the gate resistor compact network comprising at least four nodes of a three-dimensional transistor architecture represented by the layout diagram and at least five equivalent resistances between corresponding nodes of the at least four nodes; The effective resistance of the gate region is determined based on the equivalent resistance in the gate resistor compact network. Determine whether the effective resistance meets the design specifications; and When the effective resistance is not compliant The layout diagram has been modified to facilitate compliance.

2. The method according to claim 1, wherein: The gate region extends from the first isolation region through the active region to the second isolation region; and The gate region has a second width spanning the first isolation region, the active region, and the second isolation region.

3. The method according to claim 2, wherein, The at least four nodes include: The gate node is located at the gate structure of the three-dimensional transistor architecture; The first non-gate node is located at the first position of the first gate via; The second non-gate node is located at the first edge of the gate region overlapping with the first isolation region; and The third non-gate node is located at the second edge of the gate region that overlaps with the second isolation region, the second edge being opposite to the first edge.

4. The method according to claim 3, wherein, Constructing the compact network of the gate resistor includes: The gate resistor compact network is obtained by simplifying the precursor of the gate resistor compact network using a Δ-Y transformation.

5. The method according to claim 3, wherein: The compact gate resistor network is equivalent to a half-edge structure of two non-overlapping triangular meshes sharing a common edge; and The common edge represents the equivalent resistance between the first non-gate node and the gate node.

6. A system for manufacturing an integrated circuit (IC) device, the system comprising a processor and a non-transitory computer-readable storage medium containing computer program code for one or more programs, the non-transitory computer-readable storage medium, the computer program code, and the processor being configured to cause the system to perform at least the following operations: A layout diagram of a receiving IC device, the layout diagram including... the following: The gate region has a first width spanning the first isolation region, the active region, and the second isolation region. The first gate via is located at a first position along a second width spanning the active region, and The second gate via is located at the first edge of the gate region; Construct a compact network of gate resistors, comprising at least four nodes of a three-dimensional transistor architecture represented by the layout diagram and at least five equivalent resistances between corresponding nodes of the at least four nodes; The effective resistance of the gate region is determined based on the equivalent resistance in the gate resistor compact network. as well as Circuit simulation is performed based on the effective resistance.

7. The system according to claim 6, wherein, The at least four nodes include: The gate node is located at the gate structure of the three-dimensional transistor architecture; The first non-gate node is located at the first position of the first gate via; The second non-gate node is located at the first edge of the gate region that overlaps with the first isolation region; and The third non-gate node is located at the second edge of the gate region that overlaps with the second isolation region, the second edge being opposite to the first edge.

8. The system according to claim 7, wherein, The computer-readable storage medium, the computer program code, and the processor are further configured to cause the system to perform at least the following operations: The precursor is considered as the gate resistor network. The precursor is simplified using a Δ-Y transformation to obtain the compact network of the gate resistor.

9. A non-transitory computer-readable medium storing computer-executable instructions thereon representing a method for generating an IC layout diagram of an integrated circuit (IC) device, the computer-executable instructions being executable by at least one processor to perform the method, the method comprising: Receive the layout diagram of the IC device, the layout diagram including: The gate region has a first width spanning the active region, and A first gate via is located at a first position along the first width; Select at least four nodes and gate structure of the IC device; The gate region is modeled using a gate resistor compact network, the gate resistor compact network including the at least four nodes and corresponding at least five equivalent resistances located between each pair of nodes in the at least four nodes; and The layout pattern is determined based on the compact network of the gate resistors to determine whether it conforms to design specifications.

10. The non-transitory computer-readable medium according to claim 9, wherein: The gate region extends from the first isolation region through the active region to the second isolation region; and The gate region has a second width spanning the first isolation region, the active region, and the second isolation region.

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