Anti-radiation photosensitive transistor and electronic equipment

Abstract

The invention discloses an anti-radiation photosensitive transistor and electronic equipment, and relates to the technical field of transistors, the anti-radiation photosensitive transistor comprises a substrate, a channel layer, a gate dielectric layer, an electrode structure and a two-dimensional semiconductor material layer; the channel layer is located on the substrate, is made of a high-forbidden-bandwidth semiconductor material and comprises a non-photosensitive functional region and a solar-blind photosensitive region, and the non-photosensitive functional region and the solar-blind photosensitive region form an RESURF structure through in-situ doping gradient transition; the gate dielectric layer is located between the gate and the solar-blind photosensitive region and is made of a high-dielectric-constant material; the two-dimensional semiconductor material layer is located between the source electrode and the solar-blind photosensitive region, and the two-dimensional semiconductor material layer and the material of the solar-blind photosensitive region form a Van der Waals heterojunction. The integrated structure synergistically improves the extreme environment radiation resistance, solar blind photosensitive sensitivity and single particle burning resistance reliability of the device, enhances the total ionizing dose resistance, uniformizes electric field distribution, relieves interface stress, optimizes carrier transport, inhibits trapped charge accumulation and local thermal runaway, and gives consideration to high photosensitive response and high breakdown voltage. And the method adapts to extreme high-voltage scenes.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and in particular to a radiation-resistant photosensitive transistor and electronic device. Background Technology

[0002] Traditional phototransistors typically employ a composite gate dielectric structure of alumina and silicon oxide. This type of gate dielectric has a relatively low dielectric constant, resulting in insufficient gate control capability. Furthermore, it is prone to generating high-density trapped charges under ionizing radiation, causing significant threshold voltage drift and severely impacting device switching stability and photosensitivity reliability. Simultaneously, traditional phototransistors generally employ a uniform channel design, presenting an irreconcilable technical contradiction in synergistically optimizing photosensitivity and radiation resistance. Improving radiation resistance through high doping significantly reduces its solar-blind ultraviolet responsivity; conversely, using low doping to ensure photosensitivity greatly increases the risk of single-particle burn-in, leading to a surge in leakage current. Summary of the Invention

[0003] The purpose of this invention is to provide a radiation-resistant photosensitive transistor and electronic device that can effectively suppress the accumulation of trap charge in the gate dielectric and the off-state leakage current, thus resolving the technical contradiction that traditional devices cannot simultaneously achieve both photosensitive performance and radiation resistance.

[0004] To address the aforementioned technical problems, the present invention provides a radiation-resistant photosensitive transistor, comprising: a substrate; a channel layer located on the substrate; the channel layer including a non-photosensitive functional region near the substrate and a solar-blind photosensitive region located on the side of the non-photosensitive functional region away from the substrate; the channel layer being a semiconductor material with a bandgap greater than a set bandgap threshold; the non-photosensitive functional region and the solar-blind photosensitive region forming a RESURF structure through an in-situ doping gradient transition; a gate dielectric layer and an electrode structure located on the channel layer; the gate dielectric layer being located between the gate electrode of the electrode structure and the solar-blind photosensitive region; the gate dielectric layer being a material with a dielectric constant greater than a preset dielectric constant threshold; a two-dimensional semiconductor material layer being located between the source electrode of the electrode structure and the solar-blind photosensitive region; the two-dimensional semiconductor material layer and the material of the solar-blind photosensitive region forming a van der Waals heterojunction.

[0005] To address the aforementioned technical problems, the present invention also provides an electronic device, comprising: the aforementioned radiation-resistant phototransistor, and a logic controller connected to the radiation-resistant phototransistor; a solar blindness photodetector for monitoring photocurrent and a radiation dose monitoring component for monitoring total ionizing dose and single-particle burn-off risk value are disposed on the radiation-resistant phototransistor; the logic controller is configured to perform photoelectric coordinated regulation of the radiation-resistant phototransistor based on photocurrent, total ionizing dose and single-particle burn-off risk value data; and is also configured to perform in-situ damage recovery of the radiation-resistant phototransistor based on photocurrent and single-particle burn-off risk value data.

[0006] The beneficial effects of this invention are that the radiation-resistant phototransistor provided by this invention, through the integrated structural design of partitioned channel, high dielectric constant gate dielectric layer and van der Waals heterojunction, achieves a synergistic improvement in radiation resistance, solar-blind photosensitivity and single-particle burn-off reliability under extreme environments, effectively extending the device's lifespan. Specifically, the lattice stability of the wide-bandgap semiconductor material and the low trap charge density of the gate dielectric layer significantly enhance the resistance to total ionizing dose; the in-situ doped gradient transition structure between the non-photosensitive functional region and the solar-blind photosensitive region enables a uniform electric field distribution, resolving the technical contradiction that traditional single-channel transistors cannot simultaneously achieve high photosensitivity and high breakdown voltage; the van der Waals heterojunction formed by the two-dimensional semiconductor material layer and the photosensitive region not only alleviates interface stress and optimizes carrier transport efficiency, but also avoids the problem of excessive interface defects caused by lattice mismatch in traditional covalent heterojunctions, reducing defect-mediated carrier recombination, while isolating substrate influence and reducing interface thermal boundary resistance. The above structural design can suppress the accumulation of gate dielectric trap charge caused by total dose effect under radiation environment and local thermal runaway caused by single-event burn-out from the source. While improving the photosensitive responsivity in the solar blind, it can effectively suppress the off-state leakage current and the risk of single-event burn-out, ensure that the device has excellent selectivity in the solar blind band, avoid solar background light interference, and fully adapt to the high voltage application requirements in extreme environments.

[0007] In addition, the present invention also provides a corresponding electronic device for radiation-resistant photosensitive transistors, which has the same or corresponding technical features as the radiation-resistant photosensitive transistors mentioned above, and has the same effect. Attached Figure Description

[0008] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is one of the structural schematic diagrams of the radiation-resistant photosensitive transistor provided in an embodiment of the present invention; Figure 2 This is a second schematic diagram of the structure of the radiation-resistant photosensitive transistor provided in an embodiment of the present invention; Figure 3 A schematic diagram of the architecture corresponding to the main branch and backup branch provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0011] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] An embodiment of the present invention provides a radiation-resistant photosensitive transistor. Figure 1 This is one of the structural schematic diagrams of the radiation-resistant photosensitive transistor provided in an embodiment of the present invention, such as... Figure 1 As shown, the radiation-resistant photosensitive transistor includes: Substrate 1; A channel layer is located on substrate 1. The channel layer includes a non-photosensitive functional region 2 close to substrate 1 and a solar-blind photosensitive region 3 located on the side of the non-photosensitive functional region 2 away from substrate 1. The material of the channel layer is a semiconductor material with a band gap greater than a set band gap threshold. The non-photosensitive functional region 2 and the solar-blind photosensitive region 3 form a RESURF (Reduced Surface Field) structure through in-situ doping gradient transition. The gate dielectric layer 4 and the electrode structure are located on the channel layer; the gate dielectric layer 4 is located between the gate of the electrode structure and the solar-blind photosensitive region 3; the material of the gate dielectric layer is a material with a dielectric constant greater than a preset dielectric constant threshold; the electrode structure includes a gate 5, a source 6 and a drain 7. A two-dimensional semiconductor material layer 8 is located between the source electrode 6 and the solar-blind photosensitive region 3 of the electrode structure; the materials of the two-dimensional semiconductor material layer 8 and the solar-blind photosensitive region 3 form a van der Waals heterojunction.

[0014] In the radiation-resistant phototransistor provided in this embodiment of the invention, the integrated structure design of partitioned channel, high dielectric constant gate dielectric layer and van der Waals heterojunction achieves a synergistic improvement in radiation resistance, solar-blind photosensitivity and single-event burnout (SEB) reliability under extreme environments, effectively extending the device's lifespan. Specifically, the lattice stability of the wide bandgap semiconductor material and the low trap charge density of the gate dielectric layer 4 significantly enhance resistance to total ionizing dose (TID). The in-situ doped gradient transition structure between the non-photosensitive functional region 2 and the solar-blind photosensitive region 3 enables a uniform electric field distribution, resolving the technical contradiction of traditional single-channel transistors in achieving both high photosensitivity and high breakdown voltage. The van der Waals heterojunction formed by the two-dimensional semiconductor material layer 8 and the solar-blind photosensitive region 3 alleviates interface stress, optimizes carrier transport efficiency, avoids the problem of excessive interface defects caused by lattice mismatch in traditional covalent heterojunctions, reduces defect-mediated carrier recombination, and simultaneously isolates the substrate influence and reduces the interface thermal boundary resistance. The above structural design can suppress the accumulation of gate dielectric trap charge caused by total dose effect under radiation environment and local thermal runaway caused by single-event burn-out from the source. While improving the photosensitive responsivity in the solar blind, it can effectively suppress the off-state leakage current and the risk of single-event burn-out, ensure that the device has excellent selectivity in the solar blind band, avoid solar background light interference, and fully adapt to the high voltage application requirements in extreme environments.

[0015] It should be noted that the set bandgap threshold for the channel layer material can be determined comprehensively based on the response requirements of the solar-blind photosensitive band and the characteristics of radiation-resistant application scenarios. From the perspective of solar-blind photosensitive function, the set bandgap threshold can be higher than the photon energy corresponding to the solar-blind ultraviolet band, ensuring that the device only responds to photons in the target band, while effectively suppressing visible light and other non-target bands. From the perspective of radiation resistance, the set bandgap threshold can meet the lattice stability requirements of the material under ionizing radiation and high-energy particle bombardment, avoiding the generation of a large number of lattice defects due to radiation-induced defects. That is, a wide bandgap semiconductor channel material is used for the channel layer. In terms of specific numerical selection, the set bandgap threshold can be no less than 4.4 eV, covering the application requirements of wide bandgap semiconductor materials in the fields of solar-blind detection and radiation resistance, ensuring that the device has both excellent photosensitive selectivity and radiation resistance reliability. Preferably, the material of the channel layer can be β-phase gallium oxide (GaN). Its own bandgap is approximately 4.8 eV to 4.9 eV, which meets the threshold requirement.

[0016] The preset dielectric constant threshold of the gate dielectric layer 4 material can be determined by comprehensively considering the device's gate control performance requirements, radiation resistance reliability requirements, and interface compatibility with the channel layer. From the perspective of gate control capability, the preset dielectric constant threshold can be significantly higher than that of traditional silicon-based gate dielectric materials to increase the gate capacitance value with the same dielectric layer thickness, enhance the gate voltage's regulation efficiency of channel carriers, and avoid tunneling leakage caused by an excessively thin dielectric layer. From the perspective of radiation resistance, the preset dielectric constant threshold can match the inherent characteristics of high dielectric constant materials, namely, high dielectric constant is often accompanied by strong chemical bond energy and low defect density, which can suppress the accumulation of trapped charges induced by total ionization dose. In other words, the gate dielectric layer 4 uses a high dielectric constant material. In terms of specific numerical selection, considering the application scenarios of wide bandgap semiconductor devices, this preset dielectric constant threshold can be no less than 10, which distinguishes it from traditional low dielectric constant media such as silicon dioxide (dielectric constant of about 3.9), while also covering the selection range of high-performance gate dielectric materials, ensuring that the device has both excellent gate control accuracy and radiation resistance stability. Preferably, the material of the gate dielectric layer 4 can be tantalum pentoxide (…). Its dielectric constant is approximately 20 to 25, which meets the threshold requirement. Gate dielectric layer 4 is applied to When used as a radiation-resistant phototransistor with a channel layer, the gate control capability can be significantly improved with the same dielectric layer thickness, enhancing the gate 5's efficiency in controlling channel carriers; simultaneously... Its high chemical bond energy and low defect density characteristics can effectively suppress the accumulation of trap charges induced by total ionizing dose irradiation, ensuring the switching stability and photosensitive reliability of the device under extreme radiation environments.

[0017] Furthermore, in a specific implementation, in the radiation-resistant photosensitive transistor provided in the embodiments of the present invention, the solar-blind photosensitive region 3 can be obtained by molecular beam epitaxy, and its thickness range can be set to 300 nm to 800 nm; the solar-blind photosensitive region 3 can be n-type doped, and the doping concentration range can be set to to .

[0018] The non-photosensitive functional region 2 can be grown using a metal-organic chemical vapor deposition process, and its thickness can be set to 1.0 μm to 2.0 μm; the non-photosensitive functional region 2 can be n-type doped, and the doping concentration can be set to... to .

[0019] In implementation, The total thickness of the channel layer can be set to 2μm. A partitioned structure design is adopted, dividing it into a solar-blind photosensitive area 3 and a non-photosensitive functional area 2, to achieve decoupling optimization of function and performance. The specific parameters and processes are as follows:

[0020] The thickness of the solar-blind photosensitive region 3 can range from 300 nm to 800 nm, preferably 500 nm; it is grown using molecular beam epitaxy (MBE) with Sn as the highly efficient n-type dopant; the doping concentration can range from... to Preferred The low doping concentration improves the photogenerated carrier capture efficiency. The absorption coefficient of the material in this region for the 254nm solar-blind wavelength can be... It matches the characteristics of the solar ultraviolet blind zone; the carrier lifetime can reach 20ms, which can effectively extend the survival time of photogenerated carriers and improve the photosensitivity of the device.

[0021] The thickness of the non-photosensitive functional region 2 can range from 1.0 μm to 2.0 μm, preferably 1.5 μm; it is grown using a metal-organic chemical vapor deposition (MOCVD) process, with Si as the highly efficient n-type dopant; the doping concentration can range from... to Preferred The high doping concentration improves carrier transport efficiency; the carrier lifetime can be 1ns, which is suitable for the fast switching requirements of high power switches.

[0022] The solar-blind photosensitive area 3 and the non-photosensitive functional area 2 adopt an in-situ doping gradient transition, with the doping concentration starting from the preferred value. Gradient to This creates a concentration gradient of 1.5 to 2.5 times; this method reduces the interfacial carrier scattering rate by 30%, constructs a RESURF structure, achieves a uniform electric field distribution, and increases the device breakdown voltage from 5kV to 10kV.

[0023] Furthermore, in a specific implementation, in the radiation-resistant photosensitive transistor provided in the embodiments of the present invention, the source electrode 6 of the electrode structure can form a Schottky contact with the solar-blind photosensitive region 3 through the two-dimensional semiconductor material layer 8; the drain electrode 7 of the electrode structure can form an ohmic contact with the solar-blind photosensitive region 3.

[0024] In implementation, source electrode 6 forms a Schottky contact with the solar-blind photosensitive region 3 through the graphene layer, leveraging the high carrier mobility of graphene and... The wide bandgap characteristics work synergistically to construct a stable Schottky barrier, enabling precise control of the device's off-state leakage current. Furthermore, it can effectively reduce the phenomenon of carrier trapping caused by irradiation-induced interface defects. The drain 7 and the channel layer are formed into an ohmic contact using a metallization scheme, with a contact resistivity less than or equal to... This low contact resistivity design, in conjunction with the Si doping gradient structure of the non-photosensitive functional region 2, can significantly reduce the current concentration effect under single-particle pulse, thereby increasing the single-particle burn-off voltage of the device to over 220V, while ensuring the efficient transport of solar-blind photogenerated carriers.

[0025] Furthermore, in a specific implementation, in the radiation-resistant photosensitive transistor provided in the embodiments of the present invention, the gate dielectric layer 4 can be prepared by an atomic layer deposition process, using tantalum pentaethoxy and deionized water as precursors; the total thickness of the gate dielectric layer 4 can be controlled by setting the deposition thickness per cycle and accumulating the corresponding deposition cycle number.

[0026] In practice, this invention can be adopted Gate dielectric layer 4 replaces the traditional The composite gate dielectric, prepared by atomic layer deposition (ALD), effectively overcomes the bottlenecks of traditional gate dielectrics in terms of dielectric properties and total ionization dose resistance. The specific preparation process and performance advantages are as follows: The precursor can be tantalum pentaethoxy and deionized water. The deposition temperature can be set to 300℃. A cyclic deposition mode is adopted, with a deposition thickness of 0.14nm per cycle. A total of 2140 cycles are performed to finally obtain a gate dielectric layer 4 with a total thickness of 300nm. After deposition, it needs to be annealed at 600℃ for 20 minutes to reduce the trap charge and optimize the interface characteristics through interface energy level modulation.

[0027] Prepared The dielectric constant of the gate dielectric layer 4 can reach 25 (compared to traditional methods). (6.4 times that of the standard), significantly improving the device's gate control capability; the breakdown electric field is 8MV / m, exhibiting excellent high-voltage withstand performance; the fixed oxide charge density is less than or equal to The trap charge density is The trap energy level depth is 0.3 eV, and the trap charge can be efficiently released through annealing. In terms of radiation resistance, under a total ionizing dose of 3 Mrad, the threshold voltage drift is only 1.2 V (compared to traditional...). The composite gate dielectric reduces total ionization dose by 52%, demonstrating excellent stability against total ionization dose.

[0028] Furthermore, in a specific implementation, in the radiation-resistant photosensitive transistor provided in the embodiments of the present invention, the material of the two-dimensional semiconductor material layer 8 can be a material with a mobility greater than a preset mobility threshold; the two-dimensional semiconductor material layer 8 can be grown on a copper foil substrate using a chemical vapor deposition process and transferred to the surface of the channel layer, and then obtained after an annealing process.

[0029] It should be noted that the preset mobility threshold of the two-dimensional semiconductor material layer 8 can be determined comprehensively by considering the device's carrier transport efficiency requirements, interface contact characteristics, and radiation-resistant application scenarios. From the perspective of carrier transport, the preset mobility threshold can meet the requirement of rapid charge conduction between the source 6 and the solar-blind photosensitive region 3, reducing energy loss during transport. From the perspective of interface characteristics, it matches the interface stress relief effect of the van der Waals heterojunction, reducing defect-mediated carrier recombination. From the perspective of radiation resistance, the preset mobility threshold can ensure the stability of mobility under radiation environment, avoiding performance degradation due to ionization damage. In other words, the two-dimensional semiconductor material layer 8 uses a high-mobility two-dimensional semiconductor material. In terms of specific numerical selection, this preset mobility threshold can be no less than... This ensures the device possesses excellent switching response speed and photosensitivity. Preferably, the two-dimensional semiconductor material layer 8 can be a graphene layer, as graphene exhibits extremely excellent carrier mobility; at room temperature, the carrier mobility of intrinsic graphene can reach [value missing]. Even under the influence of fabrication and transfer processes, the carrier mobility of the graphene layer applied to the device can be stably maintained. The efficiency is above the preset mobility threshold, which can significantly optimize the carrier transport efficiency between the source 6 and the solar-blind photosensitive region 3, improve the solar-blind photosensitive responsivity of the device, and suppress the risk of leakage current surge under radiation environment.

[0030] In practice, in this invention A 5nm thick chemical vapor deposition (CVD) graphene layer is inserted between the photosensitive area and the source electrode. Through the synergy of materials and interfaces, it achieves three functions: enhanced photosensitivity, leakage current suppression, and resistance to single-particle burn-off. The specific fabrication process, core role, and overall device performance improvement are as follows: Monolayer graphene was grown on copper foil using CVD technology and then transferred to PMMA-assisted transfer. The surface is then annealed at 400℃ for 10 min to remove residual PMMA; the final prepared graphene layer has a carrier mobility greater than or equal to This allows the device to achieve a day-blind responsivity of 0.28 A / W.

[0031] The high carrier mobility of graphene can significantly improve the transport efficiency of photogenerated carriers, increasing the solar-blind responsivity from 0.2 A / W to 0.28 A / W; simultaneously with A Schottky barrier is formed in the photosensitive area, effectively suppressing off-state leakage current. Regarding radiation resistance and single-event burn-off resistance, under 700MeV Bi ion irradiation, the peak leakage current of the device decreased from 0.52A / mm to 0.08A / mm, and the single-event burn-off risk value decreased from 0.65 to 0.25.

[0032] This invention significantly enhances the device's gate control capability, solar-blind photosensitivity, radiation resistance, and single-event burn-off reliability through multi-level material and interface synergistic optimization. Specifically, it achieves: total ionizing dose tolerance greater than or equal to 3 Mrad under extreme environments, solar-blind photosensitivity greater than or equal to 0.27 A / W (optical on / off ratio greater than or equal to 5300), single-event burn-off risk value less than or equal to 0.3, and peak leakage current less than or equal to 0.08 A / mm, effectively extending the device's lifespan.

[0033] Furthermore, in a specific implementation, the radiation-resistant phototransistor provided in the embodiments of the present invention may further include: an insulating layer 9 located between the gate dielectric layer 4 and the channel layer; a polysilicon micro-heating component 10 covering the outer surface of the gate dielectric layer 4 and the channel layer; and a temperature sensor 11 disposed at the gate dielectric layer 4, the non-photosensitive functional area 2, and the solar-blind photosensitive area 3.

[0034] Figure 2 This is a second schematic diagram of the structure of a radiation-resistant photosensitive transistor provided in an embodiment of the present invention. In implementation, as... Figure 2 As shown, in the structural design of the radiation-resistant phototransistor, the integration of the insulating layer 9, the polysilicon micro-heating component 10, and the temperature sensor 11 enables in-situ repair of radiation damage. The insulating layer 9, serving as the isolation layer between the gate dielectric layer 4 and the channel layer, not only ensures precise control of the channel by the gate 5 based on its high dielectric and radiation-resistant properties, reducing radiation-induced leakage current and trap charge accumulation, but also provides a stable structural foundation for subsequent annealing repair. The polysilicon micro-heating component 10, covering the outer surface of the gate dielectric layer 4 and the channel layer, leverages the moderate thermal conductivity and small thermal diffusion range of polysilicon to achieve independent zone heating for different functional areas (gate dielectric layer 4, solar-blind photosensitive area 3, and non-photosensitive functional area 2), avoiding thermal crosstalk between areas and meeting different needs. The need for differentiated annealing temperatures in different regions; and the temperature sensors 11 distributed in the gate dielectric layer 4, the non-photosensitive functional area 2 and the solar-blind photosensitive area 3 can provide real-time feedback on the heating temperature of each region, forming a closed-loop temperature control logic with the polycrystalline silicon micro-heating component 10. This not only prevents secondary damage such as graphene heterojunction damage and carrier mobility decay caused by over-annealing, but also avoids the problem of incomplete repair caused by under-annealing. Ultimately, it ensures that the transistor can achieve efficient damage recovery through in-situ partitioned annealing under extreme radiation environments, and no offline disassembly is required throughout the process, which significantly improves the reliability and long-cycle operation capability of the device.

[0035] It should be noted that this invention aims to construct a "radiation-resistant and highly photosensitive" core carrier, and conducts device-level heterostructure optimization, which can be achieved by using... Zoned channels (solar blind photosensitive area 3 and non-photosensitive functional area 2). The core logic behind the integrated structural design of high dielectric constant gate dielectric and graphene van der Waals heterostructure stems from the precise adaptation of material properties synergy and radiation damage mechanism.

[0036] As an ultra-wide bandgap semiconductor with a bandgap of 4.8eV, its breakdown electric field is 2.4 times that of GaN and 27 times that of Si, naturally possessing excellent radiation resistance and high voltage withstand capability. The dielectric constant reaches 25, which is higher than that of traditional dielectrics. The thickness is 6.4 times that of traditional devices, which can reduce leakage current while maintaining strong gate control capability by thickening the film layer; graphene alleviates interface stress and optimizes carrier transport through van der Waals forces. The three work together to suppress two types of core damage caused by the total ionizing dose effect in the radiation environment: the accumulation of trap charge in the gate dielectric and the local thermal runaway caused by the single-event effect (single-event burn-out). This addresses the key pain points of traditional devices: one is to overcome the shortcomings of radiation resistance: for GaN solar-blind devices, the threshold voltage drift is greater than or equal to 2V under a total ionizing dose of 3Mrad, and the leakage current surge of Si-based devices. The problem of multiples, relying on Lattice stability and Less than or equal to The low trap charge density significantly improves the resistance to total ionizing dose. One key aspect is resolving the performance-priority trade-off: through a partitioned channel design, the solar-blind photosensitive region 3 is used for photon capture, while the non-photosensitive functional region 2 utilizes a RESURF in-situ doped gradient structure to uniformly apply the electric field, solving the problem that traditional single-channel designs cannot simultaneously achieve high photosensitivity and high breakdown voltage. Another aspect is optimizing interface characteristics: utilizing graphene van der Waals layers to isolate the substrate's influence, enabling… Interfacial thermal boundary resistance as low as This design avoids the problem of excessive interface defects caused by lattice mismatch in traditional covalent heterostructures, reducing defect-mediated carrier recombination. After 3Mrad total ionizing dose irradiation, the threshold voltage drift is only 0.8V, and the single-particle burn-off withstand voltage is increased to over 220V. It also exhibits excellent solar blindness sensitivity, with a photo-dark current ratio reaching [value missing]. The responsivity is greater than or equal to 0.27 A / W, with outstanding selectivity in the 200nm to 280nm solar-blind band (visible light suppression ratio R210nm / R400nm=16.2), which can avoid interference from solar background light; at the same time, the off-state leakage current is as low as With a breakdown voltage of 10kV (1 times higher than the 5kV of traditional devices), it is fully adapted to high-voltage application scenarios in extreme environments.

[0037] In the above embodiments, the radiation-resistant phototransistor has been described in detail. Based on the same inventive concept, embodiments of the present invention also provide an electronic device. This electronic device may include: a radiation-resistant phototransistor and a logic controller connected to the radiation-resistant phototransistor; a solar blindness photodetector for monitoring the photocurrent and a radiation dose monitoring component for monitoring the total ionizing dose and single-particle burn-off risk value are disposed on the radiation-resistant phototransistor; the logic controller is used to perform photoelectric coordinated control of the radiation-resistant phototransistor based on the photocurrent, total ionizing dose, and single-particle burn-off risk value data; and is also used to perform in-situ damage recovery of the radiation-resistant phototransistor based on the photocurrent and single-particle burn-off risk value data.

[0038] In the electronic device provided in the embodiments of the present invention, an integrated protection system can be constructed by integrating radiation-resistant photosensitive transistors, logic controllers, solar-blind photosensitive monitoring components, and radiation dose monitoring components. On the one hand, the dual monitoring components capture core parameters such as photosensitive current, total ionization dose, and single-event burn-off risk value in real time, providing comprehensive and accurate device status data support for the logic controller. This ensures that photoelectric synergistic regulation can respond specifically to radiation damage and changes in photosensitive performance, effectively suppressing threshold voltage drift caused by total ionization dose and leakage current surge caused by single-event effects, while ensuring high sensitivity and high selectivity of solar-blind photosensitive sensors and avoiding interference from solar background light. On the other hand, the logic controller can autonomously trigger in-situ damage repair based on monitoring data, without offline disassembly or manual intervention, achieving timely targeted repair of radiation damage, significantly improving device damage recovery rate and performance stability, greatly reducing the risk of device failure in extreme environments, and extending service life. The overall design also enables the electronic device to adapt to the long-term reliable operation requirements of extreme radiation scenarios such as satellites and nuclear facilities, taking into account both photosensitive detection accuracy and radiation resistance, breaking through the bottlenecks of traditional equipment with single monitoring parameters, lagging regulation, and cumbersome repair, and improving the continuity and reliability of equipment operation.

[0039] Since the embodiments of the electronic device portion correspond to the embodiments of the radiation-resistant photosensitive transistor portion, the description of the features in the embodiment corresponding to the electronic device portion can be found in the relevant description of the embodiment corresponding to the radiation-resistant photosensitive transistor, and will not be repeated here. Furthermore, it has the same beneficial effects as the radiation-resistant photosensitive transistor mentioned above.

[0040] Furthermore, in a specific implementation, the electronic device provided in the embodiments of the present invention may include a main branch and a backup branch connected in parallel; both the main branch and the backup branch include radiation-resistant photosensitive transistors; a solar blindness photosensitive monitoring component and a radiation dose monitoring component are disposed on the main branch. In this case, the logic controller may specifically be used to receive data on photosensitive current, total ionization dose, and single-particle burn-off risk value, and compare them with a preset first threshold; when the gate leakage current fluctuation amplitude, photosensitive current fluctuation amplitude, total ionization dose, or single-particle burn-off risk value exceeds the corresponding first threshold, a switching operation between the main branch and the backup branch is performed, and the gate bias conditions of the main branch or the backup branch are adjusted accordingly.

[0041] Figure 3 This is a schematic diagram illustrating the architecture of the main branch and backup branch provided in an embodiment of the present invention. In implementation, as... Figure 3 As shown, the electronic device can adopt a core architecture of primary and backup branch redundancy and multi-parameter collaborative control, consisting of a parallel primary branch, backup branch, and logic controller. Both the primary and backup branches are equipped with the aforementioned radiation-resistant solar-blind ultraviolet photosensitive transistors. The overall goal is to achieve closed-loop control with accurate monitoring and rapid response. Relying on redundancy fault tolerance mechanisms and real-time feedback logic, the continuity of device function and performance stability under extreme environments are guaranteed. This invention aims to solve the pain points of traditional control circuits not being adapted to the radiation resistance requirements of solar-blind photosensitive devices, the inability to predict radiation damage due to single monitoring parameters, and the easy interruption of function due to device failure due to the lack of redundant circuits. By quickly switching between primary and backup branches to achieve fault redundancy, the monitoring components are strongly bound to the core performance of the device to ensure the accuracy of the control signal. At the same time, by utilizing the correlation between radiation damage and photosensitive signals, damage prediction and timely intervention are triggered by threshold comparison, and the control needs of multiple damage types are adapted to achieve one control strategy for one type of damage.

[0042] Among them, the main and backup branch circuits adopt The heterogeneous complementary topology has a completely identical structure. The main branch handles both solar-blind photosensitive and conventional high-power switching tasks. High dielectric constant enables precise gate control, The partitioned design balances photosensitive and power performance, while the backup branch serves as a redundant backup for total ionizing dose / single-event burnout failures. The logic controller adopts radiation-hardened CMOS technology (total ionizing dose tolerance greater than or equal to 5Mrad) and can monitor the gate leakage current, photosensitive current fluctuation amplitude, and single-event burnout risk value of the main branch in real time. When any parameter exceeds the preset first threshold, the main and backup branches can be switched within 10ns to 100ns. During the switching process, the output fluctuation is less than or equal to 5%, ensuring that the detection and control functions are not interrupted.

[0043] The electronic device of this invention also integrates a solar blindness photodetector and a radiation dose monitoring component to achieve simultaneous acquisition of multi-physics field signals and risk warning. The solar blindness photodetector is composed of... Composed of a photosensitive device and a radiation-hardened amplifier circuit, it has a response wavelength of 254nm, a responsivity of 0.28A / W, and a UV / visible light suppression ratio. It can capture solar blind ultraviolet signals in real time and eliminate visible light interference. The radiation dose monitoring component adopts a 4H-SiC PIN sensor with a monitoring range of 0-5Mrad and a response time of less than or equal to 1μs. It can simultaneously output total ionization dose data and single-particle burn-off risk warning signal.

[0044] For different operating conditions, this invention proposes a differentiated dynamic bias voltage coordinated control strategy: when the total ionization dose is greater than or equal to 200 krad, the gate bias voltage drops from 0V to -2V to -1V, reducing... Hole trapping in the gate dielectric suppresses threshold voltage drift; when the single-event burn-out risk value is greater than or equal to 0.3, a transient gate voltage of -5V to -3V is applied to enhance [the effect]. The depletion region width is used to suppress leakage current surges; when the photosensitive current falls below 10% of the reference value, the gate voltage is finely adjusted (+0.1 to +0.2V) to quickly restore photosensitivity. Through the above architecture and control design, this invention ultimately achieves the technical effect of a total ionization dose monitoring error of less than or equal to 5% and a single-particle burn-up risk identification response time of less than or equal to 1μs, enabling intervention to be triggered before damage worsens and controlling device parameter fluctuations within a certain range. Within, simultaneously coordinating transistors The gate dielectric and graphene heterojunction structure suppress the accumulation of trapped charges and the surge in leakage current, ensuring that the device has no significant output interruption during annealing repair or radiation peak, and is suitable for application requirements in extreme environments such as satellites and nuclear facilities.

[0045] Furthermore, in a specific implementation, in the electronic device provided in the embodiments of the present invention, the logic controller can be specifically used to receive photosensitive current and single-particle burn-off risk value data, and compare them with a preset second threshold; when the gate leakage current, the fluctuation amplitude of the photosensitive current, or the single-particle burn-off risk value exceeds the corresponding second threshold, according to the coverage area of ​​the polycrystalline silicon micro-heating component 10 and the corresponding temperature sensor 11, an independent power supply is used to perform partitioned annealing, and different temperatures and durations of annealing operations are performed on different areas to perform in-situ damage recovery.

[0046] Figure 4 This is a schematic diagram of the structure of an electronic device for in-situ damage recovery provided in an embodiment of the present invention. In implementation, as... Figure 4As shown, the electronic device adopts an integrated structure consisting of an insulating layer 9 for separation, polycrystalline silicon micro-heating components 10 for zoned coverage, temperature sensors 11 for zoned coverage, and differentiated annealing logic. Relying on a differentiated repair mechanism and closed-loop temperature control logic, it achieves precise targeted repair of radiation damage to the device. This device is integrated into the electronic device, and the main body includes the aforementioned radiation-resistant solar-blind ultraviolet photosensitive transistor and logic controller 12. The transistor is equipped with a solar-blind photosensitive monitoring component 13 and a radiation dose monitoring component 14. An insulating layer 9 is placed between the gate dielectric layer 4 and the channel layer, and the outer surfaces of both are covered with polycrystalline silicon micro-heating components 10. Temperature sensors 11 are configured in the gate dielectric layer 4, the solar-blind photosensitive area 3, and the non-photosensitive functional area 2. The logic controller receives data from each monitoring component and compares it with a preset second threshold. When the gate leakage current, the fluctuation amplitude of the photosensitive current, or the single-particle burn-off risk value exceeds the threshold, it relies on the coverage area of ​​the polycrystalline silicon micro-heating component 10 and the corresponding temperature sensor 11 to perform zoned annealing through an independent power supply. Differentiated temperature and duration annealing operations are used for different areas to achieve in-situ damage recovery.

[0047] This device overcomes the drawback of traditional offline annealing, which requires disassembling components for overall heating, thus avoiding the problems caused by excessively high overall temperatures (greater than or equal to 200°C). Issues such as heterojunction interface diffusion and carrier mobility reduction greater than or equal to 20%; the need for partitioned design of heterojunctions at the adapter level to address significant differences in damage repair temperature thresholds across different regions. This design features a specific temperature range (160℃ required for the non-photosensitive area, 140℃ for the non-photosensitive area, and 120℃ for the photosensitive area). It avoids the conflict between overall heating and material tolerance by using zoned heating and temperature measurement. The polycrystalline silicon micro-heating component is made of a material with moderate thermal conductivity, allowing for rapid heating and a small thermal diffusion range, effectively preventing thermal crosstalk between areas. The temperature sensor uses a platinum resistance thermometer, achieving high measurement accuracy. The response time is less than or equal to 100μs, meeting the precise temperature control requirements of differentiated annealing.

[0048] In this embodiment, both the insulating layer and the gate dielectric layer are selected from materials with high dielectric constant, radiation resistance, and excellent thermal stability. The annealing temperature range is set from 140℃ to 180℃, which improves gate control efficiency and suppresses leakage current through high dielectric properties, reduces trap charge accumulation in a radiant environment, and matches the annealing temperature requirements of polycrystalline silicon micro-heating components. Structurally, The insulating layer is located between the gate electrode and Between the photosensitive areas of solar blindness, grid electrodes are formed. and The channel MIS structure is compatible with polysilicon micro-heating components and source / drain electrodes in terms of layout. Functionally, it not only serves as the foundation for gate control, ensuring solar-blind photosensitivity and electrical control, but also plays a role in radiation hardening, avoiding radiation-induced performance degradation. At the same time, it assists polysilicon micro-heating components in completing the in-situ damage repair cycle of heating, trap charge release, and performance recovery, ensuring the functional continuity and reliability of the chip in special scenarios.

[0049] against and To address different damage mechanisms, this invention provides a differentiated annealing scheme: In terms of hardware, sheet resistors... Polycrystalline silicon micro heating components and precision Independent coverage of platinum resistance temperature sensor Region and Each partition; annealing parameters have been optimized and matched. The region is annealed at 160℃ for 25 hours to accelerate the release of trapped charges through high temperature, and the gate leakage current recovery rate is greater than or equal to 98%. The photosensitive area is annealed at 120℃ for 40 hours to avoid high-temperature damage to the graphene heterojunction, and the carrier lifetime and responsivity recovery rate are both greater than or equal to 95%. The non-photosensitive area is annealed at 140℃ for 35 hours to restore the carrier transport capacity, and the on-resistance recovery rate is greater than or equal to 90%.

[0050] To ensure the annealing effect, an intelligent triggering mechanism is also provided, such as... Figure 4 As shown, the baseline established based on parameter calibration component 15 enables automated and precise annealing: within 10ms after chip power-on, the built-in standard current / voltage source will... Leakage current, The photosensitivity and graphene contact resistance were calibrated to establish a baseline for pre-irradiation parameters; when device parameter degradation exceeded a threshold, Gate leakage current greater than or equal to 1e-10 A When the photosensitive area responsivity decreases by more than or equal to 10% or the single particle burn-out risk value is greater than or equal to 0.3, annealing is automatically triggered, and an independent power supply is used during annealing to avoid interfering with the business circuit.

[0051] This invention can achieve efficient in-situ repair with a damage recovery rate greater than or equal to 95%, wherein The gate dielectric trap charge release rate reaches 98.3%. The photosensitive area responsivity recovered to 99.3% of its initial value; partitioned annealing strictly controlled the temperature of each region within the tolerance threshold, maintaining the graphene carrier mobility at or above the threshold. There is no significant attenuation; it can achieve automated operation by triggering when the threshold is exceeded and stopping when the temperature reaches the target without manual intervention. After 1000 annealing cycles, the performance change rate of the heating component and sensor is less than or equal to 3%, which can meet the long-term use requirements of the device in extreme environments.

[0052] To verify the effectiveness of this invention, a corresponding simulation model was first constructed for simulation verification. During the model construction phase, a targeted discrete computational grid was generated using the `generate_grid()` function. The grid consisted of 100 nodes in the gate dielectric region, 600 nodes in the substrate region, 200 nodes in the photosensitive region, and 100 nodes in the non-photosensitive region, totaling approximately 1000 grid points. The minimum grid spacing was set to... The model calls physical field calculation functions such as `get_carrier_concentration()` and `calculate_electric_field()` to solve for the spatial distribution data of key physical quantities such as carrier concentration distribution, electric field strength, current density, temperature field, and single-particle burn-up risk. Simultaneously, during the model initialization phase (taking less than or equal to 10 milliseconds), a parameter calibration process is executed to calibrate core parameters such as the doping concentration of the photosensitive area and the dielectric constant of tantalum oxide, establishing a simulation baseline that closely matches physical reality and ensuring the accuracy of subsequent simulations.

[0053] Simulation results show that the present invention meets or exceeds the design specifications in terms of performance in solar-blind photosensitivity, resistance to single-particle burn-off, and thermal management and damage recovery: in the solar-blind photosensitivity level, the proportion of photogenerated carriers is approximately 15.2%, the photosensitivity is improved by 40%, the responsivity reaches 0.281 A / W, and the UV / visible light suppression ratio is as high as With a carrier on / off ratio of 5280, it exhibits excellent selectivity and sensitivity. Regarding single-event burn-off resistance and electric field characteristics, the maximum electric field of the entire device is 2.38 MV / m (far below the breakdown threshold of 8 MV / m), and the maximum electric field in the photosensitive area is 2.12 MV / m (35% lower than the non-partitioned structure), demonstrating significantly optimized electric field distribution. The maximum risk value for single-event burn-off is as low as 0.25, the length of the high-risk region is close to zero, and the peak leakage current is 0.07 A / mm, meeting safe operation requirements. In terms of thermal and damage recovery performance, the highest operating temperature of the entire device is 582.3 K, and the highest temperature in the photosensitive area is 548.7 K, both below the material's thermal failure threshold. The partitioned annealing strategy achieves efficient recovery. The gate dielectric trap charge release rate reaches 98.3%. The photosensitive area has a responsivity recovery rate of up to 99.3%. These data validate the high reliability and long-life operation potential of this invention under extreme environments.

[0054] The core control chip of this invention is applied to the power controller of a satellite at an orbital altitude of 500km (radiation environment: total ionizing dose 2Mrad / year, SEE trigger probability). After 12 months of continuous operation, the results were significant: in terms of parameter stability, the threshold voltage (Vth) drift of the SiC VDMOSFET was less than or equal to 0.2V. HJ-FET leakage current ( ) is always less than or equal to No functional failures; regarding annealing recovery, the annealing process was automatically triggered twice during the period (in the 4th and 9th months), and after each annealing... Leakage current recovered to Below, SiC Vth recovers to over 90% of its initial value; regarding output performance, because... The HJ-FET withstand voltage has been increased to 10kV, and the output voltage fluctuation of the power controller has been optimized from less than or equal to 2% to less than or equal to 1.5%, meeting the high reliability requirements of satellite high-power power supply.

[0055] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (FPGAs), field-programmable gate arrays (FPGAs), etc.

[0056] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0057] The above provides a detailed description of the radiation-resistant photosensitive transistor and electronic device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the embodiments above are only intended to help understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A radiation-resistant photosensitive transistor, characterized in that, include: Substrate; A channel layer is located on the substrate; the channel layer includes a non-photosensitive functional region close to the substrate and a solar-blind photosensitive region located on the side of the non-photosensitive functional region away from the substrate; the channel layer is made of a semiconductor material with a band gap greater than a set band gap threshold; the non-photosensitive functional region and the solar-blind photosensitive region are connected by an in-situ doping gradient transition to form a RESURF structure; A gate dielectric layer and an electrode structure are located on the channel layer; the gate dielectric layer is located between the gate of the electrode structure and the solar-blind photosensitive region; the material of the gate dielectric layer is a material with a dielectric constant greater than a preset dielectric constant threshold. A two-dimensional semiconductor material layer is located between the source electrode of the electrode structure and the solar-blind photosensitive region; the two-dimensional semiconductor material layer and the material of the solar-blind photosensitive region form a van der Waals heterojunction.

2. The radiation-resistant photosensitive transistor according to claim 1, characterized in that, The solar-blind photosensitive region is grown using molecular beam epitaxy (MBE) and has a thickness ranging from 300 nm to 800 nm. The solar-blind photosensitive region is n-type doped, with a doping concentration ranging from [missing value]. to ; The non-photosensitive functional region is grown using a metal-organic chemical vapor deposition process, with a thickness ranging from 1.0 μm to 2.0 μm; the non-photosensitive functional region is n-type doped, with a doping concentration ranging from [missing value]. to .

3. The radiation-resistant photosensitive transistor according to claim 1, characterized in that, The source electrode of the electrode structure forms a Schottky contact with the solar-blind photosensitive area through the two-dimensional semiconductor material layer; The drain of the electrode structure forms an ohmic contact with the solar-blind photosensitive area.

4. The radiation-resistant photosensitive transistor according to claim 1, characterized in that, The gate dielectric layer is prepared using atomic layer deposition (ALD) with tantalum pentaethoxy and deionized water as precursors. The total thickness of the gate dielectric layer is controlled by setting the deposition thickness per cycle and accumulating the corresponding number of deposition cycles.

5. The radiation-resistant photosensitive transistor according to claim 1, characterized in that, The material of the two-dimensional semiconductor material layer is a material with a mobility greater than a preset mobility threshold. The two-dimensional semiconductor material layer is grown on a copper foil substrate using a chemical vapor deposition process and transferred to the surface of the channel layer, followed by an annealing process.

6. The radiation-resistant photosensitive transistor according to claim 1, characterized in that, The channel layer is made of β-phase gallium oxide; the gate dielectric layer is made of tantalum pentoxide; and the two-dimensional semiconductor material layer is a graphene layer.

7. The radiation-resistant photosensitive transistor according to claim 1, characterized in that, Also includes: An insulating layer is located between the gate dielectric layer and the channel layer; A polycrystalline silicon micro-heating component is covered on the outer surface of the gate dielectric layer and the channel layer; A temperature sensor is disposed in the grid dielectric layer, the non-photosensitive functional area, and the solar-blind photosensitive area.

8. An electronic device, characterized in that, include: The radiation-resistant phototransistor as described in any one of claims 1 to 7, and the logic controller connected to the radiation-resistant phototransistor; The radiation-resistant phototransistor is provided with a solar blindness photodetector for monitoring the photosensitive current and a radiation dose monitoring component for monitoring the total ionization dose and single-particle burn-off risk value. The logic controller is used to perform photoelectric coordinated control of the radiation-resistant phototransistor based on the photosensitive current, total ionization dose, and single-particle burn-off risk data. It is also used to perform in-situ damage recovery of the radiation-resistant phototransistor based on the photosensitive current and single-particle burn-out risk value data.

9. The electronic device according to claim 8, characterized in that, The electronic device includes a main branch and a backup branch connected in parallel; both the main branch and the backup branch include the radiation-resistant photosensitive transistor; the solar blindness photosensitive monitoring component and the radiation dose monitoring component are disposed on the main branch; The logic controller is used to receive data on photosensitive current, total ionization dose, and single-particle burn-off risk, and compare them with a preset first threshold. When the gate leakage current fluctuation amplitude, photosensitive current fluctuation amplitude, total ionization dose, or single-particle burn-out risk value exceeds the corresponding first threshold, the main branch and the backup branch are switched, and the gate bias conditions of the main branch or the backup branch are adjusted accordingly.

10. The electronic device according to claim 8, characterized in that, The logic controller is used to receive photosensitive current and single-particle burn-off risk value data and compare them with a preset second threshold. When the gate leakage current, the fluctuation amplitude of the photosensitive current, or the single-particle burn-off risk value exceeds the corresponding second threshold, the controller uses an independent power supply to perform partitioned annealing based on the coverage area of ​​the polycrystalline silicon micro-heating component and the corresponding temperature sensor, and performs annealing operations at different temperatures and durations for different areas to restore damage in situ.

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