Display panel

Abstract

The invention discloses a display panel. The service life of the display panel can be prolonged. The display panel is provided with a hole opening area, a winding area and a display area, and the winding area is located between the hole opening area and the display area. The display panel comprises an array substrate, a pixel definition layer, a light-emitting common layer, a first partition structure and an opening. The array substrate comprises a plurality of winding area wires; the plurality of winding area wires are located in the winding area and arranged around the opening area. The pixel definition layer is located on one side of the array substrate and is provided with a pixel opening. At least part of the light-emitting common layer is located in the pixel opening and the side, away from the array substrate, of the pixel defining layer. The first partition structure is located in the winding area, is located between the pixel definition layer and the light-emitting common layer, and disconnects the light-emitting common layer in the winding area. The open hole is located in the open hole area and at least penetrates through the array substrate in the stacking direction of the array substrate and the pixel definition layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] Organic light-emitting diode (OLED) display devices have become the mainstream direction of display device development due to their high contrast, wide color gamut, fast response speed, low power consumption, folding potential and other advantages. With the development of display technology, in the manufacturing of OLED display screens, in order to pursue a higher screen ratio and at the same time meet the needs of taking pictures, a camera area is generally required to be set in the screen. In order to achieve good shooting effect, the screen area where the camera is located is cut off, that is, an opening is formed. However, water vapor and the like from the outside will gradually penetrate into the organic light-emitting diode display device in the display area through the opening, resulting in poor performance of the organic light-emitting diode display device and shortening the service life of the OLED display screen. SUMMARY

[0003] Embodiments of the present application provide a display panel to at least partially solve the above technical problems.

[0004] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, a display panel is provided, the display panel has an opening area, a winding area and a display area, and the winding area is located between the opening area and the display area. The display panel comprises an array substrate, a pixel definition layer, a light-emitting common layer, a first partition structure and an opening. The array substrate comprises a plurality of winding area wirings; the plurality of winding area wirings are located in the winding area and are arranged around at least part of the opening area. The pixel definition layer is located on one side of the array substrate and is provided with a pixel opening. At least part of the light-emitting common layer is located in the pixel opening and on the side of the pixel definition layer away from the array substrate. The first partition structure is located in the winding area and between the pixel definition layer and the light-emitting common layer, and disconnects the light-emitting common layer of the winding area. The opening is located in the opening area and penetrates at least the array substrate along the stacking direction of the array substrate and the pixel definition layer.

[0005] Optionally, the first partition structure comprises a bottom surface and a top surface arranged oppositely, the top surface is located on the side of the bottom surface away from the array substrate, and the area of the bottom surface is smaller than the area of the top surface.

[0006] Optionally, the first partition structure is arranged around the opening area.

[0007] Optionally, the material of the first partition structure is different from the material of the pixel definition layer.

[0008] Optionally, the first partition structure includes an insulating material, the light-emitting common layer includes a cathode layer, and the first partition structure isolates the cathode layer.

[0009] Optionally, the array substrate includes a substrate, and a plurality of the winding area wirings are located on the substrate; The pixel definition layer also includes a dam and a support structure, the dam being disposed around the pixel opening and the support structure being located on the surface of the dam facing away from the array substrate; Wherein, the distance from the first top end of the first partition structure to the substrate is less than or equal to the distance from the second top end of the support structure to the substrate, the first top end is the end of the first partition structure facing away from the array substrate, and the second top end is the end of the support structure facing away from the array substrate.

[0010] Optionally, the display panel further includes an encapsulation area located between the winding area and the opening area; The array substrate includes an organic insulating layer and an inorganic insulating layer, wherein the organic insulating layer is located between the inorganic insulating layer and the pixel definition layer; The display panel is also provided with an opening, which is located in the encapsulation area and penetrates the pixel definition layer and the organic insulating layer, and exposes the inorganic insulating layer; The display panel further includes a second partition structure located within the opening and on the inorganic insulating layer, which isolates the light-emitting common layer.

[0011] Optionally, the encapsulation area includes a first encapsulation area and a second encapsulation area; The display panel further includes a blocking structure, which is located between the first encapsulation area and the second encapsulation area and on the array substrate, and the second encapsulation area is located between the blocking structure and the opening area; The number of second partition structures provided in the second packaging area is greater than the number of second partition structures provided in the first packaging area.

[0012] Optionally, the organic insulating layer is not provided between adjacent second partition structures in the first encapsulation area.

[0013] Optionally, the light-emitting common layer includes a cathode layer and a common organic layer, the common organic layer being located between the cathode layer and the pixel definition layer; the second partition structure disconnects the cathode layer and the common organic layer.

[0014] In the display panel of this application embodiment, a first partition structure is added to the winding area where multiple winding wirings are provided. The first partition structure is located between the pixel definition layer and the light-emitting common layer, and disconnects the light-emitting common layer of the winding area. This reduces the risk of external pollutants such as water vapor penetrating into the display area through the light-emitting common layer of the winding area under high temperature and humidity conditions, thereby improving the reliability of the display panel in high temperature and humidity environments and extending the service life of the display panel. Furthermore, since the first partition structure is located in the winding area, the winding area can provide more space for the first partition structure, which is conducive to increasing the number of first partition structures, thereby improving the overall isolation effect of multiple first partition structures on the light-emitting common layer. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an exemplary embodiment of this application; Figure 2 This is a cross-sectional view of the display area and redundant pixel area of ​​the display panel provided in an exemplary embodiment of this application; Figure 3 This is a cross-sectional view of the winding area and encapsulation area of ​​the display panel provided in an exemplary embodiment of this application; Figure 4 This is a partial cross-sectional view of the light-emitting device layer provided in an exemplary embodiment of this application; Figure 5 and Figure 6 This is a partially enlarged schematic diagram of the manufacturing process of the display panel provided in an exemplary embodiment of this application.

[0016] Explanation of reference numerals in the attached figures: 100, Display panel; 100A, Display area; 100B, Opening area; 100C, Winding area; 100D, Encapsulation area; 100D1, First encapsulation area; 100D2, Second encapsulation area; 100E, Redundant pixel area; 1. Array substrate; 11. Substrate; 121. Display area wiring; 122. Winding area wiring; 130. Metal layer; 131. First metal layer; 132. Second metal layer; 133. Third metal layer; 134. Fourth metal layer; 141. Inorganic insulating layer; 142. Organic insulating layer; 2. Pixel definition layer; 21. Pixel opening; 22. Dam; 23. Support structure; 3. Light-emitting device layer; 31. Anode layer; 32. Light-emitting layer; 33. Shared light-emitting layer; 331. Cathode layer; 332. Shared organic layer; 4. Thin-film encapsulation layer; 41. First inorganic encapsulation layer; 42. Organic encapsulation layer; 5. Opening a hole; 61. First partition structure; 611. Bottom surface; 612. Top surface; 62. Second partition structure; 621. First conductive part; 622. Second conductive part; 623. Third conductive part; 7. Opening; 81. Barrier structure; 82. Crack barrier structure. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0018] Please see Figures 1 to 3 This application provides a display panel 100, which has an opening area 100B, a winding area 100C, and a display area 100A. The winding area 100C is located between the opening area 100B and the display area 100A. The display panel 100 includes an array substrate 1, a pixel definition layer 2, and a light-emitting device layer 3.

[0019] The array substrate 1 includes a substrate 11, multiple display area wirings 121, and multiple winding area wirings 122, all located on the substrate 11. The multiple display area wirings 121 are located in the display area 100A and include multiple data lines and multiple scan lines. The multiple winding area wirings 122 are located in the winding area 100C and are disposed around at least a portion of the opening area 100B. Each winding area wiring 122 is connected to a corresponding display area wiring 121.

[0020] The array substrate 1 also includes multiple metal layers 130 located on the substrate 11. The multiple metal layers 130 include multiple display area wirings 121 and multiple winding area wirings 122.

[0021] In some embodiments, the plurality of metal layers 130 may include a first metal layer 131 and a second metal layer 132, wherein the second metal layer 132 is located on the side of the first metal layer 131 facing away from the substrate 11. The first metal layer 131 may be referred to as a first gate metal layer 130, and the first metal layer 131 may include the gate of a transistor and multiple scan lines. The second metal layer 132 may also be referred to as a first source / drain metal layer, and the second metal layer 132 may include the source / drain electrodes of a transistor and multiple data lines.

[0022] In some embodiments, the plurality of metal layers 130 may include, in addition to the first metal layer 131 and the second metal layer 132, a third metal layer 133 and a fourth metal layer 134. The third metal layer 133 may also be referred to as the second gate metal layer. The third metal layer 133 is located between the first metal layer 131 and the second metal layer 132 and includes an electrode plate of a capacitor, which overlaps with the gate of a transistor. The fourth metal layer 134 may also be referred to as the second source / drain metal layer. The fourth metal layer 134 is located on the side of the third metal layer 133 facing away from the substrate 11 and includes power signal lines.

[0023] In some embodiments, the array substrate 1 may further include an inorganic insulating layer 141 and an organic insulating layer 142, wherein the inorganic insulating layer 141 is located between the organic insulating layer 142 and the substrate 11, and the organic insulating layer 142 is located between the inorganic insulating layer 141 and the pixel definition layer 2. A plurality of metal layers 130 are located in one or more of the following: between the inorganic insulating layer 141 and the substrate 11; inside the inorganic insulating layer 141; between the inorganic insulating layer 141 and the organic insulating layer 142; inside the organic insulating layer 142; and between the organic insulating layer 142 and the pixel definition layer 2.

[0024] In some embodiments, when the plurality of metal layers 130 include a first metal layer 131 and a second metal layer 132, the inorganic insulating layer 141 may include a first gate insulating layer and an interlayer insulating layer, wherein the first gate insulating layer is located between the first metal layer 131 and the substrate 11, and the interlayer insulating layer is located between the first metal layer 131 and the second metal layer 132.

[0025] In some embodiments, when the plurality of metal layers 130 include a first metal layer 131 and a second metal layer 132, and also a third metal layer 133 and a fourth metal layer 134, the inorganic insulating layer 141 may further include a second gate insulating layer, the second gate insulating layer being located between the first metal layer 131 and the third metal layer 133, and the interlayer insulating layer being located between the third metal layer 133 and the fourth metal layer 134.

[0026] In some embodiments, the organic insulating layer 142 may include one or more organic planarization layers for planarizing the uneven areas caused by the inorganic insulating layer 141 and the plurality of metal layers 130 beneath the organic insulating layer 142.

[0027] The pixel definition layer 2 is located on one side of the array substrate 1 and has a plurality of pixel openings 21. The pixel definition layer 2 also includes a dam 22 and a support structure 23. At least a portion of the pixel openings 21 are located in the display area 100A. The dam 22 is disposed around the pixel openings 21, and the support structure 23 is located on the surface of the dam 22 facing away from the array substrate 1 and in the display area 100A. When forming a light-emitting layer 32 or the like in the pixel openings 21, a mask can be placed on the support structure 23 so that the support structure 23 provides support for the mask. In some embodiments, the shape of the longitudinal section of the pixel opening 21 may include an inverted trapezoid, and the longitudinal section of the pixel opening 21 is perpendicular to the substrate 11. In some embodiments, the shape of the longitudinal section of the support structure 23 may include a trapezoid, and the longitudinal section of the support structure 23 is perpendicular to the substrate 11.

[0028] In some embodiments, the pixel definition layer 2 may include a light-transmitting pixel definition layer (not shown in the figure), and the pixel opening 21 extends through the light-transmitting pixel definition layer along the thickness direction of the pixel definition layer 2.

[0029] In some embodiments, the pixel definition layer 2 may include a light-transmitting pixel definition layer (not shown in the figure) and a light-absorbing pixel definition layer (not shown in the figure). The light-absorbing pixel definition layer is located on the side of the light-transmitting pixel definition layer away from the substrate 11, and the pixel opening 21 penetrates the light-transmitting pixel definition layer and the light-absorbing pixel definition layer along the thickness direction of the pixel definition layer 2.

[0030] Please see Figure 1 and Figure 4 The light-emitting device layer 3 includes an anode layer 31, multiple light-emitting layers 32, and a common light-emitting layer 33.

[0031] The anode layer 31 is located between the pixel definition layer 2 and the array substrate 1, and includes a plurality of anodes spaced apart from each other. Exemplarily, the anode layer 31 is located between the organic insulating layer 142 and the pixel definition layer 2. Each pixel opening 21 exposes a corresponding anode.

[0032] Each light-emitting layer 32 is located in a corresponding pixel opening 21 and is located on the anode. The multiple light-emitting layers 32 may include a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer. The first light-emitting layer, the second light-emitting layer, and the third light-emitting layer can be used to emit three different colors of visible light, such as red light, blue light, and green light, respectively.

[0033] At least a portion of the shared light-emitting layer 33 is located in the pixel opening 21 and on the side of the pixel definition layer 2 facing away from the array substrate 1, and is located in the display area 100A and the winding area 100C. In some embodiments, the shared light-emitting layer 33 may include a cathode layer 331, which covers a plurality of light-emitting layers 32 and the pixel definition layer 2, and includes a conductive material such as silver. In some embodiments, in addition to the cathode layer 331, the shared light-emitting layer 33 may also include a shared organic layer 332, which is located between the cathode layer 331 and the pixel definition layer 2, and is located in the pixel opening 21 and on the side of the pixel definition layer 2 facing away from the array substrate 1. In some embodiments, the shared organic layer 332 is located between the light-emitting layer 32 and the anode layer 31, and between the cathode layer 331 and the light-emitting layer 32. In some embodiments, the common organic layer 332 may include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0034] In some embodiments, the display panel 100 further includes a redundant pixel region 100E, which is located between the winding region 100C and the display region 100A. A pixel opening 21 is also located in the redundant pixel region 100E, and the light-emitting layer 32 may also be located in the pixel opening 21, which is also located in the redundant pixel region 100E. During the formation of the multiple light-emitting layers 32, the light-emitting layer 32 in the redundant pixel region 100E can buffer the light-emitting layer 32 in the display region 100A, thereby improving the uniformity of the thickness of the light-emitting layer 32 in the display region 100A.

[0035] The display panel 100 also includes a thin-film encapsulation layer 4, which is located on the side of the light-emitting device layer 3 facing away from the array substrate 1, to encapsulate the light-emitting device layer 3. The thin-film encapsulation layer 4 includes a first inorganic encapsulation layer 41, an organic encapsulation layer 42, and a second inorganic encapsulation layer (not shown in the figure). The organic encapsulation layer 42 is located between the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer, with the first inorganic encapsulation layer 41 located on the side of the organic encapsulation layer 42 closer to the light-emitting device layer 3.

[0036] The display panel 100 also has an opening 5, which is located in the opening area 100B and extends at least through the array substrate 1, the pixel definition layer 2, the light-emitting common layer 33, and the thin film encapsulation layer 4 along the stacking direction of the array substrate 1 and the pixel definition layer 2. When a photosensitive element or a light-emitting device is disposed below the display panel 100, light can pass through the opening 5 and be received by the photosensitive element, or light can be emitted by the light-emitting device and then emitted through the opening 5.

[0037] In some embodiments, please refer to Figure 3 The display panel 100 also includes a first partition structure 61, which is located in the winding area 100C and between the pixel definition layer 2 and the light-emitting common layer 33, and disconnects the light-emitting common layer 33 of the winding area 100C. By adding the first partition structure 61 to the winding area 100C, which has multiple winding area wirings 122, and by disconnecting the light-emitting common layer 33 of the winding area 100C, the risk of external pollutants such as moisture penetrating into the display area 100A through the light-emitting common layer 33 of the winding area 100C under high temperature and high humidity conditions is reduced. This improves the reliability of the display panel 100 in high temperature and high humidity environments, thereby extending the service life of the display panel 100. Furthermore, since the first partition structure 61 is located in the winding area 100C, the winding area 100C can provide more space for the first partition structure 61, which is conducive to increasing the number of the first partition structure 61, thereby improving the overall partitioning effect of multiple first partition structures 61 on the light-emitting common layer 33.

[0038] In some embodiments, please refer to Figure 3 The first partition structure 61 includes a bottom surface 611 and a top surface 612 disposed opposite to each other. The top surface 612 is located on the side of the bottom surface 611 that faces away from the array substrate 1, and the area of ​​the bottom surface 611 is smaller than the area of ​​the top surface 612. Thus, the size of the top surface 612 of the first partition structure 61 is larger than the size of the bottom surface 611 of the first partition structure 61, enabling the first partition structure 61 to function as a barrier to the light-emitting common layer 33 formed thereon.

[0039] In some embodiments, the shape of the longitudinal section of the first partition structure 61 may include, but is not limited to, an inverted trapezoid, and the longitudinal section of the first partition structure 61 is perpendicular to the substrate 11. In this way, the area of ​​the bottom surface 611 of the first partition structure 61 may be smaller than the area of ​​the top surface 612 of the first partition structure 61.

[0040] In some embodiments, the first partition structure 61 is disposed around the opening area 100B, that is, the orthographic projection of the first partition structure 61 on the substrate 11 is annular. In this way, the first partition structure 61 can separate the light-emitting common layer 33 around the opening area 100B from the light-emitting common layer 33 of the display area 100A, reducing the risk of external pollutants such as moisture penetrating into the display area 100A through the continuous light-emitting common layer 33.

[0041] In some embodiments, a plurality of first partition structures 61 are arranged sequentially from the inside to the outside around the opening area 100B to improve the overall isolation capability of the plurality of first partition structures 61 to the light-emitting common layer 33. Furthermore, by providing a plurality of first partition structures 61 in the winding area 100C, the space of the winding area 100C can be fully utilized to improve the problem of increasing the area of ​​the non-display area 100A of the display panel 100 due to the addition of a plurality of first partition structures 61.

[0042] In some embodiments, the dimensions of the plurality of first partition structures 61 along the stacking direction between the array substrate 1 and the pixel definition layer 2, which may also be referred to as the height of the first partition structure 61, may be the same, so that the plurality of first partition structures 61 can be formed using the same manufacturing process, thereby simplifying the manufacturing process of the plurality of first partition structures 61.

[0043] In other embodiments, the dimensions of the plurality of first partition structures 61 along the stacking direction between the array substrate 1 and the pixel definition layer 2 may also be different from each other. For example, the height of the plurality of first partition structures 61 increases in the direction near the aperture region 100B; or, the height of the plurality of first partition structures 61 first increases and then decreases in the direction near the aperture region 100B.

[0044] In some embodiments, the material of the first partition structure 61 may be different from the material of the pixel definition layer 2. Since the longitudinal section of the support structure 23 of the pixel definition layer 2 is typically trapezoidal, and the top surface 612 of the first partition structure 61 is larger than the ground surface 611, it is difficult to form the first partition structure 61 and the support structure 23 of the pixel definition layer 2 by patterning the same organic insulating material. When the material of the first partition structure 61 is different from the material of the pixel definition layer 2, the first partition structure 61 and the pixel definition layer 2 can be obtained by patterning two different organic material layers. In one example, the first partition structure 61 can be obtained by exposure to negative photoresist followed by development, and the pixel definition layer 2 can be obtained by exposure to positive photoresist followed by development.

[0045] In some embodiments, the first partition structure 61 includes an insulating material, and the light-emitting common layer 33 includes a cathode layer 331. The first partition structure 61 isolates the cathode layer 331. When the first partition structure 61 includes an insulating material, the first partition structure 61 and the cathode layer 331 are electrically insulated, reducing the risk that the cathode layer 331 around the opening area 100B and the cathode layer 331 of the display area 100A will be electrically connected through the first partition structure 61. This reduces the risk that when the cathode layer 331 of the display area 100A is connected to a negative voltage, the cathode layer 331 around the opening area 100B will prevent the K-rays entering through the opening 5 in the polarizer on the display panel 100 from the display panel 100. +Ions and other particles are transported to the cathode layer 331 of the display area 100A, causing the first inorganic encapsulation layer 41 in the thin film encapsulation layer 4 to be K-. + The risk of ion corrosion leading to failure of the 100A package in the display area.

[0046] In some embodiments, the first partition structure 61 may include an organic insulating material, which allows the first partition structure 61 to be designed to be taller, thereby improving the partitioning performance of the first partition structure 61. In some embodiments, the first partition structure 61 may include an organic insulating material obtained by exposure and development of negative photoresist, so that after exposure and development, the organic layer forming the first partition structure 61 forms a structure in which the size of the top surface 612 is larger than the size of the bottom surface 611.

[0047] In some embodiments, the first partition structure 61 contacts the surface of the dam 22 facing away from the array substrate 1. Since the pixel definition layer 2 is typically an organic layer, when the first partition structure 61 includes an organic insulating material, the bonding force between the first partition structure 61 and the pixel definition layer 2 is stronger, reducing the risk of the first partition structure 61 peeling off from the dam 22.

[0048] In some embodiments, the distance D1 from the first tip T1 of the first partition structure 61 to the substrate 11 is less than or equal to the distance D2 from the second tip of the support structure 23 to the substrate 11. The first tip is the end of the first partition structure 61 facing away from the array substrate 1, and the second tip is the end of the support structure 23 facing away from the array substrate 1. This reduces the risk of the first partition structure 61, added to the winding region 100C, lifting the mask when the support structure 23 supports the mask. In one example, the distance from the first tip T1 of the first partition structure 61 to the substrate 11 is less than the distance from the second tip of the support structure 23 to the substrate 11.

[0049] In some embodiments, please refer to Figure 3 The display panel 100 also has an encapsulation region 100D, located between the winding region 100C and the opening region 100B. The display panel 100 also has an opening 7 located in the encapsulation region 100D, penetrating the pixel definition layer 2 and the organic insulating layer 142, and exposing the inorganic insulating layer 141. A thin-film encapsulation layer 4 is located in the encapsulation region 100D to encapsulate it. Thus, by removing the pixel definition layer 2 and the organic insulating layer 142 from the encapsulation region 100D, and encapsulating the encapsulation region 100D with the thin-film encapsulation layer 4 in conjunction with the inorganic insulating layer 141, the risk of external contaminants such as moisture penetrating into the display region 100A through the pixel definition layer 2 and the organic insulating layer 142 of the encapsulation region 100D is reduced.

[0050] In some embodiments, please refer to Figure 3The display panel 100 also includes a second partition structure 62, which is located within the opening 7 and on the inorganic insulating layer 141, and partitions the light-emitting common layer 33. In this way, the light-emitting common layer 33 is also partitioned within the encapsulation region 100D, further reducing the risk of external contaminants such as moisture penetrating into the display region 100A through the light-emitting common layer 33 of the encapsulation region 100D.

[0051] In some embodiments, please refer to Figure 3 and Figure 4 The light-emitting common layer 33 includes a cathode layer 331 and a common organic layer 332, with the common organic layer 332 located between the cathode layer 331 and the pixel definition layer 2. The second isolation structure 62 separates the cathode layer 331 and the common organic layer 332. Thus, by separating the cathode layer 331 and the common organic layer 332, and particularly the common organic layer 332, the second isolation structure 62 reduces the risk of external contaminants such as moisture penetrating into the display area 100A through the common organic layer 332.

[0052] In some embodiments, please refer to Figure 3 The encapsulation region 100D includes a first encapsulation region 100D1 and a second encapsulation region 100D2. The display panel 100 also includes a barrier structure 81, which is located between the first encapsulation region 100D1 and the second encapsulation region 100D2 and is located on the array substrate 1. The second encapsulation region 100D2 is located between the barrier structure 81 and the opening region 100B. The barrier structure 81 is used to block the organic encapsulation layer 42, thereby confining the organic encapsulation layer 42 within the first encapsulation region 100D1 and on the side of the first encapsulation region 100D1 closest to the display region 100A, reducing the risk of the organic encapsulation layer 42 overflowing into the second encapsulation region 100D2, and reducing the risk of external contaminants such as moisture gradually penetrating into the display region 100A through the organic encapsulation layer 42. The first inorganic encapsulation layer 41 and the second inorganic encapsulation layer are located in the first encapsulation area 100D1 and the second encapsulation area 100D2, so that the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer can encapsulate the first encapsulation area 100D1 and the second encapsulation area 100D2, thereby reducing the risk of external pollutants such as water vapor reaching the display area 100A through the opening area 100B.

[0053] In some embodiments, the blocking structure 81 may include at least one of a portion of the pixel definition layer 2 and a portion of the organic insulating layer 142 to increase the height of the blocking structure 81 and ensure the blocking effect of the blocking structure 81. In one example, the blocking structure 81 includes a first portion of the organic insulating layer 142 and a first portion of the pixel definition layer 2, with the first portion of the pixel definition layer 2 stacked on top of the first portion of the organic insulating layer 142.

[0054] In some embodiments, please refer to Figure 3The number of second partition structures 62 provided in the second encapsulation region 100D2 is greater than the number of second partition structures 62 provided in the first encapsulation region 100D1. In this way, the number of second partition structures 62 provided in the second encapsulation region 100D2 is greater, which improves the overall isolation effect of the multiple second partition structures 62 provided in the second encapsulation region 100D2 on the light-emitting common layer 33.

[0055] In some embodiments, please refer to Figure 3 In the first encapsulation region 100D1, no organic insulating layer 142 is provided between adjacent second partition structures 62. In this way, based on the use of the first partition structure 61 to isolate the cathode layer 331, the organic insulating layer 142 between adjacent second partition structures 62 in the first encapsulation region 100D1 can be removed, simplifying the patterning process of the organic insulating layer 142.

[0056] In some embodiments, please refer to Figure 3 The second partition structure 62 may include a first conductive portion 621 and a second conductive portion 622 stacked together, with the first conductive portion 621 recessed relative to the second conductive portion 622. Thus, the second partition structure 62, utilizing the recessed relationship between the first conductive portion 621 and the second conductive portion 622, can effectively isolate the light-emitting common layer 33, particularly the common organic layer 332. In some embodiments, the thickness of the first conductive portion 621 may be greater than the thickness of the second conductive portion 622 to improve the isolation effect on the light-emitting common layer 33 when the first conductive portion 621 is recessed relative to the second conductive portion 622. The recession of the first conductive portion 621 relative to the second conductive portion 622 can be formed by side etching.

[0057] In some embodiments, the second partition structure 62 may further include a third conductive portion 623, which is located between the first conductive portion 621 and the substrate 11. The material of the third conductive portion 623 is the same as that of the second conductive portion 622.

[0058] In some embodiments, a metal layer 130 may include a plurality of second partition structures 62, so as to form a plurality of second partition structures 62 using the metal layer 130 in the array substrate 1, avoiding the need to add a new film layer to form a plurality of second partition structures 62, and simplifying the manufacturing process of the display panel 100. In one example, the second metal layer 132 or the fourth metal layer 134 includes a plurality of second partition structures 62.

[0059] In some embodiments, please refer to Figure 3The display panel 100 also includes a crack-blocking structure 82, which is located on the array substrate 1 and on the side of the second partition structure 62 near the opening region 100B. The crack-blocking structure 82 extends to the inorganic insulating layer 141 to reduce the risk of crack propagation in the inorganic insulating layer 141. In some embodiments, the crack-blocking structure 82 may include a second portion of the pixel defining layer 2 and a second portion of the organic insulating layer 142, the second portion of the pixel defining layer 2 being located on the second portion of the organic insulating layer 142.

[0060] Please see Figure 5 to 6 This application provides a schematic diagram of the manufacturing method of the display panel 100 described above. The display panel 100 has a winding area 100C, and the manufacturing method of the display panel 100 includes the following steps: Step S101: Form an array substrate 1 and a pixel definition layer 2. The array substrate 1 includes multiple winding area wirings 122, which are located in the winding area 100C. The pixel definition layer 2 is located on the array substrate 1. Step S102: Form a first partition structure 61, the first partition structure 61 being located on the surface of the pixel definition layer 2 facing away from the array substrate 1 and located in the winding region 100C; and Step S103: Form a light-emitting common layer 33, and the first isolation structure 61 disconnects the light-emitting common layer 33 of the winding area 100C.

[0061] In some embodiments, such as Figure 5 As shown, forming the array substrate 1 in step S101 may include forming a metal layer 130, an inorganic insulating layer 141, and an organic insulating layer 142 on the substrate 11. The inorganic insulating layer 141 is located between the organic insulating layer 142 and the substrate 11. The metal layer 130 is located between the substrate 11 and the inorganic insulating layer 141, inside the inorganic insulating layer 141, inside the organic insulating layer 142, or between the inorganic insulating layer 141 and the organic insulating layer 142, or more of these locations.

[0062] In some embodiments, such as Figure 5 As shown, multiple wirings 122 are located in one or more metal layers 130. The display panel 100 also has an encapsulation region 100D, which is located on the side of the wiring region 100C opposite to the display area (not shown in the figure). A metal layer 130 may also include a second partition structure 62, which is located in the encapsulation region 100D. After the light-emitting common layer 33 is formed, the second partition structure 62 can also act as a barrier to the light-emitting common layer 33.

[0063] In some embodiments, forming the pixel definition layer 2 in step S101 may include: forming a positive photoresist layer covering the entire surface, exposing and developing the positive photoresist layer covering the entire surface to obtain the pixel definition layer 2.

[0064] In some embodiments, forming the first partition structure 61 in step S102 may include: forming a negative photoresist layer covering the entire surface, exposing and developing the negative photoresist layer covering the entire surface to obtain a plurality of first partition structures 61.

[0065] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0066] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0067] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0068] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel has an opening area, a winding area, and a display area, wherein the winding area is located between the opening area and the display area, and the display panel includes: An array substrate includes multiple winding area wirings; the multiple winding area wirings are located in the winding area and are disposed around at least a portion of the opening area; A pixel definition layer is located on one side of the array substrate and has pixel openings; A light-emitting common layer, at least a portion of which is located in the pixel opening and on the side of the pixel definition layer opposite to the array substrate; A first partition structure is located in the winding area and between the pixel definition layer and the light-emitting shared layer, and disconnects the light-emitting shared layer of the winding area; An opening is located in the opening area and extends at least through the array substrate, the pixel definition layer, and the light-emitting common layer along the stacking direction between the array substrate and the pixel definition layer.

2. The display panel according to claim 1, characterized in that, The first partition structure includes a bottom surface and a top surface disposed opposite to each other, the top surface being located on the side of the bottom surface away from the array substrate, and the area of ​​the bottom surface being smaller than the area of ​​the top surface.

3. The display panel according to claim 1, characterized in that, The first partition structure is arranged around the opening area.

4. The display panel according to claim 1, characterized in that, The material of the first partition structure is different from the material of the pixel definition layer.

5. The display panel according to claim 1 or 4, characterized in that, The first partition structure includes an insulating material, and the light-emitting common layer includes a cathode layer, with the first partition structure separating the cathode layer.

6. The display panel according to claim 1, characterized in that, The array substrate includes a substrate, and a plurality of the winding area wirings are located on the substrate; The pixel definition layer also includes a dam and a support structure, the dam being disposed around the pixel opening and the support structure being located on the surface of the dam facing away from the array substrate; Wherein, the distance from the first top end of the first partition structure to the substrate is less than or equal to the distance from the second top end of the support structure to the substrate, the first top end is the end of the first partition structure facing away from the array substrate, and the second top end is the end of the support structure facing away from the array substrate.

7. The display panel according to claim 1, characterized in that, The display panel also has an encapsulation area, which is located between the winding area and the opening area; The array substrate includes an organic insulating layer and an inorganic insulating layer, wherein the organic insulating layer is located between the inorganic insulating layer and the pixel definition layer; The display panel is also provided with an opening, which is located in the encapsulation area and penetrates the pixel definition layer and the organic insulating layer, and exposes the inorganic insulating layer; The display panel further includes a second partition structure located within the opening and on the inorganic insulating layer, which isolates the light-emitting common layer.

8. The display panel according to claim 7, characterized in that, The encapsulation area includes a first encapsulation area and a second encapsulation area; The display panel further includes a blocking structure, which is located between the first encapsulation area and the second encapsulation area and on the array substrate, and the second encapsulation area is located between the blocking structure and the opening area; The number of second partition structures provided in the second packaging area is greater than the number of second partition structures provided in the first packaging area.

9. The display panel according to claim 8, characterized in that, The organic insulating layer is not disposed between adjacent second partition structures in the first encapsulation area.

10. The display panel according to claim 7, characterized in that, The light-emitting common layer includes a cathode layer and a common organic layer, the common organic layer being located between the cathode layer and the pixel definition layer; the second isolation structure disconnects the cathode layer and the common organic layer.

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