Suspension type multi-chip silicon bridge direct connection structure and preparation method

Abstract

The invention provides a suspension type multi-chip silicon bridge direct connection structure and a preparation method thereof, and the structure comprises an organic substrate, the front surface of which is provided with a ball mounting window and a bump window; the back surface of the silicon bridge chip is connected with the salient point window of the organic substrate through a micro-boss and soldering tin cap structure, and the front surface of the silicon bridge chip is provided with a micro-boss for connecting a functional chip; the front surface of the functional chip is provided with a first salient point and a second salient point of a metal micro boss and a soldering tin cap, the size of the first salient point is smaller than that of the second salient point, the first salient point is connected with the micro boss on the front surface of the silicon bridge chip, and the second salient point is connected with the ball mounting window of the organic substrate. According to the invention, the surface of the silicon bridge chip can be effectively leveled, the electroplating non-uniformity is reduced, and the height consistency of the mixed salient points is ensured.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging silicon bridge technology, and in particular to a suspended multi-chip silicon bridge direct connection structure and its fabrication method. Background Technology

[0002] The development of integrated circuits is currently constrained by the "memory wall," "area wall," "power wall," and "functionality wall." When chip manufacturing processes are fixed, increasing the chip area allows for the integration of more transistors to improve performance. However, chip size is limited by the size of the photomask in lithography machines, and overcoming this limit is extremely costly. Currently, integrating multiple chips through advanced packaging technology is a low-cost solution to overcome the chip "area wall."

[0003] Achieving high-density integration of multiple chips requires smaller linewidths and spacings for inter-chip interconnects. Current chip packaging technologies often use leadframes or redistribution layers (RDLs) for inter-chip interconnects, but these suffer from low interconnect density and slow signal transmission rates, making them insufficient to meet the high-performance requirements of modern integrated circuits. For example, the maximum linewidth / spacing of existing RDLs is 2μm / 2μm, while silicon bridges can replace some of the interconnect functions of RDLs, thereby enabling high-density integration of multiple chips.

[0004] Existing silicon bridge technologies are mainly divided into three categories: the first category is to embed the silicon bridge chip into a traditional organic substrate (embedded silicon bridge); the second category is to embed the silicon bridge in epoxy resin material and then achieve local high-density packaging through key fan-out processes such as redistribution and microbumps (redistribution silicon bridge); the third category is to place the silicon bridge on the substrate and connect it directly to the functional chip, and there is no substrate or epoxy resin material covering the silicon bridge (suspended silicon bridge).

[0005] Currently, the technologies for embedded silicon bridges and redistribution silicon bridges are relatively mature, while the engineering development of suspended silicon bridges has been slower. However, theoretically, this technology still has potential advantages in reducing process costs and improving system flexibility. The slow development of suspended silicon bridge technology stems primarily from two key technical challenges: 1. Silicon Bridge Coplanarity Control: Due to the lack of protection from organic substrates or epoxy resin materials, the bumps on the front side of the silicon bridge cannot be planarized. Simultaneously, the lack of mechanical constraints between individual silicon bridge chips makes them susceptible to warping of the corresponding area of ​​the underlying substrate. The combination of these two factors results in poor coplanarity of the silicon bridge's front side, thus affecting the soldering reliability of functional chips.

[0006] 2. Process Compatibility of Hybrid Bump Structure Fabrication: In areas not connected to the silicon bridge chip, the functional chip, lacking an organic substrate or epoxy resin material as a transition layer, requires the fabrication of bumps with larger window sizes and higher heights to directly connect to the substrate. Conversely, in areas connected to the silicon bridge chip, bumps with smaller window sizes and lower heights are needed for connection. One feasible solution is to use two sets of electroplating masks on the functional chip side, one for large-size, high-copper pillar bumps with solder caps and the other for small-size, low-copper pillar bumps with solder caps. However, using two sets of electroplating masks not only increases costs but may also introduce variations in multi-step electroplating, making it a non-standard process for traditional packaging and testing workflows.

[0007] Therefore, choosing a reasonable design and fabrication scheme, improving the coplanarity of silicon bridges, enhancing the process compatibility of hybrid bump structure fabrication, and reducing the overall risk of substrate warping are key to promoting the development of suspended silicon bridge technology. Summary of the Invention

[0008] In view of this, the present invention provides a suspended multi-chip silicon bridge direct connection structure and fabrication method to solve at least one of the aforementioned problems.

[0009] To achieve the above objectives, the present invention adopts the following solution: According to a first aspect of the present invention, embodiments of the present invention provide a suspended multi-chip silicon bridge direct connection structure, comprising: An organic substrate with a ball-planting window and a raised dot window on its front side; At least one silicon bridge chip has its back side connected to the bump opening of the organic substrate via a micro-protrusion and solder cap structure, and its front side is provided with micro-protrusions for connecting functional chips. At least one functional chip has a first bump and a second bump with a metal micro-bump and solder cap on its front side. The size of the first bump is smaller than that of the second bump. The first bump is connected to the micro-bump on the front side of the silicon bridge chip, and the second bump is connected to the ball-mounting window of the organic substrate.

[0010] In one embodiment of this application, a metallization layer under the bump is deposited in both the ball-planting window and the bump window of the organic substrate.

[0011] In one embodiment of this application, the size of the above-mentioned ball-planting window is larger than that of the protrusion window.

[0012] In one embodiment of this application, the above-mentioned suspended multi-chip silicon bridge direct connection structure further includes an integrated passive device chip and / or an input / output interface chip. The back side of the integrated passive device chip and the input / output interface chip are connected to the bump opening of the organic substrate through a micro-protrusion and solder cap structure, and the front side is provided with a micro-protrusion for connecting the functional chip.

[0013] In one embodiment of this application, the above-mentioned suspended multi-chip silicon bridge direct connection structure further includes a high-bandwidth memory chip, which has a third bump on its front side that is connected to the micro-bump on the front side of the silicon bridge chip, and is interconnected with the functional chip through the silicon bridge chip.

[0014] In one embodiment of this application, the first bump and the second bump on the functional chip are formed by photolithography on the same photomask and by a single electroplating process.

[0015] According to a second aspect of the present invention, embodiments of the present invention provide a method for fabricating a suspended multi-chip silicon bridge direct connection structure, comprising: An organic substrate is provided, on the front side of which ball-planted windows and bump windows are formed using standard substrate processes; The ball-planting window position on the organic substrate is planted using standard substrate technology; At least one silicon bridge chip is mounted on the back side of a designated area on the front side of the organic substrate, such that the micro-bump and solder cap structure on the back side of the silicon bridge chip is connected to the bump opening of the organic substrate. The silicon bridge chip is annealed and pressure is applied to the front side using a customized annealing and leveling fixture to level the surface of the silicon bridge chip. Remove the annealing and leveling fixture, and then connect the front side of at least one functional chip to the front side of the silicon bridge chip and the ball-planting window area of ​​the organic substrate, wherein the first bump of the functional chip is connected to the micro-bump on the front side of the silicon bridge chip, and the second bump is connected to the ball-planting window of the organic substrate.

[0016] In one embodiment of this application, the step of mounting the silicon bridge chip onto the organic substrate further includes mounting the back side of the integrated passive device chip and / or input / output interface chip onto a designated area on the front side of the organic substrate, so that the micro-protrusion and solder cap structure on the back side of the integrated passive device chip and / or input / output interface chip is connected to the bump opening of the organic substrate.

[0017] In one embodiment of this application, the step of connecting the functional chip to the silicon bridge chip further includes connecting a third bump on the front side of the high-bandwidth memory chip to a micro-bump on the front side of the silicon bridge chip, so as to interconnect the functional chip through the silicon bridge chip.

[0018] In one embodiment of this application, the step of annealing and applying pressure to the front side of the silicon bridge chip described above further includes simultaneously annealing and applying pressure to the front side of the integrated passive device chip and / or the input / output interface chip.

[0019] In one embodiment of this application, the first bump and the second bump on the functional chip are formed by photolithography on the same photomask and by a single electroplating process.

[0020] In one embodiment of this application, during the annealing and pressure application step described above, the solder on the back of the silicon bridge chip is subjected to creep at high temperature, thereby smoothing the surface of the silicon bridge chip.

[0021] In one embodiment of this application, after connecting the functional chip, the step of encapsulating and protecting the entire structure with a molding bottom filler is further included.

[0022] In one embodiment of this application, after the above method forms ball-mounted windows and bump windows on the front side of the organic substrate using a standard substrate process, it further includes: depositing a bump undermetallization layer on the ball-mounted windows and the bump windows.

[0023] The suspended multi-chip silicon bridge direct connection structure and fabrication method proposed in this invention address the problem of poor coplanarity caused by the lack of organic substrate or resin material protection in suspended silicon bridges. This invention uses a customized annealing and leveling fixture to anneal and pressurize the front side of the silicon bridge chip, causing the solder on the back side of the chip to creep at high temperature, thereby effectively leveling the surface of the silicon bridge chip and improving the soldering reliability of subsequent functional chips. To solve the process compatibility problem in the fabrication of hybrid bump structures on functional chips, this invention utilizes a standard substrate ball-mounting process to compensate for the height required for direct connection bumps between the functional chip and the substrate. It also uses the same photomask to photolithographically form windows of two sizes on the functional chip, controlling the total electroplating height to within 10µm, reducing electroplating inhomogeneity, ensuring the height consistency of the hybrid bumps, and contributing to improved soldering reliability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This application provides a method for fabricating a suspended multi-chip silicon bridge direct connection structure. Figure 2 This is a schematic diagram of an organic substrate with windows of different sizes provided in the embodiments of this application; Figure 3 This is a schematic diagram of an organic substrate after laser ball implantation, provided in an embodiment of this application. Figure 4 This is a schematic diagram of the silicon bridge chip provided in an embodiment of this application; Figure 5 This is a schematic diagram of the system after the silicon bridge chip is mounted according to an embodiment of this application; Figure 6 This is a schematic diagram of the process of leveling mounted chips using a customized annealing and leveling fixture, provided in an embodiment of this application. Figure 7 This is a schematic diagram of a functional chip provided in an embodiment of this application; Figure 8 This is a schematic diagram of the system after the functional chip is mounted according to the embodiments of this application; Figure 9 This is a schematic diagram of an organic substrate with windows of different sizes provided in another embodiment of this application; Figure 10 This is a schematic diagram of an organic substrate after ball implantation, provided in another embodiment of this application; Figure 11 This is a schematic diagram of a silicon bridge chip, an IPD chip, and an I / O interface chip provided in another embodiment of this application; Figure 12 This is a schematic diagram of a chip-mounted system according to another embodiment of this application; Figure 13 This is a schematic diagram of a process for leveling mounted chips using a customized annealing and leveling fixture, provided in another embodiment of this application. Figure 14 This is a schematic diagram of an HBM chip and a functional chip provided in another embodiment of this application; Figure 15 This is a schematic diagram of a system after the HBM chip and functional chip are mounted, according to another embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0026] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0027] Furthermore, it should be noted that the use of terms such as "first" and "second" to define related concepts is merely for the purpose of distinguishing the corresponding concepts. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0028] like Figure 1 The diagram illustrates a method for fabricating a suspended multi-chip silicon bridge direct-connect structure according to an embodiment of this application. The method includes the following steps: Step S101: Provide an organic substrate, and form ball-mounted windows and bump windows on the front side of the organic substrate using standard substrate processing.

[0029] First, an organic substrate is provided, and two different sized openings are fabricated on its front side using standard substrate manufacturing processes: a larger ball-mounted opening and a smaller bump opening. For example, the diameter of the ball-mounted opening can be set to 100µm, while the diameter of the bump opening can be set to 60µm. Preferably, both types of openings have an under-bump metallization (UBM) layer deposited within them. The UBM layer promotes solder wetting during subsequent soldering, ensuring reliable connections.

[0030] Step S102: Ball placement is performed at the ball placement window position of the organic substrate using standard substrate technology.

[0031] On the organic substrate with windows created, for larger solder balls, a solder ball placement technique is used to place them. For example, solder balls with a diameter of 150µm can be implanted. This step provides connection points for the large bumps of subsequent functional chips.

[0032] Step S103: Attach the back side of at least one silicon bridge chip to a designated area on the front side of the organic substrate, so that the micro-bump and solder cap structure on the back side of the silicon bridge chip is connected to the bump opening of the organic substrate.

[0033] A pre-fabricated silicon bridge chip, approximately 100µm thick, is provided. Its front side has micro-protrusions for connecting functional chips, while its back side has micro-protrusion structures with solder caps. Then, using high-precision thermo-press bonding (TCB) technology, the back side of the silicon bridge chip is precisely mounted onto a designated area on the front side of an organic substrate, aligning the micro-protrusions and solder caps on the back side with the bump openings on the organic substrate and completing the bonding process.

[0034] Step S104: Anneal and apply pressure to the front side of the silicon bridge chip using a customized annealing and leveling fixture to level the surface of the silicon bridge chip.

[0035] After the silicon bridge chips are mounted onto the substrate, a customized annealing and leveling fixture is used to apply pressure to the front side of all mounted silicon bridge chips and perform high-temperature annealing. Under the combined action of high temperature and pressure, the solder on the solder caps on the back of the silicon bridge chips will creep. This slight plastic deformation can compensate for the problem of uneven height of silicon bridge chips caused by substrate warping and other factors, thereby making the front side of all silicon bridge chips reach a flat and coplanar state.

[0036] Step S105: Remove the annealing and leveling fixture, and then connect the front side of at least one functional chip to the front side of the silicon bridge chip and the ball-planting window area of ​​the organic substrate, wherein the first bump of the functional chip is connected to the micro-bump on the front side of the silicon bridge chip, and the second bump is connected to the ball-planting window of the organic substrate.

[0037] First, the annealing and leveling fixture is removed. Then, a pre-fabricated functional chip is provided. This chip has two different sized bumps on its front side: a small bump (first bump) corresponding to the micro-bumps of the silicon bridge chip, and a large bump (second bump) corresponding to the ball placement windows on the organic substrate. Finally, high-precision thermosetting bonding technology is used again to mount the front side of the functional chip onto the leveled silicon bridge chip and the organic substrate. Through this process, the small bumps of the functional chip connect with the micro-bumps of the silicon bridge chip, achieving high-density interconnection between chips; simultaneously, its large bumps connect with the ball placement on the organic substrate, completing direct connection with the organic substrate.

[0038] In one embodiment of this application, the above method further includes the step of mounting the back side of the integrated passive device chip and / or input / output interface chip to a designated area on the front side of the organic substrate, so that the micro-boob with solder cap structure on the back side of the integrated passive device (IPD) chip and / or input / output (I / O) interface chip is connected to the bump opening of the organic substrate.

[0039] In other words, in addition to providing silicon bridge chips, this application can also provide IPD chips and I / O interface chips. These chips have a similar structure to the aforementioned silicon bridge chips, with micro-protrusion structures with solder caps processed on their back sides for connection to the organic substrate, and micro-protrusions for connecting functional chips on their front sides.

[0040] In this embodiment, high-precision thermocompression bonding (TCB) technology can be used to mount the back sides of the silicon bridge chip, IPD chip, and I / O interface chip onto the corresponding designated areas on the front side of the organic substrate in a single process. During this process, the micro-protrusions with solder caps on the back sides of these chips are aligned with the bump openings on the organic substrate and soldered together, achieving electrical and mechanical connections between the chips and the organic substrate. This step allows the IPD chip and I / O interface chip to be integrated into the system, thereby improving the system's functionality, flexibility, and scalability.

[0041] In another embodiment of this application, the step S104 of annealing and pressurizing the front side of the silicon bridge chip further includes simultaneously annealing and pressurizing the front side of the integrated passive device chip and / or the input / output interface chip.

[0042] In this embodiment, a customized annealing and leveling fixture can be used to simultaneously anneal and apply pressure to the front side of all chips that have been mounted on the organic substrate, including silicon bridge chips, IPD chips, and I / O interface chips.

[0043] The purpose of this operation is to allow the solder on the back of these different types of chips to creep at high temperatures, thereby uniformly flattening the surface of all chips and ensuring that they have good coplanarity, thus preparing for the subsequent uniform mounting of functional chips and HBM chips.

[0044] In another embodiment of this application, the step S105 of connecting the functional chip to the silicon bridge chip further includes connecting a third bump on the front side of the high bandwidth memory (HBM) chip to a micro-bump on the front side of the silicon bridge chip, so as to interconnect the functional chip through the silicon bridge chip.

[0045] In this embodiment, in addition to providing the functional chip, an HBM chip is also provided. The front side of the HBM chip is processed with small-sized microbumps (third bumps), and the structure consists of metal micro-boobs with solder caps. After removing the annealing and leveling fixture, high-precision thermosetting bonding technology is used to mount the front sides of the functional chip and the HBM chip onto the micro-boobs on the front side of the leveled silicon bridge chip, IPD chip, I / O interface chip, and the ball-planting area of ​​the organic substrate in one step.

[0046] In this process, small bumps on the front of the HBM chip connect to micro-bumps on the front of a specific silicon bridge chip below. This allows the HBM chip to achieve high-density interconnection with functional chips via the silicon bridge chip, providing more memory space for the entire system and enabling functional expansion.

[0047] In another embodiment of this application, the first bump and the second bump on the above-mentioned functional chip are formed by photolithography on the same photomask and by a single electroplating process.

[0048] In the embodiments of this application, the small-sized bump (first bump) and the large-sized bump (second bump) on the functional chip are formed by photolithography using the same photomask and a single electroplating process. This aims to solve the problem of increased cost and potential variation risks associated with using two sets of electroplating photomasks. However, electroplating bumps of two different window sizes in a single photomask reduces height uniformity. Therefore, in this embodiment, the target electroplating height is controlled within 10 μm during electroplating to minimize height differences as much as possible.

[0049] In a suspended multi-chip silicon bridge direct-connect structure, the functional chip needs to be connected to both the silicon bridge chip and the organic substrate simultaneously. Therefore, two different sized windows need to be formed on the front side of the functional chip: a small window corresponds to the micro-protrusions of the silicon bridge chip for high-density interconnection; a large window corresponds to the ball-mounted window on the organic substrate for direct connection to the substrate. Existing hybrid bump fabrication methods utilize two sets of photomasks to electroplate large-sized high-copper pillar bumps + solder cap bumps and small-sized low-copper pillar bumps + solder cap bumps on the functional chip side. This method increases mask costs and may introduce variations in multi-step electroplating, making it a non-standard process for traditional packaging and testing plants. Therefore, in this application, the height of the large-sized window bumps is compensated for using a standard substrate ball-mounting process in the embodiments of this application. Furthermore, this application uses the same photomask for photolithography on the front side of the functional chip, ensuring precise correspondence of the window positions: the small-sized window matches the position of the micro-protrusions on the front side of the silicon bridge chip, and the large-sized window matches the position of the ball-mounted window on the organic substrate. Following photolithography, the corresponding micro-boobs and solder cap structures are formed in a single process using standard electroplating. This entire process is a single step, simultaneously creating both types of bumps and avoiding variations that might be introduced by multiple electroplating steps. At the same time, by controlling the target height of the electroplating within a certain range, two bump structures of similar height—large and small—are formed, ensuring that the bump uniformity remains within a feasible soldering range.

[0050] In one embodiment of this application, after connecting the functional chip, the above method further includes a step of encapsulating and protecting the entire structure with a molding bottom filler.

[0051] This step follows the thermocompression bonding of the functional chips (or HBM chips and functional chips). At this point, the system has completed its electrical and mechanical interconnection, but still needs protection against external damage, moisture, or thermal stress. A molding underfill is used to fill and cover the entire bottom and sides of the structure. This material typically has good flowability and curing properties, filling the chip gaps and providing underfill support and insulation.

[0052] Corresponding to the above-described method for fabricating a suspended multi-chip silicon bridge direct connection structure, another embodiment of this application provides a suspended multi-chip silicon bridge direct connection structure, comprising: An organic substrate with a ball-planting window and a raised dot window on its front side; At least one silicon bridge chip has its back side connected to the bump opening of the organic substrate via a micro-protrusion and solder cap structure, and its front side is provided with micro-protrusions for connecting functional chips. At least one functional chip has a first bump and a second bump with a metal micro-bump and solder cap on its front side. The size of the first bump is smaller than that of the second bump. The first bump is connected to the micro-bump on the front side of the silicon bridge chip, and the second bump is connected to the ball-mounting window of the organic substrate.

[0053] In one embodiment of this application, a metallization layer under the bump is deposited in both the ball-planting window and the bump window of the organic substrate.

[0054] In one embodiment of this application, the size of the above-mentioned ball-planting window is larger than that of the protrusion window.

[0055] In one embodiment of this application, the above-mentioned suspended multi-chip silicon bridge direct connection structure further includes an integrated passive device chip and / or an input / output interface chip. The back side of the integrated passive device chip and the input / output interface chip are connected to the bump opening of the organic substrate through a micro-protrusion and solder cap structure, and the front side is provided with a micro-protrusion for connecting the functional chip.

[0056] In one embodiment of this application, the above-mentioned suspended multi-chip silicon bridge direct connection structure further includes a high-bandwidth memory chip, which has a third bump on its front side that is connected to the micro-bump on the front side of the silicon bridge chip, and is interconnected with the functional chip through the silicon bridge chip.

[0057] In one embodiment of this application, the first bump and the second bump on the functional chip are formed by photolithography on the same photomask and by a single electroplating process.

[0058] The following two specific embodiments will further illustrate the suspended multi-chip silicon bridge direct connection structure and its fabrication method of this application.

[0059] Example 1: Step 1: As Figure 2 As shown, an organic substrate 101 is provided, where (a) is a top view of the organic substrate 101 and (b) is a side view. The front side of the organic substrate 101 is formed with ball-mounted windows 102 and bump windows 103 using standard substrate processing. The diameter of the ball-mounted windows 102 is 100 μm, and the diameter of the bump windows 103 is 60 μm. UBM is deposited within the windows for soldering.

[0060] Step 2: Laser-assisted ball implantation 104 is performed at the location of the ball implantation window 102 on the organic substrate. The diameter of the implanted balls is 150μm. The organic substrate after laser ball implantation is as follows. Figure 3 As shown.

[0061] Step 3: As Figure 4 As shown, several silicon bridge chips 105 are provided, with two in this example. The silicon bridge chip 105 is approximately 100μm thick, with a metal micro-protrusion 106 with a 20μm opening and a height of 6μm processed on the front side, and a metal micro-protrusion + solder cap structure 107 with a 60μm opening and a height of 10μm processed on the back side.

[0062] Step 4: Using high-precision thermo-press bonding technology, the back side of the silicon bridge chip 105 is mounted to a designated area on the front side of the organic substrate 101. Specifically, the metal micro-protrusions + solder cap structure 107 on the back side of the silicon bridge chip 105 is correspondingly bonded to the bump openings 103 on the front side of the organic substrate 101. Figure 5 As shown.

[0063] Step 5: Annealing and applying pressure to the front side of the silicon bridge chip 105 using a customized annealing and leveling fixture 110 causes the solder on the back side of the chip to creep at high temperature, gradually leveling the surface of the silicon bridge chip. This step is as follows: Figure 6 As shown, it is a schematic diagram (side view) of the system after the silicon bridge chip is mounted.

[0064] Step Six: As Figure 7 As shown, several functional chips 107 are provided, with three shown in the illustration. The front side of each functional chip 107 has small-sized bumps 108 and large-sized bumps 109. The small-sized bump 108 has a window diameter of 20 μm and a height of 10 μm, and its structure is a metal micro-boob + solder cap. The large-sized bump 109 has a window diameter of 100 μm and a height of 10 μm, and its structure is also a metal micro-boob + solder cap. The small-sized bumps 108 of the functional chip 107 correspond to the window positions of the metal micro-boobs 106 of the silicon bridge chip 105 below. The large-sized bumps 109 of the functional chip 107 correspond to the positions of the ball-mounting windows 102 on the substrate. The small-sized bumps 108 and large-sized bumps 109 on the front side of the functional chip 107 are formed simultaneously using a standard electroplating process.

[0065] Step 7: Remove the annealing and leveling fixture 110, and use high-precision hot-pressing technology to connect the front side of the functional chip to the front side of the silicon bridge chip and the designated area for ball placement on the organic substrate, such as... Figure 8 The diagram shows a system after the functional chips are mounted, where (a) is a top view and (b) is a side view.

[0066] Step 8: Encapsulate and protect the entire system using molded bottom filler.

[0067] Example 2: Step 1: As Figure 9As shown, an organic substrate 201 is provided. The front side of the organic substrate 201 is formed with a ball-mounted window 202 and a bump window 203 using a standard substrate process. The diameter of the ball-mounted window 202 is 100 μm, and the diameter of the bump window 203 is 60 μm. UBM is deposited in the windows for soldering.

[0068] Step 2: Laser-assisted ball implantation is performed at the location of the ball implantation window 202 on the organic substrate 201. The diameter of the implanted balls is 150μm. A schematic diagram of the organic substrate after ball implantation is shown below. Figure 10 As shown.

[0069] Step 3: Provide a first silicon bridge chip 205, a second silicon bridge chip 206, an IPD chip 207, and an I / O interface chip 208. The front side of the first silicon bridge chip 205 is used to connect the functional chip and the HBM chip, while the front side of the second silicon bridge chip 206 is used to connect two functional chips. These chips are approximately 100μm thick. The front side has a 20μm windowed metal micro-protrusion 209 with a height of 6μm, and the back side has a 60μm windowed metal micro-protrusion + solder cap structure 210 with a height of 10μm. The specific structure is as follows... Figure 11 As shown.

[0070] Step 4: Using high-precision thermosetting bonding technology, the back side of the first silicon bridge chip 205, the second silicon bridge chip 206, the IPD chip 207, and the I / O interface chip 208 are mounted onto the designated area on the front side of the organic substrate. A schematic diagram of the system after chip mounting is shown below. Figure 12 As shown.

[0071] Step 5: Using a customized annealing and leveling fixture 211, annealing pressure is applied to the front surfaces of the first silicon bridge chip 205, the second silicon bridge chip 206, the IPD chip 207, and the I / O interface chip 208. This causes the solder on the back of the chips to creep at high temperatures, gradually leveling the surface of the silicon bridge chips. Specifically, as shown below... Figure 13 As shown, (a) is the front view and (b) is the side view.

[0072] Step Six: As Figure 14As shown, an HBM chip 212 and a functional chip 213 are provided, where (a) is the HBM chip 212 and (b) is the functional chip 213. The HBM chip 212 has small-sized bumps 214 processed on its front side. The small-sized bump 214 has a window diameter of 20 μm and a height of 10 μm, and its structure is a metal micro-boob + solder cap. The functional chip 213 has small-sized bumps 214 and large-sized bumps 215 processed on its front side. The large-sized bump 215 on the front side of the functional chip 213 has a window diameter of 100 μm and a height of 10 μm, and its structure is a metal micro-boob + solder cap. It should be noted that the small-sized bumps 214 and large-sized bumps 215 on the front side of the functional chip 213 are formed simultaneously in a single process. The small bumps 214 of HBM chip 212 and functional chip 213 correspond to the positions of the metal micro-bumps 209 on the front of the first silicon bridge chip 205, the second silicon bridge chip 206, the IPD chip 207, and the I / O interface chip 208 below. The large bumps 215 of functional chip 213 correspond to the positions of the ball-mounting windows 202 on the organic substrate 201.

[0073] Step 7: Remove the annealing and leveling fixture, and use high-precision hot-pressing technology to connect the front side of the HBM chip and the functional chip to the front side of the silicon bridge chip and the designated area for ball placement on the organic substrate, such as... Figure 15 As shown.

[0074] Step 8: Encapsulate and protect the entire system using molded bottom filler.

[0075] As described above, the suspended multi-chip silicon bridge direct connection structure and fabrication method proposed in this invention address the problem of poor coplanarity caused by the lack of organic substrate or resin material protection in suspended silicon bridges. This invention uses a customized annealing and leveling fixture to anneal and pressurize the front side of the silicon bridge chip, causing the solder on the back side of the chip to creep at high temperature, thereby effectively leveling the surface of the silicon bridge chip and improving the soldering reliability of subsequent functional chips. To solve the process compatibility problem in the fabrication of hybrid bump structures on functional chips, this invention utilizes a standard substrate ball-mounting process to compensate for the required height of the bumps, and uses the same photomask to form windows of two sizes (large and small), controlling the total electroplating height within 10µm, reducing electroplating inhomogeneity, ensuring the height consistency of the hybrid bumps, and contributing to improved soldering reliability.

[0076] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A suspended multi-chip silicon bridge direct connection structure, characterized in that, include An organic substrate with a ball-planting window and a raised dot window on its front side; At least one silicon bridge chip has its back side connected to the bump opening of the organic substrate via a micro-protrusion and solder cap structure, and its front side is provided with micro-protrusions for connecting functional chips. At least one functional chip has a first bump and a second bump with a metal micro-bump and solder cap on its front side. The size of the first bump is smaller than that of the second bump. The first bump is connected to the micro-bump on the front side of the silicon bridge chip, and the second bump is connected to the ball-mounting window of the organic substrate.

2. The suspended multi-chip silicon bridge direct connection structure as described in claim 1, characterized in that, The organic substrate has a metallization layer deposited under the bumps in both the ball-planting windows and the bump windows.

3. The suspended multi-chip silicon bridge direct connection structure as described in claim 1, characterized in that, The size of the ball-planting window is larger than that of the protruding point window.

4. The suspended multi-chip silicon bridge direct connection structure as described in claim 1, characterized in that, It also includes an integrated passive device chip and / or an input / output interface chip. The back side of the integrated passive device chip and the input / output interface chip are connected to the bump opening of the organic substrate through a micro-boob and solder cap structure, and the front side is provided with a micro-boob for connecting the functional chip.

5. The suspended multi-chip silicon bridge direct connection structure as described in claim 1 or 4, characterized in that, It also includes a high-bandwidth memory chip, which has a third bump on its front side that connects to the micro-bumps on the front side of the silicon bridge chip, and is interconnected with the functional chip through the silicon bridge chip.

6. The suspended multi-chip silicon bridge direct connection structure as described in claim 1, characterized in that, The first and second bumps on the functional chip are formed by photolithography using the same photomask and a single electroplating process.

7. A method for fabricating a suspended multi-chip silicon bridge direct-connection structure, characterized in that, include: An organic substrate is provided, on the front side of which ball-planted windows and bump windows are formed using standard substrate processes; The ball-planting window position on the organic substrate is planted using standard substrate technology; At least one silicon bridge chip is mounted on the back side of a designated area on the front side of the organic substrate, such that the micro-bump and solder cap structure on the back side of the silicon bridge chip is connected to the bump opening of the organic substrate. The silicon bridge chip is annealed and pressure is applied to the front side using a customized annealing and leveling fixture to level the surface of the silicon bridge chip. Remove the annealing and leveling fixture, and then connect the front side of at least one functional chip to the front side of the silicon bridge chip and the ball-planting window area of ​​the organic substrate, wherein the first bump of the functional chip is connected to the micro-bump on the front side of the silicon bridge chip, and the second bump is connected to the ball-planting window of the organic substrate.

8. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 7, characterized in that, The step of mounting the silicon bridge chip onto the organic substrate further includes mounting the back side of the integrated passive device chip and / or input / output interface chip onto a designated area on the front side of the organic substrate, so that the micro-protrusion and solder cap structure on the back side of the integrated passive device chip and / or input / output interface chip is connected to the bump opening of the organic substrate.

9. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 7 or 8, characterized in that, The step of connecting the functional chip to the silicon bridge chip further includes connecting a third bump on the front side of the high-bandwidth memory chip to a micro-bump on the front side of the silicon bridge chip, so as to interconnect the functional chip through the silicon bridge chip.

10. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 8, characterized in that, The step of annealing and applying pressure to the front side of the silicon bridge chip also includes simultaneously annealing and applying pressure to the front side of the integrated passive device chip and / or the input / output interface chip.

11. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 7, characterized in that, The first and second bumps on the functional chip are formed by photolithography using the same photomask and a single electroplating process.

12. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 7, characterized in that, In the annealing and pressure application step, the solder on the back of the silicon bridge chip is caused to creep by high temperature, thereby flattening the surface of the silicon bridge chip.

13. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 7, characterized in that, After the functional chips are connected, the process also includes encapsulating and protecting the entire structure with a molded underfill material.

14. The method for fabricating the suspended multi-chip silicon bridge direct connection structure as described in claim 7, characterized in that, After forming ball-mounted windows and bump windows on the front side of the organic substrate using standard substrate processes, the method further includes depositing a bump undermetallization layer on the ball-mounted windows and the bump windows.

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