High-frequency chip heterogeneous integrated circuit and preparation method thereof

Abstract

The invention provides a high-frequency chip heterogeneous integrated circuit and a preparation method thereof, and relates to the technical field of semiconductors. The high-frequency chip heterogeneous integrated circuit comprises a plurality of chips, a porous conductor and a substrate, the plurality of chips have at least two types; and the plurality of chips are connected to the bonding pad of the substrate through the porous conductor in a planar interconnection form. According to the invention, each chip is connected to the substrate in a planar interconnection mode, but the problem of thermal mismatch exists when different types of chips are integrated on the same substrate in this way is solved, in order to solve the problem, a porous conductor is arranged between the chip and the substrate, and the flexible difference of different materials is offset by using the loose pore structure of the porous conductor, so that the chip is more flexible. And the thermal stress is dispersed, so that the reliability risk caused by thermal mismatch is relieved. Therefore, according to the embodiment of the invention, through a combination mode of planar interconnection and the porous conductor, the signal transmission quality under high integration level can be ensured on the basis of improving the system integration density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-frequency chip heterogeneous integrated circuit and its fabrication method. Background Technology

[0002] As mobile communication and radar technologies move towards higher frequencies, the demand for signal bandwidth and processing capabilities in high-frequency circuits continues to increase in order to improve the overall performance of the entire high-frequency system and meet the stringent application requirements in high-frequency scenarios.

[0003] Currently, the implementation and integration of high-frequency circuits mainly rely on two technical routes: one is a single semiconductor process chip solution, which uses a single type of semiconductor material such as gallium arsenide high electron mobility transistor (HEMT), gallium nitride high electron mobility transistor, gallium arsenide Schottky barrier diode (SBD) and corresponding device structure to fabricate chips, thereby realizing various high-frequency circuit functions; the other is the traditional system-in-package (SIP) technology, which integrates circuit chips with different functions and processes in the vertical direction by stacking them, combining the advantages of various chips to improve system performance. However, the inventors discovered that both methods have drawbacks. Specifically, for single-semiconductor process chips, their performance is limited by the intrinsic properties of semiconductor materials, resulting in inherent limitations. For example, while GaAs-based devices can achieve high gain and low noise, their output power is limited, while GaN-based devices excel at high output power but struggle to achieve high gain, failing to meet the demand for multiple performance indicators in high-frequency circuits. For traditional SIP technology, its vertically stacked interconnect structure generates significant parasitic effects such as parasitic inductance and capacitance in high-frequency scenarios, leading to problems such as signal reflection, power attenuation, and phase distortion, resulting in degraded signal transmission performance and making it unsuitable for the integration requirements of high-frequency circuits. Summary of the Invention

[0004] This invention provides a high-frequency chip heterogeneous integrated circuit and its fabrication method to solve the problem that traditional technical routes cannot support the core requirements of high performance and high integration of high-frequency circuits at the same time.

[0005] In a first aspect, embodiments of the present invention provide a high-frequency chip heterogeneous integrated circuit, comprising: multiple chips, a porous conductor, and a substrate; the multiple chips are of at least two types; Multiple chips are interconnected in a planar manner, connected to the substrate pads via porous conductors.

[0006] In one possible implementation, the structure of the porous conductor is determined based on the thermal and electrical properties of the chip to which it is connected.

[0007] In one possible implementation, planar interconnect forms include inverted interconnect forms or beam-type lead wire interconnect forms; Accordingly, multiple chips are connected to the substrate pads via flip-chip interconnects; Alternatively, multiple chips can be interconnected with pads on the substrate via beam-type leads.

[0008] In one possible implementation, the substrate is made of an insulating or semi-insulating material.

[0009] In one possible implementation, the substrate also includes transmission lines, matching structures, interconnects, and passive devices; Transmission lines are used to connect the pads of multiple chips to the matching structure; the matching structure is used to perform impedance matching on multiple chips. Interconnects are used to connect transmission lines, matching structures, and passive components.

[0010] In one possible implementation, the high-frequency chip heterogeneous integrated circuit is an amplifier circuit, and the multiple chips include a first HEMT chip and a second HEMT chip. The substrate also includes a first DC blocking capacitor, a second DC blocking capacitor, a third DC blocking capacitor, a first matching circuit, a second matching circuit, a third matching circuit, a fourth matching circuit, a first drain bias circuit, a second drain bias circuit, a first gate bias circuit, a second gate bias circuit, a first bypass capacitor, a second bypass capacitor, a third bypass capacitor, and a fourth bypass capacitor. The first end of the first DC blocking capacitor is connected to the input port, and the second end is connected to the emitter of the first HEMT chip through the first matching circuit; The emitter of the first HEMT chip is also connected to the first gate bias circuit and the first terminal of the first bypass capacitor, respectively. Its collector is connected to the first terminal of the second matching circuit, the first drain bias circuit and the first terminal of the second bypass capacitor, respectively. Its base is grounded. The second terminal of the first bypass capacitor and the second terminal of the second bypass capacitor are respectively grounded; The second terminal of the second matching circuit is connected to the emitter of the second HEMT chip through the second DC blocking capacitor and the third matching circuit. The emitter of the second HEMT chip is also connected to the first terminal of the second gate bias circuit and the third bypass capacitor, respectively. Its collector is connected to the first terminal of the fourth matching circuit, the first terminal of the second drain bias circuit and the fourth bypass capacitor, respectively. Its base is grounded. The second terminal of the third bypass capacitor and the second terminal of the fourth bypass capacitor are respectively grounded; The second terminal of the fourth matching circuit is connected to the output port through the third DC blocking capacitor.

[0011] In one possible implementation, the high-frequency chip heterogeneous integrated circuit is a frequency multiplier circuit, and the multiple chips include a first diode chip, a second diode chip, a third diode chip, and a fourth diode chip. The substrate includes a filter and a frequency doubling matching circuit; The first end of the filter is connected to the input end, and the second end is connected to the frequency doubling matching circuit through the negative terminals of the second diode chip and the third diode chip, respectively, and then connected to the output end through the frequency doubling matching circuit. The positive terminal of the second diode chip is connected to the negative terminal of the first diode chip, and the positive terminal of the first diode chip is grounded. The positive terminal of the third diode chip is connected to the negative terminal of the fourth diode chip, and the positive terminal of the fourth diode chip is grounded.

[0012] In one possible implementation, the substrate includes an active region and a passive region; The chip is connected to the active circuit region of the substrate via a porous conductor.

[0013] In a second aspect, embodiments of the present invention provide a manufacturing method for fabricating a high-frequency chip heterogeneous integrated circuit as provided in the first aspect or any one of the first aspects, the method comprising: Apply flux to the pads on the substrate; The porous conductor is transferred to the flux on the pads, and the substrate is then heat-annealed. The chip is connected to the pads via a planar interconnect to achieve bonding between the chip and the substrate.

[0014] In a second aspect, embodiments of the present invention provide a manufacturing method for fabricating a high-frequency chip heterogeneous integrated circuit as provided in the first aspect or any one of the first aspects, the method comprising: A porous conductor is generated on the target pad of the substrate using an electroplating method; The chip is connected to a porous conductor via a planar interconnect to achieve bonding between the chip and the substrate; or, Using 3D printing, porous conductors are generated on the target pads of the substrate; The chip is connected to a porous conductor via a planar interconnect to achieve bonding between the chip and the substrate.

[0015] This invention provides a high-frequency chip heterogeneous integrated circuit and its fabrication method. The high-frequency chip heterogeneous integrated circuit includes multiple chips, porous conductors, and a substrate, wherein the multiple chips are of at least two types. Traditional vertical stacked interconnect structures suffer from parasitic inductance and capacitance. To avoid high-frequency signal reflection, attenuation, and distortion, and to ensure signal transmission quality under high integration density, this embodiment uses a planar interconnect to connect the chips to the substrate. However, integrating different types of chips onto the same substrate in this way leads to thermal mismatch. To solve this problem, this invention incorporates porous conductors between the chips and the substrate. The porous structure of these conductors offsets the expansion and contraction differences of different materials, disperses thermal stress, and thus mitigates the reliability risks caused by thermal mismatch. Therefore, this invention, through the combination of planar interconnect and porous conductors, can significantly shorten the interconnection path between the chips and the substrate circuit while increasing system integration density, reducing parasitic inductance and capacitance, avoiding high-frequency signal reflection, attenuation, and distortion, and ensuring signal transmission quality under high integration density. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a high-frequency chip heterogeneous integrated circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram showing the division of the active and passive regions in the substrate provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the porous conductor provided in an embodiment of the present invention; Figure 4 This is a structural diagram of the beam-lead structure diode transistor-level chip provided in the embodiment of the present invention; Figure 5 This is a structural diagram of the flip-chip diode transistor stage provided in the embodiment of the present invention; Figure 6 This is a structural diagram of the beam-lead structure transistor-level chip provided in the embodiment of the present invention; Figure 7 This is a structural diagram of the flip-chip transistor stage provided in the embodiment of the present invention; Figure 8 This is a schematic diagram of the amplifier circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the frequency multiplier circuit provided in an embodiment of the present invention; Figure 10 This is a flowchart illustrating the fabrication process of a high-frequency chip heterogeneous integrated circuit provided in an embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0018] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0019] The implementation of the present invention will be described in detail below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a high-frequency chip heterogeneous integrated circuit provided in an embodiment of the present invention. (Refer to...) Figure 1 The high-frequency chip heterogeneous integrated circuit includes: multiple chips 1, porous conductors 2 and substrate 3; wherein the multiple chips 1 are of at least two types.

[0020] Multiple chips 1 are interconnected in a planar manner and connected to the pads of the substrate 3 through porous conductors 2.

[0021] In this embodiment, traditional SIP technology, with its vertically stacked interconnect structure, generates significant parasitic inductance and capacitance in high-frequency scenarios, leading to problems such as signal reflection, power attenuation, and phase distortion. To address this issue, this embodiment employs a planar interconnect, connecting multiple chips 1 to pads on a substrate 3. This method avoids the generation of parasitic inductance or capacitance. The planar interconnect can be a flip-chip interconnect or a beam interconnect.

[0022] The selected chips are high-frequency chips with frequencies above 100 MHz. They can be crystal-level chips, specifically Schottky diodes, PN junction diodes, MOSFETs, HEMTs, and HBTs made from semiconductor materials such as Si, Ge, GaAs, InP, GaN, SiC, Ga2O3, graphene, MuS2, diamond, BN, AlN, and InN.

[0023] Accordingly, multiple chips 1 are connected to the pads of the substrate 3 via flip-chip interconnect.

[0024] Alternatively, multiple chips 1 can be interconnected with the pads on the substrate 3 via beam-type leads.

[0025] However, this planar interconnection method introduces new problems in highly integrated heterogeneous circuits. Because different chips differ in their fabrication materials, transmission performance, and other characteristics, their heat dissipation performance varies, leading to thermal mismatch issues with this planar interconnection method. Therefore, in this embodiment of the invention, porous conductors 2 are added between the individual chips 1, connecting them to the pads on the substrate 3. Their porous structure compensates for the expansion and contraction differences of different materials, disperses thermal stress, and thus mitigates the reliability risks caused by thermal mismatch.

[0026] Optionally, the substrate 3 includes an active region and a passive region.

[0027] Chip 1 is connected to the active circuit region of substrate 3 via porous conductor 2.

[0028] Optionally, the substrate 3 is made of insulating or semi-insulating material.

[0029] Figure 2 This is a schematic diagram illustrating the division of the active and passive regions in the substrate provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the structure design of the porous conductor 2 can optimize the current distribution, reduce electromagnetic coupling during high-frequency signal transmission, and reduce parasitic inductance and parasitic resistance. At the same time, the chip 1 is precisely connected to the active area of ​​the substrate 3, which shortens the signal transmission path, avoids interference of passive area circuits to active signals, and further improves the transmission efficiency and fidelity of high-frequency signals.

[0030] To meet the insulation requirements of high-frequency circuits and avoid signal crosstalk, the substrate 3 is made of insulating or semi-insulating materials, which can effectively isolate the electrical connections between different circuit modules on the substrate surface, prevent crosstalk and leakage of high-frequency signals, and provide a stable working environment for the chip 1. At the same time, the insulating or semi-insulating substrate 3 has good high-frequency dielectric properties, which can reduce signal transmission loss and meet the application requirements of high-frequency bands.

[0031] Therefore, this invention connects the individual chips to the substrate using a planar interconnection method. However, integrating different types of chips onto the same substrate in this way can lead to thermal mismatch. To address this issue, this invention incorporates porous conductors between the chips and the substrate. These porous conductors utilize their loose structure to offset the expansion and contraction differences between different materials, dispersing thermal stress and mitigating the reliability risks associated with thermal mismatch. Thus, this invention, through the combination of planar interconnection and porous conductors, can significantly shorten the interconnection path between the chips and the substrate circuitry while increasing system integration density. This reduces parasitic inductance and capacitance, avoids high-frequency signal reflection, attenuation, and distortion, and ensures signal transmission quality under high integration.

[0032] In an alternative embodiment, the structure of the porous conductor 2 is determined based on the thermal and electrical characteristics of the chip 1 to which it is connected.

[0033] Figure 3 This is a schematic diagram of the porous conductor provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the structure of the porous conductor 2 includes its area, thickness, and pore density. Specifically, taking a typical chip in a high-frequency heterogeneous integrated circuit that simultaneously contains both GaAs Schottky diodes and GaN Schottky diodes as an example, the structure of the porous conductor 2 is explained.

[0034] GaAs Schottky diodes are characterized by low power and low heat dissipation, and are often used in medium and high frequency applications. Their thermal characteristics are: low operating power, low heat generation, and low heat dissipation requirements; their electrical characteristics are: low operating current, and high frequency signal transmission is sensitive to parasitic inductance.

[0035] Correspondingly, the structure of the porous conductor 2 is as follows: Its area can be slightly larger than the chip electrode area. For example, if the chip electrode area is 0.5 mm², the area of ​​the porous conductor 2 can be 0.6 mm², which is sufficient to meet the basic electrical connection requirements and avoid increasing parasitic capacitance due to excessive area.

[0036] Its thickness can be selected as 10μm thin structure to reduce the parasitic inductance of the metal layer, adapt to the low loss transmission requirements of medium and high frequency signals, and at the same time the thinness is sufficient to conduct the small amount of heat generated by the chip.

[0037] Its pore density can be selected as low pore density, such as 20% pores, to ensure the conductivity continuity of the conductor, avoid the resistance increase caused by too many pores, and in low heat dissipation scenarios, there is no need for high porosity to enhance heat dissipation.

[0038] GaN Schottky diodes are characterized by high power and high heat dissipation, and are often used in high-frequency, high-power applications. Their thermal characteristics are: high operating power, large heat generation, and urgent need for heat dissipation; their electrical characteristics are: large operating current, requiring reduction of current density to avoid local overheating, and parasitic parameters need to be controlled under high-frequency conditions.

[0039] Correspondingly, the structure of the porous conductor 2 is as follows: Its area can be slightly larger than the chip electrode area. For example, if the chip electrode area is 0.5 mm², the conductor area is 0.8 mm², which increases the current conduction cross-section, reduces the current density, and reduces Joule heating.

[0040] Its thickness can be selected as 20μm thick structure to increase the conductive volume to carry large current, while the thick metal layer increases the heat dissipation contact area and accelerates the heat conduction to the substrate.

[0041] Its pore density can be selected to be high, such as 40% pores. On the one hand, the pores form heat dissipation channels and enhance the heat conduction efficiency under high heat dissipation. On the other hand, the pore structure is used to break the electromagnetic coupling of the metal layer, which can offset the problem of increased parasitic inductance caused by the thickness. At the same time, high porosity can improve structural elasticity and alleviate the thermal mismatch stress between GaN and the substrate.

[0042] Figure 4 This is a structural diagram of the beam-lead structure diode transistor-level chip provided in the embodiment of the present invention; Figure 5 This is a structural diagram of the flip-chip diode transistor stage provided in the embodiment of the present invention; Figure 6 This is a structural diagram of the beam-lead structure transistor-level chip provided in the embodiment of the present invention; Figure 7 This is a structural diagram of the flip-chip transistor stage provided in an embodiment of the present invention. The following description, in conjunction with the above-mentioned typical structures, will illustrate these structures: Figure 4 This diode chip employs a beam-type interconnect configuration to meet the requirements of planar substrate interconnection, and represents the core structure of passive devices in high-frequency applications. It comprises a substrate, a PN junction, an anode beam-type lead, and a cathode beam-type lead. The anode and cathode beam-type leads are flat, rigid metal beams integrated into the chip, extending directly out of the chip edge without requiring additional leads.

[0043] The ends of the beam-type leads can be directly soldered to the substrate pads to achieve electrical connection between the chip and the substrate. The long lead-free design reduces high-frequency parasitic effects, while the high strength of the metal beam structure improves interconnect reliability and is suitable for low-loss transmission of high-frequency signals.

[0044] Figure 5 This is a diode chip employing flip-chip interconnection, a planar alternative to beam interconnection, and is also suitable for high-frequency heterogeneous integration scenarios. It comprises a substrate, a PN junction, and chip pads. Unlike traditional front-facing connections, this chip uses an inverted design, with the chip's electrode surface directly facing the substrate.

[0045] The chip pads are precisely bonded to the substrate pads through structures such as metal bumps, resulting in extremely short interconnect paths. This minimizes high-frequency parasitic inductance and capacitance. At the same time, the chip is tightly bonded to the substrate, improving heat dissipation efficiency and meeting the high-frequency performance requirements of high integration.

[0046] Figure 6 This is a HEMT chip, which uses a beam interconnect configuration. It comprises a substrate, source, drain, gate, and source beam leads, drain beam leads, and gate beam leads extending outwards from the chip edge. The metal beams are directly connected to the internal electrodes of the chip, forming an outward connection interface.

[0047] The source, drain, and gate electrodes are directly soldered to the substrate pads via beam-type leads, enabling electrical connections between the source, drain, gate, and substrate bias circuitry and matching structure. Its rigid metal beam design ensures connection stability under high-frequency, high-current conditions while shortening interconnect paths, preventing signal attenuation, and meeting the high-gain, low-noise requirements of amplifier circuits.

[0048] Figure 7 This is a complementary solution to HEMT chips using a flip-chip interconnect configuration, emphasizing higher integration and lower parasitic effects. It includes a substrate, source, drain, gate, and source, drain, and gate pads on the chip surface. After the chip is flipped, these pads are directly bonded to the corresponding pads on the substrate via metal bumps. This direct connection between the pads and the substrate shortens the interconnect path, and combined with the thermal stress buffering effect of the porous conductor, it simultaneously solves high-frequency parasitic problems and thermal mismatch issues. It is suitable for high-power, high-frequency amplifier circuits, ensuring the transmission quality after signal amplification.

[0049] Figures 4-7 The structure provided by the system abandons the traditional long lead and vertical stacking design, reduces parasitic effects by shortening the interconnect path, and adapts to the active area connection of the substrate, porous conductor bonding and other designs, ultimately supporting the core requirements of high performance and high integration of high frequency circuits.

[0050] In an optional embodiment, the substrate 3 also includes transmission lines, matching structures, interconnects, and passive devices.

[0051] The transmission line is used to connect the pads of multiple chips 1 to the matching structure; the matching structure is used to perform impedance matching on multiple chips 1.

[0052] Interconnects are used to connect transmission lines, matching structures, and passive components.

[0053] In this embodiment, in addition to the above, the substrate 3 also includes through holes and irregular structures.

[0054] In this embodiment, the transmission line is used for signal transmission; the matching structure is a preset topology composed of passive components, used to achieve impedance matching between chip 1 and the transmission line or different integrated circuits; the interconnect line is used to connect the transmission line, passive components, matching structure, and the pads corresponding to chip 1. Through-holes are used to enable circuit conduction between different wiring layers of the substrate, or to connect the substrate to external components. The irregular structure is a non-standard shape structure designed to adapt to high-frequency characteristics and integrated layout requirements; for example, it may include specially curved transmission line segments, irregular grounding metal surfaces, chip bonding positioning grooves, porous conductor irregular contours, etc.

[0055] In an optional embodiment, the high-frequency chip heterogeneous integrated circuit is an amplifier circuit, and the multiple chips include a first HEMT chip HEMT1 and a second HEMT chip HEMT2.

[0056] The substrate also includes a first DC blocking capacitor Cg1, a second DC blocking capacitor Cg2, a third DC blocking capacitor Cg3, a first matching circuit P1, a second matching circuit P2, a third matching circuit P3, a fourth matching circuit P4, a first drain bias circuit L1, a second drain bias circuit L2, a first gate bias circuit S1, a second gate bias circuit S2, a first bypass capacitor Cp1, a second bypass capacitor Cp2, a third bypass capacitor Cp3, and a fourth bypass capacitor Cp4.

[0057] The first end of the first DC blocking capacitor Cg1 is connected to the input port K1, and the second end is connected to the emitter of the first HEMT chip HEMT1 through the first matching circuit P1.

[0058] The emitter of the first HEMT chip HEMT1 is also connected to the first terminal of the first gate bias circuit S1 and the first terminal of the first bypass capacitor Cp1, respectively. Its collector is connected to the first terminal of the second matching circuit P2, the first drain bias circuit L1 and the first terminal of the second bypass capacitor Cp2, respectively, and its base is grounded.

[0059] The second terminal of the first bypass capacitor Cp1 and the second terminal of the second bypass capacitor Cp2 are respectively grounded.

[0060] The second terminal of the second matching circuit P2 is connected to the emitter of the second HEMT chip HEMT2 through the second DC blocking capacitor Cg2 and the third matching circuit P2.

[0061] The emitter of the second HEMT chip HEMT2 is also connected to the first terminal of the second gate bias circuit S2 and the third bypass capacitor Cp3, respectively. Its collector is connected to the first terminal of the fourth matching circuit P4, the first terminal of the second drain bias circuit L2 and the fourth bypass capacitor Cp4, respectively, and its base is grounded.

[0062] The second terminal of the third bypass capacitor Cp3 and the second terminal of the fourth bypass capacitor Cp4 are grounded respectively.

[0063] The second terminal of the fourth matching circuit P4 is connected to the output port K2 through the third DC blocking capacitor Cg3.

[0064] Figure 8 This is a schematic diagram of the amplifier circuit provided in an embodiment of the present invention; as shown below. Figure 8 As shown.

[0065] The amplifier circuit is a high-frequency heterogeneous amplifier circuit based on dual HEMT chips. By integrating two types of HEMT chips heterogeneously and combining auxiliary circuits such as matching, biasing, DC blocking, and bypassing, it achieves low-noise and high-gain amplification of high-frequency signals, adapting to the signal enhancement requirements in high-frequency scenarios.

[0066] In this circuit, the high-frequency input signal enters from the input port K1, and after the DC component is filtered out by the first DC blocking capacitor Cg1, the impedance is adapted by the first matching circuit P1 and transmitted to the emitter of the first HEMT chip HEMT1.

[0067] HEMT1 amplifies the signal initially under the gate bias voltage provided by the first gate bias circuit S1 and the drain bias voltage provided by the first drain bias circuit L1. The amplified signal is output from its collector and its transmission characteristics are optimized by the second matching circuit P2.

[0068] The signal is filtered out of DC interference again by the second DC blocking capacitor Cg2, and after further impedance matching by the third matching circuit P3, it is input to the emitter of the second HEMT chip HEMT2.

[0069] With the power support of the second gate bias circuit S2 and the second drain bias circuit L2, HEMT2 amplifies the signal a second time. The amplified signal is output from its collector and is matched to the load impedance by the fourth matching circuit P4.

[0070] Finally, the signal is filtered by the third DC blocking capacitor Cg3 to remove DC, and then output from the output port K2.

[0071] In an optional embodiment, the high-frequency chip heterogeneous integrated circuit is a frequency multiplier circuit, and the plurality of chips 1 include a first diode chip D1, a second diode chip D2, a third diode chip D3, and a fourth diode chip D4.

[0072] The substrate 3 includes a filter L1 and a frequency doubling matching circuit PL1. The filter L1 can be a low-pass filter.

[0073] The first end of filter L1 is connected to the input terminal H1, and the second end is connected to the frequency doubling matching circuit PL1 through the negative terminals of the second diode chip D2 and the third diode chip D3, respectively, and is connected to the output terminal H2 through the frequency doubling matching circuit PL1.

[0074] The positive terminal of the second diode chip D2 is connected to the negative terminal of the first diode chip D1, and the positive terminal of the first diode chip D1 is grounded.

[0075] The positive terminal of the third diode chip D3 is connected to the negative terminal of the fourth diode chip D4, and the positive terminal of the fourth diode chip D4 is grounded.

[0076] Figure 9This is a schematic diagram of the frequency multiplier circuit provided in an embodiment of the present invention. Figure 9 As shown.

[0077] This circuit is a high-frequency frequency multiplier based on the heterogeneous integration of four diode chips. By utilizing the nonlinear characteristics of the diodes, the frequency of the input high-frequency signal is multiplied. At the same time, the purity and transmission efficiency of the output signal are ensured by the filter L1 and the frequency matching circuit PL1, making it suitable for frequency conversion requirements in high-frequency communication, radar and other scenarios.

[0078] The signal flow is as follows: the high-frequency input signal enters from the input terminal H1, and after being filtered by the filter L1 to remove high-frequency noise, a pure original frequency signal is obtained. The pure signal is divided into two paths, which pass through the negative terminals of the second diode chip D2 and the third diode chip D3, respectively, and are input to the frequency doubling and matching circuit PL1.

[0079] Diode chips (D1-D4) form a nonlinear conversion network: the positive terminal of D2 is connected to the negative terminal of D1 and the positive terminal of D1 is grounded; the positive terminal of D3 is connected to the negative terminal of D4 and the positive terminal of D4 is grounded. The unidirectional conductivity of the diodes is used to multiply the signal frequency and generate a frequency-doubled signal.

[0080] The frequency-doubled signal undergoes impedance matching via the frequency-doubled matching circuit PL1 to reduce signal reflection and loss, and is finally output from the output terminal H2.

[0081] In an optional embodiment, the present invention provides a fabrication method for fabricating the high-frequency chip heterogeneous integrated circuit provided above, the method comprising: Apply flux to the pads on the substrate.

[0082] The porous conductor is transferred to the flux on the pads, and the substrate is then heat-annealed.

[0083] The chip is connected to the pads via a planar interconnect to achieve bonding between the chip and the substrate.

[0084] The fabrication method provided in this embodiment uses a transfer method to fabricate the corresponding high-frequency chip heterogeneous integrated circuit. Figure 10 This is a flowchart illustrating the fabrication process of a high-frequency chip heterogeneous integrated circuit provided in an embodiment of the present invention. The following is a description of the process in conjunction with... Figure 10 This embodiment will be described.

[0085] The substrate 3 includes pads 4, pre-treated substrate pads 4, and flux 5 is uniformly applied to the area of ​​the target pads 4 to provide adhesion for the temporary fixation of the porous conductor 2.

[0086] The pre-fabricated porous conductor 2 is precisely transferred onto the pad 4 coated with flux 5. Initial positioning is achieved through the flux. Subsequently, the substrate 3 is subjected to thermal annealing to form a stable bond between the porous conductor 2 and the pad 4.

[0087] Using a planar form of flip-chip interconnect or beam interconnect, various types of high-frequency chips 1 are connected to the pads 4 of the substrate 3, and pressure and heat are applied to complete the bonding between the chip 1 and the substrate 3, ultimately forming a high-frequency chip heterogeneous integrated circuit.

[0088] In addition to the methods mentioned above, it can also be prepared by electroplating or 3D printing. The two methods are as follows: A porous conductor is formed on the target pad of the substrate using an electroplating method.

[0089] The chip is connected to a porous conductor via a planar interconnect to achieve bonding between the chip and the substrate; or, A porous conductor is generated on the target pad of the substrate using 3D printing.

[0090] The chip is connected to a porous conductor via a planar interconnect to achieve bonding between the chip and the substrate.

[0091] In summary, this invention provides a high-frequency chip heterogeneous integrated circuit and its fabrication method. The high-frequency chip heterogeneous integrated circuit includes multiple chips, porous conductors, and a substrate, wherein the multiple chips are of at least two types. Traditional vertical stacked interconnect structures suffer from parasitic inductance and capacitance. To avoid high-frequency signal reflection, attenuation, and distortion, and to ensure signal transmission quality under high integration density, this embodiment uses a planar interconnect to connect each chip to the substrate. However, integrating different types of chips onto the same substrate in this way leads to thermal mismatch. To solve this problem, this invention provides porous conductors between each chip and the substrate. Their porous structure offsets the expansion and contraction differences of different materials, disperses thermal stress, and thus mitigates the reliability risks caused by thermal mismatch. Therefore, this invention, through the combination of planar interconnect and porous conductors, can significantly shorten the interconnection path between the chip and substrate circuits while increasing system integration density, reducing parasitic inductance and capacitance, avoiding high-frequency signal reflection, attenuation, and distortion, and ensuring signal transmission quality under high integration density.

[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-frequency chip heterogeneous integrated circuit, characterized in that, include: Multiple chips, porous conductors, and a substrate; the multiple chips are of at least two types; The multiple chips are interconnected in a planar manner and connected to the pads of the substrate through the porous conductor.

2. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The structure of the porous conductor is determined based on the thermal and electrical properties of the chip it is connected to.

3. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The planar interconnection form includes inverted interconnection or beam-type lead wire interconnection; Accordingly, the plurality of chips are connected to the pads of the substrate via flip-chip interconnect; Alternatively, the plurality of chips are interconnected to the pads on the substrate via beam-type interconnects.

4. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The substrate is made of insulating or semi-insulating material.

5. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The substrate also includes transmission lines, matching structures, interconnect lines, and passive devices; The transmission line is used to connect the pads of the plurality of chips to the matching structure; the matching structure is used to perform impedance matching on the plurality of chips. The interconnect line is used to connect the transmission line, the matching structure, and the passive device.

6. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The high-frequency chip heterogeneous integrated circuit is an amplifier circuit, and the plurality of chips include a first HEMT chip and a second HEMT chip. The substrate also includes a first DC blocking capacitor, a second DC blocking capacitor, a third DC blocking capacitor, a first matching circuit, a second matching circuit, a third matching circuit, a fourth matching circuit, a first drain bias circuit, a second drain bias circuit, a first gate bias circuit, a second gate bias circuit, a first bypass capacitor, a second bypass capacitor, a third bypass capacitor, and a fourth bypass capacitor. The first end of the first DC blocking capacitor is connected to the input port, and the second end is connected to the emitter of the first HEMT chip through the first matching circuit; The emitter of the first HEMT chip is also connected to the first gate bias circuit and the first terminal of the first bypass capacitor, respectively. Its collector is connected to the first terminal of the second matching circuit, the first drain bias circuit and the first terminal of the second bypass capacitor, respectively. Its base is grounded. The second terminal of the first bypass capacitor and the second terminal of the second bypass capacitor are respectively grounded; The second terminal of the second matching circuit is connected to the emitter of the second HEMT chip through the second DC blocking capacitor and the third matching circuit; The emitter of the second HEMT chip is also connected to the first terminal of the second gate bias circuit and the third bypass capacitor, respectively. Its collector is connected to the first terminal of the fourth matching circuit, the second drain bias circuit and the first terminal of the fourth bypass capacitor, respectively. Its base is grounded. The second terminal of the third bypass capacitor and the second terminal of the fourth bypass capacitor are respectively grounded; The second terminal of the fourth matching circuit is connected to the output port through the third DC blocking capacitor.

7. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The high-frequency chip heterogeneous integrated circuit is a frequency multiplier circuit, and the plurality of chips include a first diode chip, a second diode chip, a third diode chip, and a fourth diode chip; The substrate includes a filter and a frequency doubling matching circuit; The first end of the filter is connected to the input end, and the second end is connected to the frequency doubling matching circuit through the negative terminals of the second diode chip and the third diode chip, respectively, and is connected to the output end through the frequency doubling matching circuit. The positive terminal of the second diode chip is connected to the negative terminal of the first diode chip, and the positive terminal of the first diode chip is grounded. The positive terminal of the third diode chip is connected to the negative terminal of the fourth diode chip, and the positive terminal of the fourth diode chip is grounded.

8. The high-frequency chip heterogeneous integrated circuit as described in claim 1, characterized in that, The substrate includes an active region and a passive region; The plurality of chips are connected to the active circuit region of the substrate via the porous conductor.

9. A preparation method, characterized in that, The method for fabricating a high-frequency heterogeneous integrated circuit as described in any one of claims 1-8 comprises: Apply flux to the pads on the substrate; The porous conductor is transferred to the flux on the pad, and the substrate is subjected to thermal annealing. The chip is connected to the pads via a planar interconnect to achieve bonding between the chip and the substrate.

10. A preparation method, characterized in that, The method for fabricating a high-frequency heterogeneous integrated circuit as described in any one of claims 1-8 comprises: A porous conductor is generated on the target pad of the substrate using an electroplating method; The chip is connected to the porous conductor via a planar interconnect to achieve bonding between the chip and the substrate; or, A porous conductor was generated on the target pad of the substrate using 3D printing. The chip is connected to the porous conductor via a planar interconnect to achieve bonding between the chip and the substrate.

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