Millimeter wave (MMW) low noise active phase shifter

Abstract

A phase shifter has: an input matching network; a vector modulator connected to the input matching network, the vector modulator configured to alter an amplitude of a signal provided by the input matching network; a bias network coupled to an output of the vector modulator; and a combining circuit connected to the outputs of the vector modulator, the combining circuit configured to generate a first phase ([theta] 1) signal from the outputs of the vector modulator.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to phase shifters in transceivers. Background Technology

[0002] Wireless communication devices and technologies are becoming increasingly prevalent, including those operating at millimeter-wave (mmW) and sub-terahertz (subTHz) frequencies. Wireless communication devices typically transmit and / or receive communication signals. In radio frequency (RF) transceivers, the communication signal is typically amplified and transmitted by the transmitting section, and the received communication signal is amplified and processed by the receiving section. Transceivers used for communication in 5G and 6G applications can communicate using millimeter-wave (mmW) frequency signals and / or sub-THz frequencies, and can utilize so-called zero-IF (ZIF) or low-IF architectures.

[0003] Transceivers used in 5G communication systems can increase system capacity using a technique called beamforming. Beamforming typically uses separate transmit and receive elements, where phase shifters change the phase of the signal. Often, many of these elements and phase shifters are implemented in such systems. Typically, each TX / RX element uses two phase shifters, one for transmitting and one for receiving.

[0004] Active phase shifters are commonly used in transmit applications because they offer good signal gain and typically consume little area. Active phase shifters can utilize some passive circuitry. For example, a passive circuit can generate in-phase (I) and quadrature (Q) signals and act as a vector modulator (VM) of the active circuitry to provide the desired phase shift to the I and Q signals. However, there are challenges in combining passive IQ input circuitry with a vector modulator. For example, passive IQ circuitry may generate noise and may introduce imbalances in the I and Q signals. These imbalances should be corrected before the I and Q signals are applied to the vector modulator for phase shifting. Such circuitry consumes significant power and can generate substantial system noise, making it difficult to implement in the receive chain. Summary of the Invention

[0005] The various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which individually fully encompasses the desired properties described herein. Certain prominent features are described herein without limiting the scope of the appended claims.

[0006] Details of one or more specific embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. It should be noted that the relative dimensions in the following drawings may not be drawn to scale.

[0007] One aspect of this disclosure provides a phase shifter having: an input matching network; a vector modulator connected to the input matching network and configured to change the amplitude of a signal provided by the input matching network; a bias network coupled to the output of the vector modulator; and a combination circuit connected to the output of the vector modulator and configured to generate a first phase (θ1) signal from the output of the vector modulator.

[0008] Another aspect of this disclosure provides a method for phase shifting, the method comprising: dividing an input signal into a first portion and a second portion, and adjusting the amplitudes of the first portion and the second portion; biasing the amplitude-adjusted first portion and the amplitude-adjusted second portion; and passively combining the amplitude-adjusted first portion and the amplitude-adjusted second portion to generate a first phase (θ1) signal.

[0009] Another aspect of this disclosure provides an apparatus comprising: means for dividing an input signal into a first portion and a second portion and actively adjusting the amplitudes of the first portion and the second portion; means for biasing the amplitude-adjusted first portion and the amplitude-adjusted second portion; and means for passively combining the amplitude-adjusted first portion and the amplitude-adjusted second portion using a passive combiner to generate a first phase (θ1) signal.

[0010] Another aspect of this disclosure provides a phase shifter comprising: an input matching network coupled to an input of the phase shifter; a variable gain amplifier, wherein the output of the input matching network is coupled to the gate of an amplifying transistor in the variable gain amplifier; and a quadrature all-pass filter (QAF) coupled to the output of the variable gain amplifier and the output of the phase shifter. Attached Figure Description

[0011] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter characters, such as "102a" or "102b", the letter characters distinguish two similar parts or elements in the same drawing. When the aim is to have the reference numerals cover all parts with the same reference numerals in all drawings, the letter characters of the reference numerals may be omitted.

[0012] Figure 1 This is a diagram illustrating communication between a wireless device and a wireless communication system.

[0013] Figure 2AThis is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0014] Figure 2B This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0015] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0016] Figure 3 It is a diagram showing a portion of the circuitry on an integrated circuit (IC).

[0017] Figure 4 yes Figure 3 A schematic diagram of a phase shifter.

[0018] Figure 5 yes Figure 4 A graphical representation of the operation of the combinational circuit.

[0019] Figure 6 This is a flowchart illustrating an example of the operations used for phase shifting.

[0020] Figure 7 This is a functional block diagram of a device used for phase shifting. Detailed Implementation

[0021] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0022] In an exemplary embodiment, the phase shifter may include a vector modulator for changing the signal amplitude, followed by an orthogonal full-pass filter (QAF) for generating I and Q signals.

[0023] In an exemplary embodiment, the QAF following the vector modulator in the phase-shift circuit minimizes the need for a matching network between the vector modulator and the QAF.

[0024] In an exemplary embodiment, the phase-shifting circuit with a QAF following the vector modulator is efficient in terms of area consumption.

[0025] In an exemplary implementation, a phase-shifting circuit with a QAF following a vector modulator provides a low noise figure (NF) and can be implemented in the receiver chain.

[0026] Figure 1This diagram illustrates communication between wireless device 110 and wireless communication system 120. Wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Generally, a wireless communication system may include any number of base stations and any set of network entities.

[0027] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet computer, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet computer, cordless phone, medical device, vehicle, device configured (e.g., via the Internet of Things) to connect to one or more other devices, customer premises equipment (CPE), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 can communicate with wireless communication system 120. Wireless device 110 can also receive signals from broadcast stations (e.g., broadcast station 134) and / or communicate with satellites (e.g., satellites 150 in one or more Global Navigation Satellite Systems (GNSS)). Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub6 5G, 6G, UWB, etc.

[0028] Wireless device 110 can operate in various communication frequency bands, including those used by LTE, WiFi, 5G, or other communication frequency bands within a wide frequency range. Wireless device 110 can also communicate directly with other wireless devices without communicating through a network.

[0029] Wireless device 110 may support carrier aggregation, for example, as described in one or more LTE or 5G standards. In some implementations, carrier aggregation is used to transmit a single data stream on multiple carriers, as opposed to separate carriers used for each data stream. Generally, carrier aggregation (CA) can be classified into two types: intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same frequency band. Inter-band CA refers to operation on multiple carriers in different frequency bands.

[0030] Figure 2A This is a block diagram illustrating a wireless device 200 in which exemplary technologies of the present disclosure may be implemented. The wireless device 200 may be, for example, Figure 1 The illustrated implementation scheme of wireless device 110.

[0031] Figure 2A An example of a transceiver 220 with a transmitter 230 and a receiver 250 is shown. Generally, the conditioning of the signals in the transmitter 230 and receiver 250 can be performed by one or more stages such as amplifiers, filters, up-converters, down-converters, etc. These circuit blocks are based on... Figure 2A The configurations shown are arranged differently. Furthermore, Figure 2A Other circuit blocks, not shown, can also be used to regulate the signals in transmitter 230 and receiver 250, such as phase shifters as discussed further below. Unless otherwise indicated, Figure 2A Any signal in any of the other diagrams in the attached figures may be single-ended or differential. Figure 2A Some circuit blocks in the code can also be omitted.

[0032] exist Figure 2A In the example shown, wireless device 200 typically includes a transceiver 220 and a data processor 210. Data processor 210 may include a processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code, generally shown using reference numeral 299, and may typically include analog and / or digital processing components. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Generally, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0033] Transmitters or receivers can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multiple stages of frequency conversion between radio frequency (RF) and baseband; for example, for a receiver, this might involve switching from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can utilize different circuit blocks and / or have different requirements. Figure 2A In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0034] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting digital signals generated by data processor 210 into I analog output signals and Q analog output signals (e.g., I output current and Q output current) for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 provides data (e.g., for I and Q) digitally to transceiver 220.

[0035] Within transmitter 230, low-pass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted image frequencies caused by the preceding digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from low-pass filters 232a and 232b, respectively, providing the I baseband and Q baseband signals. Upconverter 240, with upconverters 241a and 241b, uses the I TX LO and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 290 to upconvert the I baseband and Q baseband signals, providing the upconverted signals. Filter 242 filters the upconverted signals to remove unwanted image frequencies caused by frequency upconversion and noise in the receive band. Power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provide the transmit RF signal. The transmitted RF signal is routed via a duplexer or switch 246 and transmitted through antenna 248, or alternatively, the transmitted RF signal can be transmitted to a separate transmit antenna different from the separate receive antenna. Although the examples discussed herein utilize I and Q signals, those skilled in the art will understand that transceiver components can be configured to utilize polarity modulation.

[0036] In the receiving path, antenna 248 receives the communication signal and provides the received RF signal, which can be routed via a duplexer or switch 246 and provided to a low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with specific RX and TX duplexer frequencies, thus isolating the RX and TX signals. Alternatively, separate transmit and receive antennas as mentioned above can exist, in which case RX and TX isolation can be achieved through limited coupling between the two antennas. In the case of separate RX and TX antennas, the RX antenna can be directly coupled to LNA 252. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Downconverters 261a and 261b in downconverter 260 mix the output of filter 254 with the I RX LO and Q RX LO signals (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I baseband and Q baseband signals. The I-baseband signal and Q-baseband signal are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain the I-analog input signal and Q-analog input signal, which are provided to the data processor 210. In the illustrated exemplary embodiment, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor 210. In some embodiments, ADCs 216a and 216b are included in transceiver 220 and provide data digitally to the data processor 210.

[0037] exist Figure 2A In this configuration, TX LO signal generator 290 generates I TX LO and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I RX LO and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from LO signal generator 280.

[0038] In an exemplary embodiment, RX PLL 282, TX PLL 292, RX LO signal generator 280, and TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include common or shared LO signal generator circuitry to provide TX LO and RX LO signals. Alternatively, separate LO generator circuitry may be used to generate TX LO and RX LO signals.

[0039] The wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies, and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will understand that the aspects described herein may be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0040] Figure 2A The transceiver 220 is functionally illustrated in the text, and the illustrated configuration may or may not represent the physical device configuration in certain specific implementations. For example, as described above, the transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board (such as a printed circuit board (PCB)) having various modules, chips, and / or components. For example, the power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver 220 may be implemented in a single transceiver chip.

[0041] Power amplifier 244 may include one or more stages, such as driver stages, power amplifier stages, or other components that may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0042] In an exemplary implementation of the superheterodyne architecture, filter 242, PA 244, LNA 252, and filter 254 can be implemented separately from other components in transmitter 230 and receiver 250, and can be implemented on a millimeter-wave integrated circuit. Figure 2B The example superheterodyne architecture is illustrated in the figure.

[0043] Figure 2BThis is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented. Figure 2B Certain components of the wireless device 200a (e.g., those indicated by the same reference numerals) may be similar to... Figure 2A The components in the wireless device 200 shown are configured, and there will be no duplicate configuration. Figure 2B Descriptions of items with the same number in the table.

[0044] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture, in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and intermediate frequency (IF). For example, upconverter 240 may be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 may include upconverter mixer 276. Summation function 278 of upconverter 240 combines the I output and Q output and provides the combined signal to mixer 276. The combined signal may be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and the TX RF LO signal from TXRF LO signal generator 277, and provide the upconverted RF signal to phase shift circuit 281. Although PLL 292 is in Figure 2B The PLL is exemplified as being shared by signal generators 290 and 277, but a corresponding PLL can be implemented for each signal generator.

[0045] In an exemplary embodiment, the components in the phase shift circuit 281 may include one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor 210 via connection 294, and operate the adjustable or variable phased array elements based on the received control signals.

[0046] In an exemplary embodiment, phase shift circuit 281 includes phase shifter 283 and phased array element 287. Although three phase shifters 283 and three phased array elements 287 are shown for illustrative purposes, phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287.

[0047] Each phase shifter 283 can be configured to receive an RF transmission signal from the upconverter 275, change its phase by a certain amount, and provide an RF signal to a corresponding phased array element 287. Each phased array element 287 may include transmitting and receiving circuitry, including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifter 283 may be integrated into the corresponding phased array element 287.

[0048] The output of phase shift circuit 281 is provided to antenna array 248. In an exemplary embodiment, antenna array 248 includes a plurality of antennas, typically corresponding to the number of phase shifters 283 and phased array elements 287, such that each antenna element is coupled to a corresponding phased array element 287. In an exemplary embodiment, phase shift circuit 281 and antenna array 248 may be referred to as a phased array.

[0049] In the receiving direction, the output of phase shift circuit 281 is provided to downconverter 285. In an exemplary embodiment, downconverter 285 may include downconverter mixer 286. In an exemplary embodiment, mixer 286 downconverts the received RF signal provided by phase shift circuit 281 to an IF signal based on the RX RF LO signal provided by RX RF LO signal generator 279. I / Q generation function 291 of downconverter 260 receives the IF signal from mixer 286 and generates I and Q signals in downconverter 260, which downconverts the IF signal to baseband, as described above. Although PLL 282 is in Figure 2B The PLL is exemplified as being shared by signal generators 280 and 279, but a corresponding PLL can be implemented for each signal generator.

[0050] In some embodiments, upconverter 275, downconverter 285, and phase shift circuit 281 are implemented on a common IC. In some embodiments, although the summation function 278 and I / Q generation function 291 are implemented separately from mixers 276 and 286, such that mixers 276, 286, and phase shift circuit 281 are implemented on a common IC, the summation function 278 and I / Q generation function 291 are not implemented on the common IC (e.g., the summation function 278 and I / Q generation function 291 are implemented in another IC coupled to the IC having mixers 276, 286). In some embodiments, LO signal generators 277, 279 are included in a common IC. In some embodiments where the phase shift circuit is implemented on a common IC having 276, 286, 277, 278, 279, and / or 291, the common IC and antenna array 248 are included (e.g., packaged together) in a module that can be coupled to other components of transceiver 220 via connectors. In some implementations, the phase shift circuit 281 (e.g., a chip on which the phase shift circuit 281 is implemented) is coupled to the antenna array 248 via interconnects. For example, components of the antenna array 248 may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuit 281 via a flexible printed circuit board, or the chip may be mounted on the substrate.

[0051] In some implementation schemes, Figure 2A The illustrated architecture and Figure 2BThe illustrated architecture is implemented within the same device. For example, wireless devices 110 or 200 can be configured to use... Figure 2A The architecture illustrated communicates with signals having frequencies below approximately 7 GHz (e.g., the FR1 band) and uses... Figure 2B The architecture illustrated communicates with signals at frequencies higher than approximately 24 GHz. In devices implementing either of these architectures, Figure 2A and Figure 2B One or more components with the same number can be shared between the two architectures. For example, a signal that has been directly down-converted from RF to baseband and a signal that has been down-converted from RF to baseband by an IF stage can both be filtered by the same baseband filter 264. In other embodiments, a first version of filter 264 is included in the device implementation. Figure 2A In the architecture section, and the second version of filter 264 is included in the device implementation. Figure 2B In the architecture of the part.

[0052] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented. Figure 2C Certain components of the wireless device 200b (e.g., indicated by the same reference numerals) can be configured with... Figure 2A The wireless device 200 and / or shown Figure 2B The components in the wireless device 200a shown are similar, and Figure 2C Component items with the same number will not be described again.

[0053] Figure 2C The wireless device 200b in the direct conversion architecture incorporates ( Figure 2B The phase shift circuit 281 allows communication signals to be up-converted and down-converted between baseband and RF without the need for intermediate frequency (IF) signal conversion. This architecture can be configured as a low-IF (LIF) or zero-IF (ZIF) architecture. For example, Figure 2C The LO signal in the architecture can include a signal with a frequency of tens of GHz. In other examples, the LO signal can be a single digital or low dual-digit GHz frequency (e.g., when wireless device 200b is configured to be used with signals in the FR3 band) or hundreds of GHz (e.g., when wireless device 200b is configured to be used with signals in the sub-THz band).

[0054] In some embodiments, upconverter 240, downconverter 260, and phase shift circuit 281 are implemented on a common IC. In some embodiments, LO signal generators 280 and 290 are included in the common IC. In some embodiments, the common IC and antenna array 248 are included (e.g., packaged together) in a module that can be coupled to other components of transceiver 220 via connectors. In some embodiments, phase shift circuit 281 (e.g., a chip on which phase shift circuit 281 is implemented) is coupled to antenna array 248 via interconnects, or both are mounted on a substrate. For example, components of antenna array 248 may be implemented on the substrate and coupled to the integrated circuit implementing phase shift circuit 281 via flexible printed circuitry, or the integrated circuit may be mounted on the other side of the substrate. In some embodiments, upconverter 240 and downconverter 260 may be iterated multiple times to process multiple signals in different frequency bands.

[0055] Figure 3 This is a diagram showing a portion of circuit 300 including a phase shifter, which can be implemented on an integrated circuit, such as a millimeter-wave integrated circuit (mmW-IC) that also supports frequencies in FR3. However, as discussed above, circuit 300 can be configured to omit support for mmW frequencies or support for FR3 frequencies, or may be additionally or alternatively configured for use with other frequencies, such as below THz.

[0056] In an exemplary embodiment, some or all of the circuitry in circuit 300 may be implemented entirely or partially on mmW-IC or on one or more mmW-ICs.

[0057] In an exemplary embodiment, circuit 300 may include antennas 302, 304, 306, and 308. Antennas 302, 304, 306, and 308 may be... Figure 2C It is part of the antenna array 248 and can be configured to cover different frequency ranges. For example, antennas 302 and 308 can be configured to operate in the 7 GHz to 15 GHz band (e.g., in FR3), and antennas 304 and 306 can be configured to operate in the 24 GHz to 39 GHz band (e.g., mmW or FR2).

[0058] In an exemplary embodiment, antenna 302 may be connected to TX / RX switch 312, antenna 304 may be connected to TX / RX switch 314, antenna 306 may be connected to TX / RX switch 316, and antenna 308 may be connected to TX / RX switch 318. TX / RX switch 312 may be connected to phased array element 322, TX / RX switches 314 and 316 may be connected to phased array element 324, and TX / RX switch 318 may be connected to phased array element 328. In an exemplary embodiment, phased array elements 322 and 328 may be configured to operate in a 7 GHz to 15 GHz frequency band (λ1) (or in the range of 7 GHz to 24 GHz), and phased array element 324 may be configured to operate in a 24 GHz to 39 GHz frequency band (λ2). In some examples, an additional component besides the TX / RX switches is used to separate the TX and RX signals. For example, a duplexer or electromagnetic (EM) element may be used.

[0059] In an exemplary embodiment, phased array element 322 may include a power amplifier (PA) 321 and a low-noise amplifier (LNA) 323. Although shown as a single element, power amplifier 321 and LNA 323 may include more than one amplification stage.

[0060] In an exemplary embodiment, phased array element 324 may include power amplifiers 325 and 326; and may include LNAs 323 and 329. Although shown as a single element, power amplifiers 325 and 326 and LNAs 327 and 329 may include more than one amplification stage.

[0061] In an exemplary embodiment, phased array element 328 may include power amplifier 331 and LNA 333. Although shown as a single element, power amplifier 331 and LNA 333 may include more than one amplification stage.

[0062] In an exemplary embodiment, a frequency band selection switch 332 may be connected to phased array elements 322 and 324; and a frequency band selection switch 334 may be connected to phased array elements 324 and 328.

[0063] Although shown as part of circuitry 300, in some embodiments, phased array elements 322, 324, and 328 may be located on a separate radio frequency (RF) module. Furthermore, antennas 302, 304, 306, and 308 are not necessarily included on the mmW-IC. Antennas 302, 304, 306, and 308 may be part of a separate substrate and may be packaged together with the mmW-IC within the module or spaced apart from the mmW-IC.

[0064] Frequency conversion assembly 340 may include an upconversion mixer 344, a beamformer 345, a downconversion mixer 348, and a beamformer 349. In an exemplary embodiment, beamformer 345 may include a variable gain amplifier (VGA) 342 (which may include one or more stages) and a phase shifter 341. In an exemplary embodiment, beamformer 349 may include a variable gain amplifier (VGA) 347 (which may include one or more stages) and a phase shifter 346.

[0065] In an exemplary embodiment, phase shifter 341, VGA 342, and mixer 344 may be configured to operate on a transmit signal received from baseband circuitry (not shown); and phase shifter 346, VGA 347, and mixer 348 may be configured to operate on a receive signal provided to the baseband circuitry. The baseband circuitry may be configured to operate at least partially at the baseband, but may also be configured to communicate with circuitry 300 at other frequencies (e.g., intermediate frequencies). In some examples, circuitry 300 and the baseband circuitry communicate with at least some signals located at or near the baseband.

[0066] In an exemplary embodiment, frequency conversion component 340 may be connected to band selection switch 332, for example, such that frequency conversion component 340 is functionally coupled between baseband circuitry and band selection switch 332. Band selection switch 332 may be configured to route signals to phased array elements (and associated antennas) configured to operate in different frequency bands. In the illustrated example, band selection switch 332 is configured to switch back and forth between phased array elements supporting λ1 and phased array elements supporting λ2, but band selection switch 332 may be omitted when only certain frequencies are supported (e.g., one or a few closely spaced frequency bands), and / or when circuitry 300 supports additional frequency bands, the band selection switch may be configured to select between additional frequency bands.

[0067] Frequency conversion assembly 350 may include an upconversion mixer 354, a beamformer 355, a downconversion mixer 358, and a beamformer 359. In an exemplary embodiment, beamformer 355 may include a variable gain amplifier (VGA) 352 (which may include one or more stages) and a phase shifter 351. In an exemplary embodiment, beamformer 359 may include a variable gain amplifier (VGA) 357 (which may include one or more stages) and a phase shifter 356.

[0068] In an exemplary embodiment, phase shifter 351, VGA 352 and mixer 354 may be configured to operate on a transmit signal received from a baseband circuit (not shown); and phase shifter 356, VGA 357 and mixer 358 may be configured to operate on a receive signal provided to a baseband circuit (not shown).

[0069] In an exemplary embodiment, the frequency conversion component 350 may be connected to the band selection switch 334, for example, such that the frequency conversion component 350 is functionally coupled between the baseband circuitry and the band selection switch 334. The band selection switch 334 may be configured to route signals to phased array elements (and associated antennas) configured to operate in different frequency bands. In the illustrated example, the band selection switch 334 is configured to switch back and forth between phased array elements supporting λ1 and phased array elements supporting λ2; however, the band selection switch 334 may be omitted when only certain frequencies are supported (e.g., one or a few closely spaced frequency bands), and / or when the circuitry 300 supports additional frequency bands, the band selection switch may be configured to select between additional frequency bands.

[0070] In some examples, the positions of the band selection switches 332 and 334 differ from those illustrated. For example, the band selection switches 332 and 334 may be implemented between mixers (344, 348, 354, and / or 358) and associated beamformers (345, 349, 355, and / or 359). In some examples, the band selection switches are coupled between the baseband circuitry and several mixers, with the respective mixers used for λ1 and λ2. In still other examples, the respective interfaces for λ1 and λ2 are implemented between the baseband circuitry and circuitry 300, and the band selection switches 332 and 334 are omitted.

[0071] In some examples, several beamformers are coupled to a common mixer. For example, the common input of circuit 300 may be coupled to the input of mixer 344, and the output of mixer 344 may be coupled to the inputs of both beamformers 345 and 355. In such examples, mixer 354 may be omitted. Similarly, the outputs of beamformers 349 and 359 may be coupled to the input of mixer 358, and the output of mixer 358 may be coupled to the common output of circuit 300. In such examples, mixer 348 may be omitted.

[0072] Figure 3 The illustrated example is configured to provide a signal path phase shift. In other embodiments, the phase shifter is alternatively coupled between the LO and the mixer, and is configured to alternatively provide a LO path phase shift.

[0073] Figure 4 yes Figure 3 A schematic diagram 400 of a phase shifter (e.g., any of signal path phase shifters 341, 346, 351, 356, or an LO path phase shifter not illustrated). In an exemplary embodiment, the phase shifter circuit 400 includes an input matching network 401, an in-phase (I) VGA 410, a quadrature (Q) VGA 430, and a combination circuit 470. In an exemplary embodiment, the combination circuit 470 may be implemented as a quadrature all-pass filter (QAF). Although VGA 410 is referred to as an in-phase VGA and VGA 430 as a quadrature VGA, there is no or no intentional (e.g., 90-degree) phase difference between the signals in these components (although in instances of VGA 410 or 430, the polarity of the signals may be flipped or reversed). Instead, as described below, the I VGA and Q VGA are configured to receive the same differential signal from the matching network 401. For convenience, the terms "in-phase" and "quadrature" are used to describe circuits that operate on signals that will ultimately be processed to introduce a phase shift (e.g., in combinational circuit 470, it can be configured as QAF), as described below. In the example, I VGA 410 and Q VGA 430 can therefore behave as (active) vector modulators even if there is no (quadrature) phase difference between the signals therein.

[0074] In an exemplary embodiment, input matching network 401 may receive differential input signals at connections 404 and 405. In some embodiments, the positive component (+ or p) of the differential signal may be provided at connection 404, and the negative component (- or n) of the differential signal may be provided at connection 405. In other embodiments, a single-ended signal may be provided to input matching network 401, and the differential signal may be created using, for example, a balun (not shown). The signals at connections 404 and 405 may originate from another amplifier stage, such as from a low-noise amplifier (LNA) or a stage of an LNA (such as... Figure 3 One of the LNAs in the LNA), or from a VGA or VGA level (such as Figure 3 (A VGA in a VGA). In an exemplary embodiment, the input matching network 401 may include passive components, such as, for example, only resistors 402 and inductors 403, which are coupled in parallel between connection 404 and connection 405 in the illustrated example. In other embodiments, the input matching network 401 may include other passive elements or passive elements arranged in a different configuration, and in some embodiments may include active elements.

[0075] In an exemplary embodiment, positive input signals on connection 404 are provided to VGA 410 and 430 via connections 406 and 408, respectively; and negative input signals on connection 405 are provided to VGA 410 and 430 via connections 407 and 409, respectively.

[0076] In an exemplary embodiment, the I VGA 410 includes transistors 411, 412, 413, 414, 416, 417, 418, and 419. Figure 4 In the example shown, transistors 411, 412, 413, 414, 416, 417, 418, and 419 are all N-type field-effect transistors (N-FETs). However, transistors 411, 412, 413, 414, 416, 417, 418, and 419 may alternatively be P-type FETs, or may be fabricated using other manufacturing techniques and processes.

[0077] The drain of each of transistors 413 and 419 is connected to the system voltage VDD. The drain of transistor 414 is connected to the drain of transistor 417, and the drains of both transistors are connected to node 426 and connection 452. The drain of transistor 416 is connected to the drain of transistor 418, and the drains of both transistors are connected to node 428 and connection 454. Selectively enabling transistors 414 and 418 or transistors 416 and 417 can maintain or toggle the polarity of the signal passing through VGA 410 (in an instance).

[0078] The sources of transistors 413, 414, and 416 are connected together and then connected to the drain of transistor 411. The sources of transistors 417, 418, and 419 are connected together and then connected to the drain of transistor 412. The sources of transistors 411 and 412 are connected to system ground. Transistors 411 and 412 can be configured as amplifying transistors. Transistors 414, 416, 417, and 418 can be configured in a cascode configuration and / or configured as switching transistors.

[0079] The gate of transistor 411 is configured to receive a positive differential signal (I+) from connection 406, and the gate of transistor 412 is configured to receive a negative differential signal (I-) from connection 407. The gate of transistor 411 may be further connected to one side of resistor 422, and the gate of transistor 412 may be further connected to one side of resistor 424. The other sides of resistors 422 and 424 may be connected together and connected to a bias voltage Vbias_I. The bias voltage Vbias_I may be provided by a bias circuit (not shown) to provide selected gain, noise figure, and linearity performance.

[0080] The gate of transistor 413 is configured to receive the control signal Ictrl, and the gate of transistor 419 is configured to receive the control signal Ictrl. The control signal Ictrl can be generated by data processor 210. Figure 2C (or provided by another controller.)

[0081] The gates of transistors 414 and 418 are configured to receive signal SWPi. The gates of transistors 416 and 417 are configured to receive signal SWNi. Signals SWPi and SWNi can be processed by data processor 210. Figure 2C Alternatively, it may be provided by another controller. In an exemplary embodiment, control signals SWPi and SWNi control the polarity of the RF signal processed by the corresponding transistor, and control signal Ictrl controls whether a particular instance of the I VGA amplifies the input signal.

[0082] In an exemplary embodiment, inductor 453 is located at the output of VGA 410 across connections 452 and 454. Inductor 453 may be a center-tapped inductor, with the center tap connected to the system voltage VDD. These components may include a bias network. In other examples, additional components are implemented for biasing the output of VGA 410, such as the drains of transistors 414, 416, 417, and 418 in the illustrated example.

[0083] In an exemplary embodiment, the Q VGA 430 may include transistors 431, 432, 433, 434, 436, 437, 438, and 439. Figure 4 In the example shown, transistors 431, 432, 433, 434, 436, 437, 438, and 439 are all N-type field-effect transistors (N-FETs). However, transistors 431, 432, 433, 434, 436, 437, 438, and 439 may alternatively be P-type FETs, or may be fabricated using other manufacturing techniques and processes.

[0084] The drain of each of transistors 433 and 439 is connected to the system voltage VDD. The drain of transistor 434 is connected to the drain of transistor 437, and the drains of both transistors are connected to node 446 and connection 456. The drain of transistor 436 is connected to the drain of transistor 438, and the drains of both transistors are connected to node 448 and connection 458. Selectively enabling transistors 434 and 438 or transistors 436 and 437 can maintain or toggle the polarity of the signal passing through VGA 430 (in an instance).

[0085] The sources of transistors 433, 434, and 436 are connected together and then connected to the drain of transistor 431. The sources of transistors 437, 438, and 439 are connected together and then connected to the drain of transistor 432. The sources of transistors 431 and 432 are connected to system ground. Transistors 431 and 432 can be configured as amplifying transistors. Transistors 434, 436, 437, and 438 can be configured in a cascode configuration and / or configured as switching transistors.

[0086] The gate of transistor 431 is configured to receive a positive differential signal (Q+) from connection 408, and the gate of transistor 432 is configured to receive a negative differential signal (Q-) from connection 409. The gate of transistor 431 may be further connected to one side of resistor 442, and the gate of transistor 432 may be further connected to one side of resistor 444. The other sides of resistors 442 and 444 may be connected together and connected to a bias voltage Vbias_Q. The bias voltage Vbias_Q may be provided by a bias circuit (not shown) to provide selected gain, noise figure, and linearity performance.

[0087] The gate of transistor 433 is configured to receive the control signal Qctrl, and the gate of transistor 439 is configured to receive the control signal Qctrl. The control signal Qctrl can be controlled by data processor 210. Figure 2C (or provided by another controller.)

[0088] The gates of transistors 434 and 438 are configured to receive signal SWPq. The gates of transistors 436 and 437 are configured to receive signal SWNq. Signals SWNq and SWPq can be processed by data processor 210. Figure 2C Alternatively, it may be provided by another controller. In an exemplary embodiment, control signals SWNq and SWPq control the polarity of the RF signal processed by the corresponding transistor, and control signal Qctrl controls whether a specific instance of the corresponding Q VGA amplifies the input signal.

[0089] In an exemplary embodiment, inductor 457 is located at the output of the Q VGA 430 across connections 456 and 458. Inductor 457 may be a center-tapped inductor, with the center tap connected to the system voltage VDD. These components may include a bias network. In other examples, additional components are implemented for biasing the output of the VGA 430, such as the drains of transistors 434, 436, 437, and 438 in the illustrated example.

[0090] To provide different amplification levels to the signals on connections 406, 407, 408, and 409, the I VGA 410 and Q VGA 430 can be one instance of a plurality of I VGA and Q VGA instances. For example, to provide different amplification levels, each instance of the I VGA and Q VGA can be weighted. Example weightings can be binary weighting, thermometer decoding, logarithmic weighting, etc. In an example binary weighting scheme with five (5)-bit resolution, for example only, the amplification levels can correspond to x1, 2x, 4x, 8x, and 16x. Providing different weights for each instance of the I VGA and Q VGA can be implemented in various ways, such as with transistors of different sizes across a plurality of instances of the I VGA 410 and Q VGA 430. To control the amount of amplification provided, control signals Ictrl and Qctrl can be used, for example, to enable or disable certain instances of these instances. The outputs of all instances of the I VGA can be coupled to connections 452 and 454 and inductor 453 (or other bias network). The outputs of all instances of the Q VGA can be coupled to connections 456 and 458, as well as inductor 457 (or other bias networks).

[0091] A positive differential signal I+ in phase is provided at connection 452, a negative differential signal I- in phase is provided at connection 454, a positive differential signal Q+ in quadrature is provided at connection 456, and a negative differential signal Q- in quadrature is provided at connection 458. However, as described above, the I and Q naming conventions are used for ease of reference, and the I and Q signals are not provided by the VGA in a quadrature phase-shift configuration. However, the amplitudes of the I and Q signals may have been adjusted by the VGA so that the combinational circuit 470 outputs appropriately phase-shifted signals accordingly.

[0092] In an exemplary embodiment, the combinational circuit 470 is a passive structure. The combinational circuit 470 may be configured as a QAF including resistors 472 and 476, inductor 474 and 478, capacitor 477 and capacitor 479.

[0093] A resistor is connected between nodes 471 and 481. A resistor 476 is connected between nodes 482 and 473. An inductor 474 is connected between nodes 484 and 486. An inductor 478 is connected between nodes 487 and 488. A capacitor 477 is connected between nodes 471 and 484; and a capacitor 479 is connected between nodes 488 and 473.

[0094] In an exemplary embodiment, node 481 is connected to node 487, and node 482 is connected to node 486. Node 484 is connected to the positive (+) output terminal on connection 466, and node 488 is connected to the negative (-) output terminal on connection 468. Alternatively, other configurations of the QAF may be implemented, such as where the connections between inductors 474 and 478, between capacitors 477 and 479, and between resistors 472 and 476 are different.

[0095] In an exemplary embodiment, the in-phase positive signal on connection 452 is provided to capacitor 461 and then to node 471, and the in-phase negative signal on connection 454 is provided to capacitor 463 and then to node 482.

[0096] In an exemplary embodiment, a quadrature positive signal on connection 456 is provided to capacitor 462 and then to node 481, and a quadrature negative signal on connection 458 is provided to capacitor 464 and then to node 473. In some examples, capacitors 461 to 464 are DC blocking capacitors and / or all have approximately the same value.

[0097] In an exemplary embodiment, I VGA 410 selectively adjusts the amplitudes of the I+ and I- signals on connections 406 and 407, and provides amplitude-adjusted I+ and I- signals on connections 452 and 454. In an exemplary embodiment, Q VGA 430 selectively adjusts the amplitudes of the Q+ and Q- signals on connections 408 and 409, and provides amplitude-adjusted Q+ and Q- signals on connections 456 and 458.

[0098] In an exemplary embodiment, the phase shift of the (+) signal occurs at the output 466 of the combinational circuit 470, wherein the I+ signal on connection 452 is combined with the Q+ signal on connection 456 and provided at the output of the combinational circuit 470 on connection 466. The signal on connection 466 may represent the vector sum of the I+ signal on connection 452 and the Q+ signal on connection 456 (even if there is no quadrature phase difference at the output of the VGA), as described below, wherein the resulting (+) signal on connection 466 is phase-shifted relative to the (+) signal on connection 404.

[0099] In an exemplary embodiment, the phase shift of the (-) signal occurs at the output 468 of the combinational circuit 470, where the I- signal on connection 454 is combined with the Q- signal on connection 458 and provided at the output of QAF 470 on connection 468. The signal on connection 468 can represent the vector sum of the I- signal on connection 454 and the Q- signal on connection 458 (even if there is no quadrature phase difference at the VGA output), as described below, where the resulting (-) signal on connection 468 is phase-shifted relative to the (-) signal on connection 405. A differential embodiment is presented herein, but a single-ended embodiment may be used alternatively.

[0100] Figure 5 yes Figure 4 A graphical illustration of the operation of the phase shifter circuit 400. In an exemplary embodiment, Figure 500 shows a graph including a horizontal axis of in-phase (x, -x) and an orthogonal vertical axis (y, -y).

[0101] For illustrative purposes only Figure 4 The I1+ signal on connection 452 is represented by point 502, and the Q1+ signal on connection 456 is represented by point 504. Although the outputs of VGA 410 and 430 do not have a quadrature phase difference, as shown in Figure 500, the combination of the I+ and Q+ signals by the combination circuit 470 (e.g., the output of the combination circuit 470) can be represented by a vector with an end at point 506. This vector has a first phase (θ1) generated by the phase shifter circuit 400 based on the amplitudes of the signals on connections 452 and 456. Similarly, the combination circuit 470 can combine the I- signal on connection 454 with the Q- signal on connection 458 to generate a negative output signal with a first phase (θ1).

[0102] In an exemplary embodiment, phase shifter circuit 400 may generate another phase signal, whereby the I2+ signal on connection 452 is represented by point 522, and the Q2+ signal on connection 456 is represented by point 524. The combination of these signals by combination circuit 470 (e.g., the output of combination circuit 470) may be represented by a vector having an end at point 526. This vector has a second phase (θ2) generated by phase shifter circuit 400 based on the amplitudes of the signals on connections 452 and 456. The second phase (θ2) may differ from the first phase (θ2). In an exemplary embodiment, multiple instances of phase shifter circuit 400 may be present in circuit 300 (… Figure 3This is implemented in a transceiver, for example, to generate a beamformed signal. In the example, the phase shifter circuit 400 is implemented in each of the plurality of phased array elements 287, and sets the phase of the signal output from these phased array elements 287 as described above to form a desired transmit or receive beam. For example, the first phased array element 287 may output a signal with phase θ1, and the second phased array element 287 may output a signal with phase θ2.

[0103] Figure 6 This is a flowchart 600 illustrating an example of the operation of a method for phase shifting. The blocks in method 600 may be executed in the order shown or not, and in some embodiments, they may be executed at least partially in parallel.

[0104] In block 602, the input signal is split into a first part and a second part, and an active variable gain amplifier (VGA) is used to adjust the amplitude of these two parts to create the desired amplitude. For example, I VGA 410 and Q VGA 430 adjust the amplitude of signals from connections 406 and 408, which are split from the input signal at connection 404 to create the desired amplitude.

[0105] In block 604, the first and second portions of the amplification are biased. For example, center-tapped inductors 453 and 457 can bias the outputs of I VGA 410 and Q VGA 430.

[0106] In block 606, an orthogonal full-pass filter is used to generate a phase-shifted signal based on a first and second portion of the biased amplified signal to obtain a desired phase shift (e.g., compared to the input signal and / or to the signal output from another phase shifter in the system). For example, the QAF 470 may receive input signals from I VGA 410 and Q VGA 430 and generate an output signal at connection 466 that has a desired phase shift, for example, compared to the signal at connection 404.

[0107] Figure 7 This is a functional block diagram of an apparatus 700 for phase-shift processing. Apparatus 700 includes components 702 for splitting an input signal into a first part and a second part and using a variable gain amplifier (VGA) to adjust the amplitudes of these two parts to create a desired amplitude. In some embodiments, the components 702 for splitting the input signal into a first part and a second part and using a variable gain amplifier (VGA) to adjust the amplitudes of these two parts to create a desired amplitude may be configured to perform method 600 (…). Figure 6One or more of the functions described in operation block 602. In an exemplary embodiment, component 702 for splitting the input signal into a first part and a second part and using a variable gain amplifier (VGA) to adjust the amplitude of the two parts to create a desired amplitude may include an input matching network 401 configured to split the signal on connection 404 such that I VGA 410 and Q VGA 430 can amplify the input signal to create the desired amplitude.

[0108] The apparatus 700 may further include a component 704 for biasing the first and second portions of the amplification. In some embodiments, the component 704 for biasing the first and second portions of the amplification may be configured to perform method 600. Figure 6 One or more of the functions described in operation block 604. In an exemplary embodiment, component 704 for biasing the first and second portions of the amplification may include center-tapped inductors 453 and 457 configured to bias the outputs of the I VGA 410 and Q VGA 430.

[0109] Apparatus 700 may further include component 706 for generating a phase-shifted signal using a first and second portion of a biased amplified quadrature full-pass filter to obtain a desired phase. In some embodiments, component 706 for generating a phase-shifted signal using a first and second portion of a biased amplified quadrature full-pass filter to obtain a desired phase may be configured to perform method 600. Figure 6 One or more of the functions described in operation block 606. In an exemplary embodiment, component 706 for generating a phase-shifted signal to obtain a desired phase using an orthogonal full-pass filter based on a biased amplified first and second portions may include a QAF 470 configured to receive input signals from I VGA 410 and Q VGA 430 and generate an output signal with a desired phase shift at connection 466 (e.g., compared to a signal at connection 404 or compared to a signal output from another phase shifter or a means for phase-shifting processing).

[0110] Compared to previous phase shifters, some of the example phase shifters described above can reduce power and / or area. For example, the described phase shifters can be smaller and consume less power, but provide similar performance. The example phase shifters may also exhibit less loss, provide higher resolution, and / or provide broadband performance. In some transceiver designs, a phase shifter configured as described above can be used to set the phase of the transmitted signal, and another phase shifter configured as described above can be used to set the phase of the received signal. In some such designs, having similar phase shifters for transmitting and receiving can simplify the design and / or improve the ability to optimize performance. For example, the receive phase shifter can be optimized for a small area and / or a good noise figure. As another example, the transmit phase shifter can be optimized for good linearity.

[0111] The QAF included in some of the example phase shifters described above can be broadband and / or insensitive to the Q of the inductors or capacitors therein, and potentially efficient in terms of area. When used in a receiver chain, the QAF at the output of the phase shifter allows noise in the passive network to be distributed as amplifier gain, thereby reducing NF.

[0112] Some of the example configurations described above can be used in 3-bit or 5-bit phase shifters.

[0113] Specific implementation examples are described in the following numbered clauses: 1. A phase shifter comprising: an input matching network; a vector modulator connected to the input matching network and configured to change the amplitude of a signal provided by the input matching network; a bias network coupled to an output of the vector modulator; and a combination circuit connected to the output of the vector modulator and configured to generate a first phase (θ1) signal from the output of the vector modulator.

[0114] 2. The phase shifter according to Clause 1, wherein the vector modulator is an active device.

[0115] 3. The phase shifter according to any one of Clauses 1 or 2, wherein the combined circuit is a quadrature all-pass filter (QAF).

[0116] 4. The phase shifter according to Clause 3, wherein the QAF is a passive device.

[0117] 5. The phase shifter according to any one of Clauses 2 to 4, wherein the vector modulator comprises an in-phase variable gain amplifier and a quadrature variable gain amplifier.

[0118] 6. A phase shifter according to any one of clauses 2 to 5, wherein the vector modulator provides an in-phase positive differential signal (I+), an in-phase negative differential signal (I-), a quadrature positive differential signal (Q+), and a quadrature negative differential signal (Q-), wherein the in-phase positive differential signal (I+), the quadrature positive differential signal (Q+), the in-phase negative differential signal (I-), and the quadrature negative differential signal (Q-) are combined to generate a signal having a first phase (θ1) determined by selective amplification provided by the vector modulator.

[0119] 7. The phase shifter according to any one of clauses 2 to 6, wherein the first phase (θ1) can be changed to a second phase (θ2) by adjusting the amplification provided by the vector modulator.

[0120] 8. The phase shifter as described in Clause 7, wherein (θ1) and (θ2) are different.

[0121] 9. The phase shifter according to any one of clauses 3 to 6, wherein the combining circuit is configured to combine the in-phase positive differential signal (I+) with the quadrature positive differential signal (Q+) to generate a positive output signal having the first phase (θ1).

[0122] 10. The phase shifter according to any one of clauses 3 to 6, wherein the combining circuit is configured to combine the in-phase negative differential signal (I-) with the quadrature negative differential signal (Q-) to generate a negative output signal having the first phase (θ1).

[0123] 11. The phase shifter according to any one of Clauses 5 to 10, wherein the in-phase variable gain amplifier and the quadrature variable gain amplifier each comprise a plurality of instances configured to provide different amplification levels.

[0124] 12. The phase shifter according to any one of Clauses 1 to 12, wherein the bias network includes a system voltage source connected to the center tap of an inductive element.

[0125] 13. A method for phase shifting, the method comprising: dividing an input signal into a first portion and a second portion, and adjusting the amplitudes of the first portion and the second portion; biasing the amplitude-adjusted first portion and the amplitude-adjusted second portion; and passively combining the amplitude-adjusted first portion and the amplitude-adjusted second portion to generate a first phase (θ1) signal.

[0126] 14. The method according to Clause 13, wherein adjusting the amplitude of the first portion and the second portion includes using an active variable gain amplifier (VGA) to actively adjust the amplitude of the first portion and the second portion.

[0127] 15. The method according to Clause 14, wherein the active adjustment further comprises selectively amplifying the in-phase positive differential signal (I+), the in-phase negative differential signal (I-), the quadrature positive differential signal (Q+), and the quadrature negative differential signal (Q-).

[0128] 16. The method according to any one of Clauses 13 to 15, wherein the passive ground combination is performed by a passive orthogonal all-pass filter (QAF).

[0129] 17. The method according to any one of clauses 13 to 16, the method further comprising passively combining the in-phase positive differential signal (I+) with the quadrature positive differential signal (Q+) to generate a positive output signal having the first phase (θ1).

[0130] 18. The method according to any one of clauses 13 to 16, the method further comprising passively combining the in-phase negative differential signal (I-) with the quadrature negative differential signal (Q-) to generate a negative output signal having the first phase (θ1).

[0131] 19. The method according to any one of Clauses 13 to 18, wherein the biasing further comprises biasing the amplitude-adjusted first portion and the amplitude-adjusted second portion using a system voltage source connected to the center tap of the inductor element.

[0132] 20. An apparatus comprising: means for dividing an input signal into a first portion and a second portion and actively adjusting the amplitudes of the first portion and the second portion; means for biasing the amplitude-adjusted first portion and the amplitude-adjusted second portion; and means for passively combining the amplitude-adjusted first portion and the amplitude-adjusted second portion using a passive combiner to generate a first phase (θ1) signal.

[0133] 21. The device according to Clause 20, wherein the component for active adjustment further includes components for selectively amplifying the in-phase positive differential signal (I+), the in-phase negative differential signal (I-), the quadrature positive differential signal (Q+), and the quadrature negative differential signal (Q-).

[0134] 22. The device according to any one of clauses 20 or 21, wherein the component for passively combining includes a component for passively combining the in-phase positive differential signal (I+) with the quadrature positive differential signal (Q+) to generate a positive output signal having the first phase (θ1).

[0135] 23. The device according to any one of Clauses 20 to 21, wherein the component for passively combining includes a component for passively combining the in-phase negative differential signal (I-) with the quadrature negative differential signal (Q-) to generate a negative output signal having the first phase (θ1).

[0136] 24. A phase shifter comprising: an input matching network coupled to an input of the phase shifter; a variable gain amplifier, wherein the output of the input matching network is coupled to the gate of an amplifying transistor in the variable gain amplifier; and a quadrature all-pass filter (QAF) coupled to the output of the variable gain amplifier and to the output of the phase shifter.

[0137] 25. The phase shifter according to Clause 24, wherein the QAF is coupled to the drain of a transistor in the variable gain amplifier having a cascode or switched transistor configuration.

[0138] 26. The phase shifter according to any one of Clauses 24 or 25, the phase shifter comprising a plurality of variable gain amplifiers coupled to the output of the input matching network, each of the plurality of variable gain amplifiers including an output coupled to the QAF.

[0139] 27. The phase shifter according to Clause 26, the phase shifter further comprising a plurality of capacitors coupled between the respective outputs of the plurality of variable gain amplifiers and the QAF, the plurality of capacitors having substantially the same value.

[0140] 28. The phase shifter according to Clause 24, wherein the variable gain amplifier includes a second transistor having a drain, a gate, and a source, the source of the second transistor being coupled to the drain of the amplifying transistor, the drain of the second transistor being coupled to a power supply voltage, and the gate of the second transistor being coupled to a control signal.

[0141] 29. The phase shifter according to Clause 28, the phase shifter further comprising a center-tapped inductor coupled to the output of the variable gain amplifier.

[0142] 30. The phase shifter according to any one of clauses 24 to 29, wherein the phase shifter is included in a phased array element of a phased array configured to operate at frequencies in the range of 7 GHz to 24 GHz.

[0143] The circuit architecture described in this article can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described in this article can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0144] The apparatus for implementing the circuit described herein may be a standalone device or part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RF IC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a mobile phone or mobile unit, (vii) and so on.

[0145] While selected aspects have been illustrated and described in detail, it should be understood that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims

1. A phase shifter, the phase shifter comprising: Input matching network; A vector modulator, connected to the input matching network, is configured to change the amplitude of a signal provided by the input matching network; A bias network, which is coupled to the output of the vector modulator; and A combinational circuit connected to the output of the vector modulator, the combinational circuit being configured to generate a first phase (θ1) signal from the output of the vector modulator.

2. The phase shifter according to claim 1, wherein the vector modulator is an active device.

3. The phase shifter according to claim 1, wherein the combined circuit is a quadrature all-pass filter (QAF).

4. The phase shifter according to claim 3, wherein the QAF is a passive device.

5. The phase shifter of claim 4, wherein the vector modulator comprises an in-phase variable gain amplifier and a quadrature variable gain amplifier.

6. The phase shifter of claim 1, wherein the vector modulator provides an in-phase positive differential signal (I+), an in-phase negative differential signal (I-), a quadrature positive differential signal (Q+), and a quadrature negative differential signal (Q-), wherein the in-phase positive differential signal (I+), the quadrature positive differential signal (Q+), the in-phase negative differential signal (I-), and the quadrature negative differential signal (Q-) are combined to generate a signal having a first phase (θ1) determined by selective amplification provided by the vector modulator.

7. The phase shifter of claim 6, wherein the first phase (θ1) can be changed to a second phase (θ2) by adjusting the amplification provided by the vector modulator.

8. The phase shifter according to claim 7, wherein (θ1) and (θ2) are different.

9. The phase shifter of claim 6, wherein the combination circuit is configured to combine the in-phase positive differential signal (I+) with the quadrature positive differential signal (Q+) to generate a positive output signal having the first phase (θ1).

10. The phase shifter of claim 6, wherein the combination circuit is configured to combine the in-phase negative differential signal (I-) with the quadrature negative differential signal (Q-) to generate a negative output signal having the first phase (θ1).

11. The phase shifter of claim 5, wherein the in-phase variable gain amplifier and the quadrature variable gain amplifier each comprise a plurality of instances configured to provide different amplification levels.

12. The phase shifter of claim 1, wherein the bias network comprises a system voltage source connected to the center tap of the inductor element.

13. A method for phase shifting, the method comprising: The input signal is divided into a first part and a second part, and the amplitudes of the first part and the second part are adjusted. The first portion and the second portion after amplitude adjustment are biased; as well as The amplitude-adjusted first portion and the amplitude-adjusted second portion are passively combined to generate a first phase (θ1) signal.

14. The method of claim 13, wherein adjusting the amplitudes of the first portion and the second portion comprises using an active variable gain amplifier (VGA) to actively adjust the amplitudes of the first portion and the second portion.

15. The method of claim 14, wherein the active adjustment further comprises selectively amplifying the in-phase positive differential signal (I+), the in-phase negative differential signal (I-), the quadrature positive differential signal (Q+), and the quadrature negative differential signal (Q-).

16. The method of claim 15, wherein the passive ground combination is performed by a passive orthogonal all-pass filter (QAF).

17. The method of claim 16, further comprising passively combining the in-phase positive differential signal (I+) with the quadrature positive differential signal (Q+) to generate a positive output signal having the first phase (θ1).

18. The method of claim 16, further comprising passively combining the in-phase negative differential signal (I-) with the quadrature negative differential signal (Q-) to generate a negative output signal having the first phase (θ1).

19. The method of claim 13, wherein the biasing further comprises biasing the amplitude-adjusted first portion and the amplitude-adjusted second portion using a system voltage source connected to the center tap of the inductor element.

20. A device, the device comprising: A component for dividing an input signal into a first part and a second part and actively adjusting the amplitude of the first part and the second part; A component for biasing the first portion and the second portion after amplitude adjustment; and A component for passively combining the amplitude-adjusted first portion with the amplitude-adjusted second portion using a passive combiner to generate a first phase (θ1) signal.

21. The device of claim 20, wherein the component for active adjustment further comprises a component for selectively amplifying the in-phase positive differential signal (I+), the in-phase negative differential signal (I-), the quadrature positive differential signal (Q+), and the quadrature negative differential signal (Q-).

22. The device of claim 21, wherein the component for passively combining includes a component for passively combining the in-phase positive differential signal (I+) with the quadrature positive differential signal (Q+) to generate a positive output signal having the first phase (θ1).

23. The device of claim 21, wherein the component for passively combining includes a component for passively combining the in-phase negative differential signal (I-) with the quadrature negative differential signal (Q-) to generate a negative output signal having the first phase (θ1).

24. A phase shifter, the phase shifter comprising: An input matching network is coupled to the input of the phase shifter; A variable gain amplifier, wherein the output of the input matching network is coupled to the gate of the amplifying transistor in the variable gain amplifier; and An orthogonal full-pass filter (QAF) is coupled to the output of the variable gain amplifier and to the output of the phase shifter.

25. The phase shifter of claim 24, wherein the QAF is coupled to the drain of a transistor in the variable gain amplifier having a cascode or switch transistor configuration.

26. The phase shifter of claim 24, the phase shifter comprising a plurality of variable gain amplifiers coupled to the output of the input matching network, each of the plurality of variable gain amplifiers including an output coupled to the QAF.

27. The phase shifter of claim 26, further comprising a plurality of capacitors coupled between respective outputs of the plurality of variable gain amplifiers and the QAF, the plurality of capacitors having substantially the same value.

28. The phase shifter of claim 24, wherein the variable gain amplifier includes a second transistor having a drain, a gate, and a source, the source of the second transistor being coupled to the drain of the amplifying transistor, the drain of the second transistor being coupled to a power supply voltage, and the gate of the second transistor being coupled to a control signal.

29. The phase shifter of claim 28, further comprising a center-tapped inductor coupled to the output of the variable gain amplifier.

30. The phase shifter of claim 24, wherein the phase shifter is included in a phased array element of a phased array configured to operate at frequencies in the range of 7 GHz to 24 GHz.

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