Integrated device including pillar shell interconnect and internal solder interconnect

Abstract

An integrated device, the integrated device comprising: a die substrate; a plurality of pads; a plurality of internal solder interconnects, the plurality of internal solder interconnects being coupled to the plurality of pads; and a plurality of cylindrical shell interconnects, the plurality of cylindrical shell interconnects being coupled to the plurality of internal solder interconnects. The plurality of internal solder interconnects are located between the plurality of pillar shell interconnects and the plurality of pads.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to U.S. Nonprovisional Application Serial No. 18 / 465,717, filed September 12, 2023, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0002] Various features are involved in integrated devices. Background Technology

[0003] A package may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. The performance of the package and its components may depend on the quality of the bonding points between the various components of the package. There has always been a need for packages that include robust and reliable bonding points between the components. Summary of the Invention

[0004] Various features are involved in integrated devices.

[0005] One example provides an integrated device comprising: a bare die substrate; a plurality of pads; a plurality of internal solder interconnects coupled to the plurality of pads; and a plurality of cylindrical interconnects coupled to the plurality of internal solder interconnects. The plurality of internal solder interconnects are located between the plurality of cylindrical interconnects and the plurality of pads.

[0006] Another example provides a package including: a substrate; and an integrated device coupled to the substrate via a plurality of solder interconnects. The integrated device includes a die substrate; a plurality of pads; a plurality of internal solder interconnects coupled to the pads; and a plurality of cylindrical interconnects coupled to the internal solder interconnects. The internal solder interconnects are located between the cylindrical interconnects and the pads. The solder interconnects are coupled to the cylindrical interconnects.

[0007] Another example provides a method for manufacturing an integrated device. The method provides an integrated device including a bare die substrate and a plurality of pads. The method couples a plurality of internal solder interconnects to the plurality of pads. The method forms a plurality of pillar-shell interconnects coupled to the plurality of internal solder interconnects such that the plurality of internal solder interconnects are located between the plurality of pillar-shell interconnects and the plurality of pads. Attached Figure Description

[0008] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0009] Figure 1 A cross-sectional profile of an exemplary integrated device is illustrated, which includes a cylindrical interconnect and an internal solder interconnect.

[0010] Figure 2 Exemplary cylindrical shell interconnects and internal solder interconnects are illustrated.

[0011] Figure 3 A cross-sectional plan view of an exemplary cylindrical shell interconnect and an internal solder interconnect is shown.

[0012] Figure 4 A cross-sectional profile view of an exemplary package including an integrated device comprising a cylindrical interconnect and an internal solder interconnect is illustrated.

[0013] Figure 5 A close-up view of an exemplary package including an integrated device comprising a cylindrical interconnect and an internal solder interconnect, wherein the integrated device is coupled to a substrate.

[0014] Figures 6A to 6G An exemplary process for manufacturing an integrated device is illustrated, which includes a cylindrical shell interconnect and an internal solder interconnect.

[0015] Figure 7 An exemplary flowchart illustrating a method for manufacturing an integrated device, the integrated device including a cylindrical shell interconnect and an internal solder interconnect.

[0016] Figure 8 An exemplary process for manufacturing a package including an integrated device comprising a cylindrical interconnect and an internal solder interconnect is illustrated.

[0017] Figure 9 An exemplary flowchart illustrating a method for manufacturing a package including an integrated device comprising a cylindrical interconnect and an internal solder interconnect.

[0018] Figure 10 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0019] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0020] This disclosure describes a package comprising: a substrate and an integrated device coupled to the substrate via a plurality of solder interconnects. The integrated device includes: a die substrate; a plurality of pads; a plurality of internal solder interconnects coupled to the pads; and a plurality of pillar-shell interconnects coupled to the internal solder interconnects. The plurality of internal solder interconnects are located between the pillar-shell interconnects and the pads. The plurality of solder interconnects are coupled to the pillar-shell interconnects. The integrated device may include a plurality of under-bump interconnects. The plurality of internal solder interconnects may be coupled to the pads via the under-bump interconnects. Using a plurality of internal solder interconnects provides a material that better absorbs stress during coupling of the integrated device to the substrate, which helps reduce stress transmitted to the dielectric layer of the integrated device. Lower stress on the dielectric layer of the integrated device means a lower likelihood of dielectric layer delamination, which enables a more robust and reliable bond between the integrated device and the substrate. More robust and reliable bonding provides a more reliable electrical path for current and / or signal travel between integrated devices and the substrate, which can improve the performance of integrated devices and packages.

[0021] An exemplary integrated device including cylindrical shell interconnects and internal solder interconnects. Figure 1 A cross-sectional profile of an integrated device 100 is illustrated, which includes pillar-shell interconnects and internal solder interconnects. The integrated device 100 includes a die portion 102, a plurality of pillar-shell interconnects 104, a plurality of solder interconnects 106, and a plurality of internal solder interconnects 108. The integrated device 100 may include flip chips. As will be further described below, the pillar-shell interconnects differ from block pillars because the pillar shells include hollow portions that are at least partially occupied by another material, such as solder. The pillars, pillar shells, and / or pillar interconnects may include copper.

[0022] The die portion 102 includes a die substrate 120, an interconnect portion 122, a passivation layer 103 (e.g., a first passivation layer), a passivation layer 105 (e.g., a second passivation layer), and a plurality of pads 107. The integrated device 100 may also include a plurality of under-bump metallized interconnects 109. The die substrate 120 may include silicon (Si). A plurality of cells and / or transistors (not shown) may be formed in and / or on the die substrate 120. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, fin FETs, and gate-all-around FETs. In some implementations, a front-end processing (FEOL) process may be used to fabricate the plurality of cells and / or transistors in and / or on the die substrate 120. The interconnect portion 122 is located above and coupled to the die substrate 120. The interconnect portion 122 may be a die interconnect portion. Interconnect portion 122 may be configured to be electrically coupled to a plurality of cells and / or transistors located in and / or above die substrate 120. Interconnect portion 122 may include at least one dielectric layer (e.g., a die dielectric layer) and a plurality of die interconnects (not shown), wherein the plurality of die interconnects are coupled to the plurality of cells and / or transistors. In some embodiments, back-to-office (BEOL) processes may be used to fabricate interconnect portion 122.

[0023] Passivation layer 103 is located above and coupled to interconnect portion 122. Passivation layer 105 is located above and coupled to passivation layer 103. Passivation layer 105 may comprise a different material than passivation layer 103. In some embodiments, passivation layer 103 and passivation layer 105 may be considered as a single passivation layer. In some embodiments, one or more passivation layers may be present. A plurality of pads 107 are located above interconnect portion 122. The plurality of pads 107 may be coupled to die interconnects of interconnect portion 122. A plurality of under-bump metallized interconnects 109 may be coupled to the plurality of pads 107. In some embodiments, passivation layer 103, passivation layer 105, plurality of pads 107 and / or plurality of under-bump metallized interconnects 109 may be considered as part of interconnect portion 122. In some implementations, the back-to-back (BEOL) process can be used to manufacture passivation layer 103, passivation layer 105, multiple pads 107 and / or multiple under-bump metallized interconnects 109.

[0024] Multiple internal solder interconnects 108 are coupled to multiple pads 107 (e.g., directly or indirectly). The multiple internal solder interconnects 108 can be coupled to the multiple pads 107 via at least a multiple under-bump metallized interconnects 109. In some embodiments, the multiple internal solder interconnects 108 can be coupled to the multiple pads 107 via at least a multiple metallized interconnects (e.g., redistribution interconnects) and a multiple under-bump metallized interconnects 109. Multiple shell interconnects 104 are coupled to the multiple internal solder interconnects 108. The multiple internal solder interconnects 108 may be located between the multiple pads 107 and the multiple shell interconnects 104 (e.g., vertically therebetween). The multiple internal solder interconnects 108 may be located between the multiple under-bump metallized interconnects 109 and the multiple shell interconnects 104 (e.g., vertically therebetween). Multiple solder interconnects 106 may be coupled to the multiple shell interconnects 104. The plurality of solder interconnects 106 and the plurality of internal solder interconnects 108 may be separate. For example, the plurality of solder interconnects 106 and the plurality of internal solder interconnects 108 may be separate when the plurality of solder interconnects 106 do not directly contact the plurality of internal solder interconnects 108. The plurality of internal solder interconnects 108 contact the plurality of under-bump metallized interconnects 109 and the plurality of pillar interconnects 104. In some embodiments, at least one of the pillar interconnects 104 may include a first material, and at least one of the internal solder interconnects 108 may include a second material different from the first material. For example, the pillar interconnects may include copper (e.g., the first material), and the internal solder interconnects may include solder (e.g., the second material).

[0025] Multiple cylindrical interconnects 104 include a first cylindrical interconnect 104a and a second cylindrical interconnect 104b. Multiple solder interconnects 106 include a first solder interconnect 106a and a second solder interconnect 106b. Multiple pads 107 include a first pad 107a and a second pad 107b. Multiple internal solder interconnects 108 include a first internal solder interconnect 108a and a second internal solder interconnect 108b. Multiple under-bump metallized interconnects 109 include a first under-bump metallized interconnect 109a and a second under-bump metallized interconnect 109b.

[0026] A first internal solder interconnect 108a is coupled to a first under-bump metallized interconnect 109a and a first pillar interconnect 104a. A first solder interconnect 106a is coupled to the first pillar interconnect 104a. The first pillar interconnect 104a includes a first side and a first top. The first top includes a first inner top surface and a first outer top surface. The first side may include a first inner side surface and a first outer side surface. The first internal solder interconnect 108a is contactable with the first inner lateral surface of the side of the first under-bump metallized interconnect 109a, the first inner top surface of the first pillar interconnect 104a, and the first inner top surface of the first top of the first pillar interconnect 104a. The first pillar interconnect 104a is contactable with the first under-bump metallized interconnect 109a, passivation layer 103, and / or passivation layer 105. The first solder interconnect 106a is contactable with the first outer top surface of the first top of the first pillar interconnect 104a. In some embodiments, the first internal solder interconnect 108a may contact the first under-bump interconnect 109a and / or the first pad 107a. In some embodiments, the first under-bump interconnect 109a may be considered part of the first pad 107a. In such instances, when the first internal solder interconnect 108a contacts the first under-bump interconnect 109a, the first internal solder interconnect 108a may be considered to contact the first pad 107a. Additionally, in at least some embodiments, when the first internal solder interconnect 108a is coupled to the first pad 107a, this may mean that the first internal solder interconnect 108a is directly coupled to the first pad 107a or indirectly coupled to the first pad 107a through at least the first under-bump interconnect 109a.

[0027] A second internal solder interconnect 108b is coupled to a second under-bump metallized interconnect 109b and a second cylindrical shell interconnect 104b. A second solder interconnect 106b is coupled to the second cylindrical shell interconnect 104b. The second cylindrical shell interconnect 104b includes a second side and a second top. The second top includes a second inner top surface and a second outer top surface. The second side may include a second inner side surface and a second outer side surface. The second internal solder interconnect 108b is contactable with the second inner surface of the side of the second under-bump metallized interconnect 109b, the second cylindrical shell interconnect 104b, and the second inner top surface of the second top of the second cylindrical shell interconnect 104b. The second cylindrical shell interconnect 104b is contactable with the second under-bump metallized interconnect 109b, passivation layer 103, and / or passivation layer 105. The second solder interconnect 106b is contactable with the second outer top surface of the second top of the second cylindrical shell interconnect 104b. In some embodiments, the second internal solder interconnect 108b may contact the second under-bump interconnect 109b and / or the second pad 107b. In some embodiments, the second under-bump interconnect 109b may be considered part of the second pad 107b. In such instances, when the second internal solder interconnect 108b contacts the second under-bump interconnect 109b, the second internal solder interconnect 108b may be considered to contact the second pad 107b. Additionally, in at least some embodiments, when the second internal solder interconnect 108b is coupled to the second pad 107b, this may mean that the second internal solder interconnect 108b is directly coupled to the second pad 107b or indirectly coupled to the second pad 107b through at least the second under-bump interconnect 109b.

[0028] As described above, the pillar interconnects and / or pillar interconnects may include copper, which has a higher Young's modulus than solder. Young's modulus describes the elastic properties of a material. Solder has a lower Young's modulus than copper, meaning it absorbs stress more effectively than copper. Furthermore, solder may also exhibit creep properties, which further contribute to stress absorption. Therefore, using multiple internal solder interconnects 108 provides a material that better absorbs stress during coupling of the integrated device 100 to the substrate, which helps reduce stress transferred to the dielectric layer of the integrated device 100. Lower stress on the dielectric layer of the integrated device means a lower likelihood of dielectric delamination, enabling a more robust and reliable bond between the integrated device 100 and the substrate (e.g., a package substrate). A more robust and reliable bond provides a more reliable electrical path for current and / or signal propagation between the integrated device 100 and the substrate, which improves the performance of the integrated device and package. It should be noted that the materials listed above are exemplary. Other embodiments may use materials, other types of materials, and / or other combinations of materials.

[0029] In some embodiments, additional interconnects may exist between the plurality of pads 107, the plurality of under-bump metallized interconnects 109, and the plurality of internal solder interconnects 108. In some embodiments, additional interconnects may exist between (i) the plurality of pads 107 and / or the plurality of under-bump metallized interconnects 109 and (ii) the plurality of internal solder interconnects 108 and / or the plurality of pillar shell interconnects 104. For example, metallized interconnects may exist between (i) the plurality of pads 107 and / or the plurality of under-bump metallized interconnects 109 and (ii) the plurality of internal solder interconnects 108 and / or the plurality of pillar shell interconnects 104. Examples of metallized interconnects include redistributed interconnects. When metallized interconnects are present, multiple internal solder interconnects 108 and / or multiple cylindrical shell interconnects 104 may be coupled to (e.g., directly coupled to) and / or contact the metallized interconnects, rather than being directly coupled to multiple pads 107 and / or multiple under-bump metallized interconnects 109.

[0030] Figure 2 An exemplary view of the cylindrical shell interconnect 204 and the internal solder interconnect 208 is shown. Figure 2 The cylindrical shell interconnect 204 can represent the source from Figure 1 Any cylindrical shell interconnect of multiple cylindrical shell interconnects. Figure 2 Internal solder interconnects 208 can represent from Figure 1 Any of the multiple internal solder interconnects. For example... Figure 2 As shown, the cylindrical interconnect 204 may at least partially surround the internal solder interconnect 208. The cylindrical interconnect 204 may laterally surround the internal solder interconnect 208. The cylindrical interconnect 204 may be in the shape of a hollow cylinder (e.g., the internal space of the cylindrical interconnect 204). The internal space of the cylindrical interconnect 204 may be at least partially occupied by the internal solder interconnect 208. The cylindrical interconnect 204 may include a side portion 240 and a top portion 242. The side portion 240 may include an inner surface and an outer surface. The top portion 242 may include an inner top surface and an outer top surface. The internal solder interconnect 208 may contact (i) the inner surface of the side portion 240 and (ii) the inner top surface of the top portion 242 of the cylindrical interconnect 204. Solder interconnects (e.g., from a plurality of solder interconnects 106) may contact (i) the outer top surface of the top 242 of the shell interconnect 204 and / or (ii) the outer surface of the side 240 of the shell interconnect 204.

[0031] The internal solder interconnect 208 may include a first internal solder interconnect portion 208a and a second internal solder interconnect portion 208b. The first internal solder interconnect portion 208a and the second internal solder interconnect portion 208b may be continuous and / or adjacent portions of the internal solder interconnect 208. The first internal solder interconnect portion 208a includes a first diameter and / or a first width. The second internal solder interconnect portion 208b includes a second diameter and / or a second width. The second diameter and / or the second width may be greater than the first diameter and / or the first width. The first internal solder interconnect portion 208a may be configured to contact under-bump interconnects from a plurality of under-bump interconnects 109 and / or pads from a plurality of pads 107. The second internal solder interconnect portion 208b may be configured to contact under-bump interconnects from a plurality of under-bump interconnects 109. The internal solder interconnect 208 may be considered to be at least partially located within the cylindrical shell interconnect 204, because... Figure 2 In the example, only some of the internal solder interconnects 208 are laterally surrounded by the shell interconnect 204. For example, the second internal solder interconnect portion 208b is not laterally surrounded by the shell interconnect 204.

[0032] Figure 3 A cross-sectional plan view of the cylindrical shell interconnect 204 and the internal solder interconnect 208 is shown. Figure 3 As shown, the planar cross-section extending through the cylindrical shell interconnect 204 includes an O-shape. However, the planar cross-section of the cylindrical shell interconnect 204 can have any type of shape, including elliptical and / or octagonal. The cylindrical shell interconnect 204 can have different dimensions.

[0033] The integrated device 100 can be implemented in a package. Figure 4 An example of a package 400 is illustrated, comprising a substrate 402, an integrated device 100, and an encapsulation layer 408. The substrate 402 includes at least one dielectric layer 420, a plurality of interconnects 422, a solder mask layer 426, and a solder mask layer 428. A plurality of solder interconnects 430 may be coupled to the plurality of interconnects 422 of the substrate 402. The integrated device 100 is coupled to a first surface (e.g., a top surface) of the substrate 402 via internal solder interconnects 108, a plurality of pillar-shell interconnects 104, and a plurality of solder interconnects 106. In some embodiments, the internal solder interconnects 108, the plurality of pillar-shell interconnects 104, and / or the plurality of solder interconnects 106 may be considered part of the integrated device. The encapsulation layer 408 may be located above and / or around the integrated device 100 and / or the substrate 402. The encapsulation layer 408 may at least partially encapsulate the integrated device 100. The encapsulation layer 408 may include molding materials, resins, and / or epoxy resins. Encapsulation layer 408 can be a component used for encapsulation. Encapsulation layer 408 can be provided by using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0034] Figure 4 An integrated device coupled to a substrate is illustrated. In some embodiments, the package may include two or more integrated devices coupled to the substrate. Each of the one or more integrated devices may include a plurality of internal solder interconnects, a plurality of pillar interconnects, and a plurality of solder interconnects.

[0035] Figure 5 An exemplary close-up view illustrating how an integrated device is coupled to a substrate is shown. Figure 5 A portion of a package 400 may be exemplified, including an integrated device 100 and a substrate 402. The integrated device 100 is coupled to the substrate 402 via a plurality of internal solder interconnects 108, a plurality of pillar shell interconnects 104, a plurality of solder interconnects 106, and a plurality of solder interconnects 506 (e.g., pre-solder interconnects).

[0036] like Figure 5 As shown, the first under-bump metallized interconnect 109a is coupled to the first pad 107a. The first internal solder interconnect 108a is coupled to the first under-bump metallized interconnect 109a and the first pillar interconnect 104a. The first pillar interconnect 104a is coupled to the first solder interconnect 106a. The first solder interconnect 106a is coupled to the first solder interconnect 506a. The first solder interconnect 506a is coupled to the first interconnect 422a of the substrate 402. The first solder interconnect 106a and the first solder interconnect 506a can be considered to be the same solder interconnect.

[0037] The second under-bump metallized interconnect 109b is coupled to the second pad 107b. The second internal solder interconnect 108b is coupled to the second under-bump metallized interconnect 109b and the second pillar interconnect 104b. The second pillar interconnect 104b is coupled to the second solder interconnect 106b. The second solder interconnect 106b is coupled to the second solder interconnect 506b. The second solder interconnect 506b is coupled to the second interconnect 422b of the substrate 402. The second solder interconnect 106b and the second solder interconnect 506b can be considered as the same solder interconnect.

[0038] The electrical path between the substrate of the integrated device 100 and the transistors may include a first interconnect 422a, a first solder interconnect 506a, a first solder interconnect 106a, a first pillar interconnect 104a, a first internal solder interconnect 108a, a first under-bump metallized interconnect 109a, a first pad 107a, and a plurality of die interconnects from the interconnect portion 122. In this case, additional interconnects may exist between the first pad 107a and the first internal solder interconnect 108a, and the electrical path may include those additional interconnects. For example, if there are additional metallized interconnects (e.g., redistributed interconnects) between the first pad 107a and the first internal solder interconnect 108a, the electrical path may include at least some of the additional metallized interconnects. It should be noted that different configurations of the integrated device may bypass the use of some interconnects. Thus, some interconnects of the integrated device may be optional.

[0039] An integrated device (e.g., 100) may include a bare die (e.g., a semiconductor bare die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors, and / or combinations thereof. An integrated device may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include an input / output (I / O) hub. An integrated device may include transistors. An integrated device may be an example of an electronic component and / or electronic device.

[0040] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 100) described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and chiplets may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes. In some embodiments, the chiplets and another chiplet of the package may be manufactured using the same or different technology nodes.

[0041] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require that specific technology node to be used. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0042] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0043] An integrated device with cylindrical shell interconnects and internal solder interconnects has been described. The method for manufacturing the integrated device will be described below.

[0044] Exemplary steps for manufacturing an integrated device including cylindrical shell interconnects and internal solder interconnects In some specific implementations, manufacturing integrated devices involves several processes. Figures 6A to 6G Exemplary steps for providing or manufacturing an integrated device including cylindrical interconnects and internal solder interconnects are illustrated. In some specific embodiments, Figures 6A to 6G The process can be used to provide or manufacture integrated device 100. However, Figures 6A to 6G The process can be used to manufacture any integrated device described in this disclosure.

[0045] It should be noted that Figures 6A to 6G The processes may be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0046] like Figure 6A As shown, Stage 1 illustrates the state after the integrated device has been provided and / or manufactured. The integrated device 100 may include a die portion 102. The die portion 102 may include a die substrate 120, interconnect portions 122 (e.g., die interconnect portions), passivation layers 103 and 105, and a plurality of pads 107. The integrated device 100 may include an exposed die (e.g., a semiconductor exposed die). Thus, in some embodiments, an exposed die may be provided at Stage 1, which includes a die substrate 120, interconnect portions 122 (e.g., die interconnect portions), at least one passivation layer (e.g., 103 and / or 105), and a plurality of pads 107. In some embodiments, the integrated device 100 is provided and / or manufactured as part of a wafer. As will be further described below, the integrated device may include additional components and / or other components that may be manufactured on the integrated device provided at Stage 1.

[0047] Phase 2 illustrates the state after a bump under-metallization layer 609 is formed over the die portion 102 of the integrated device 100. The bump under-metallization layer 609 may be coupled to and contact the passivation layer 105 and the plurality of pads 107. The bump under-metallization layer 609 may comprise a material different from the plurality of pads 107. The bump under-metallization layer 609 may be formed using a sputtering process.

[0048] like Figure 6B As shown, stage 3 illustrates the state after a photoresist layer 600 is formed over the die portion 102 and patterned to include a plurality of openings 601 in the photoresist layer 600. The photoresist layer 600 may be coated over the die portion 102. For example, the photoresist layer 600 may be coated over the under-bump metallization layer 609. A photolithography process may be used to form and define the pattern of the photoresist layer 600. For example, an exposure process and a development process may be used to form the plurality of openings 601 in the photoresist layer 600. The plurality of openings 601 may be located over a plurality of pads 107.

[0049] like Figure 6C As shown, stage 4 illustrates the state after forming a plurality of internal solder interconnects 108 and coupling them to a plurality of pads 107 via an under-bump metallization layer 609. The plurality of internal solder interconnects 108 can be formed using an electroplating process. The plurality of internal solder interconnects 108 may contact the under-bump metallization layer 609. When the under-bump metallization layer 609 is absent, the plurality of internal solder interconnects 108 may contact the plurality of pads 107. The plurality of internal solder interconnects 108 may be formed in a plurality of openings 601 in the photoresist layer 600.

[0050] like Figure 6D As shown, stage 5 illustrates the state after the plurality of openings 601 are further opened to form a plurality of openings 603. The size of the plurality of openings 603 may be larger than the size of the plurality of openings 601. The plurality of openings 603 may be formed in the photoresist layer 600 using another exposure and development process. The plurality of openings 603 may be located above the plurality of pads 107.

[0051] like Figure 6E As shown, stage 6 illustrates the state after the formation of a plurality of pillar interconnects 104. The plurality of pillar interconnects 104 may be formed in a plurality of openings 603 in the photoresist layer 600. The plurality of pillar interconnects 104 may be coupled to a plurality of internal solder interconnects 108. The plurality of pillar interconnects 104 may at least partially surround the plurality of internal solder interconnects 108. The plurality of pillar interconnects 104 may contact the plurality of internal solder interconnects 108. The plurality of pillar interconnects 104 may contact the under-bump metallization layer 609. When the under-bump metallization layer 609 is absent, the plurality of pillar interconnects 104 may contact the passivation layer 103 and / or passivation layer 105.

[0052] like Figure 6F As shown, stage 7 illustrates the state after forming a plurality of solder interconnects 106 and coupling the plurality of solder interconnects to a plurality of cylindrical shell interconnects 104. The plurality of solder interconnects 106 may be formed through a plurality of openings 603 in the photoresist layer 600. The plurality of solder interconnects 106 may be formed using an electroplating process.

[0053] like Figure 6G As shown, stage 8 illustrates the state after removing the photoresist layer 600 and performing a solder reflow process. Stage 8 can also illustrate the state after removing portions of the under-bump metallization layer 609 to form a plurality of under-bump interconnects 109, including a first under-bump interconnect 109a and a second under-bump interconnect 109b. An etching process can be used to selectively remove portions of the under-bump metallization layer 609. Stage 8 can illustrate an example of an integrated device 100 including a plurality of pillar interconnects and a plurality of internal solder interconnects.

[0054] An exemplary flowchart of a method for manufacturing an integrated device including cylindrical interconnects and internal solder interconnects. In some specific implementations, manufacturing integrated devices involves several processes. Figure 7 An exemplary flowchart illustrating a method 700 for providing or manufacturing an integrated device, the integrated device including pillar-shell interconnects and internal solder interconnects, is shown. In some specific embodiments, Figure 7 Method 700 can be used to provide or manufacture the products described in this disclosure. Figure 1 The integrated device 100. However, method 700 can be used to provide or manufacture any integrated device described in this disclosure.

[0055] It should be noted that Figure 7 The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some specific implementations, the order of the processes may be changed or modified.

[0056] The method (at 705) provides an integrated device comprising a die substrate, die interconnect portions, and multiple pads. Figure 6A Phase 1 illustrates and describes an example of the state after the integrated device has been provided and / or manufactured. The integrated device 100 may include a die portion 102. The die portion 102 may include a die substrate 120, interconnect portions 122, passivation layers 103 and 105, and a plurality of pads 107. The integrated device 100 may include an exposed die (e.g., a semiconductor exposed die). In some specific embodiments, the integrated device 100 is provided and / or manufactured as part of a wafer.

[0057] This method (at 710) forms a bump under-metallization layer over the integrated device. Figure 6A Phase 2 illustrates and describes an example of the state after a bump under-metallization layer 609 is formed over the die portion 102 of the integrated device 100. The bump under-metallization layer 609 may be coupled to and contact the passivation layer 105 and a plurality of pads 107. The bump under-metallization layer 609 may comprise a material different from the plurality of pads 107. The bump under-metallization layer 609 may be formed using a sputtering process.

[0058] This method (at 715) provides a photoresist layer over the integrated device. Figure 6B Stage 3 illustrates and describes an example of a state after a photoresist layer 600 is formed over the die portion 102 and patterned to include a plurality of openings 601 in the photoresist layer 600. The photoresist layer 600 may be coated over the die portion 102. For example, the photoresist layer 600 may be coated over the under-bump metallization layer 609. A photolithography process may be used to form and define the pattern of the photoresist layer 600. For example, an exposure and development process may be used to form a plurality of openings 601 in the photoresist layer 600. The plurality of openings 601 may be located over a plurality of pads 107.

[0059] This method (at 720) forms multiple internal solder interconnects coupled to multiple pads. Figure 6C Phase 4 illustrates and describes an example of the state after a plurality of internal solder interconnects 108 are formed and coupled to a plurality of pads 107 via an under-bump metallization layer 609. An electroplating process can be used to form the plurality of internal solder interconnects 108. The plurality of internal solder interconnects 108 may contact the under-bump metallization layer 609. When the under-bump metallization layer 609 is not present, the plurality of internal solder interconnects 108 may contact the plurality of pads 107. The plurality of internal solder interconnects 108 may be formed in a plurality of openings 601 in the photoresist layer 600.

[0060] This method (at 725) forms an opening in the photoresist layer. Figure 6D Stage 5 illustrates and describes an example after further opening multiple openings 601 to form multiple openings 603. The size of the multiple openings 603 may be larger than the size of the multiple openings 601. The multiple openings 603 may be formed in the photoresist layer 600 using another exposure and development process. The multiple openings 603 may be located above the multiple pads 107.

[0061] This method (at 730) forms multiple cylindrical shell interconnects coupled to multiple internal solder interconnects. Figure 6EStage 6 illustrates and describes an example of the state after the formation of a plurality of pillar interconnects 104. The plurality of pillar interconnects 104 may be formed in a plurality of openings 603 in the photoresist layer 600. The plurality of pillar interconnects 104 may be coupled to a plurality of internal solder interconnects 108. The plurality of pillar interconnects 104 may at least partially surround the plurality of internal solder interconnects 108. The plurality of pillar interconnects 104 may contact the plurality of internal solder interconnects 108. The plurality of pillar interconnects 104 may contact the under-bump metallization layer 609. When the under-bump metallization layer 609 is not present, the plurality of pillar interconnects 104 may contact the passivation layer 103 and / or passivation layer 105.

[0062] This method (at 735) forms multiple solder interconnects coupled to multiple cylindrical shell interconnects. Figure 6F Stage 7 illustrates and describes an example of the state after forming a plurality of solder interconnects 106 and coupling the plurality of solder interconnects to a plurality of cylindrical shell interconnects 104. The plurality of solder interconnects 106 may be formed through a plurality of openings 603 in a photoresist layer 600. An electroplating process may be used to form the plurality of solder interconnects 106.

[0063] This method (at 740) removes a portion of the photoresist layer and the under-bump metallization layer. Figure 6G Stage 8 illustrates and describes an example of the state after removing the photoresist layer 600 and performing a solder reflow process. Figure 6G Stage 8 can also illustrate the state after removing portions of the under-bump metallization layer 609 to form a plurality of under-bump metallization interconnects 109, including a first under-bump metallization interconnect 109a and a second under-bump metallization interconnect 109b. An etching process can be used to selectively remove portions of the under-bump metallization layer 609.

[0064] The integrated device (e.g., 100) described in this disclosure may be manufactured one at a time, or may be manufactured together as part of one or more wafers and subsequently diced into individual integrated devices.

[0065] An exemplary process for manufacturing a package including an integrated device, the integrated device including a cylindrical interconnect and an inner... Partial solder interconnects In some specific implementations, manufacturing the package involves several processes. Figure 8 Exemplary steps for providing or manufacturing a package including an integrated device comprising pillar-shell interconnects and internal solder interconnects are illustrated. In some specific embodiments, Figure 8 The process can be used to provide or manufacture Figure 4 The packaging component is 400. However, Figure 8 The process can be used to manufacture any of the packages described in this disclosure.

[0066] It should be noted that Figure 8 The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0067] like Figure 8 As shown, stage 1 illustrates the state after substrate 402 is provided. Substrate 402 includes at least one dielectric layer 420, a plurality of interconnects 422, a solder mask layer 426, and a solder mask layer 428. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS).

[0068] Phase 2 illustrates the state after the integrated device 100 is coupled to the substrate 402 via multiple internal solder interconnects 108, multiple cylindrical interconnects 104, and multiple solder interconnects 106. The integrated device 100 can be coupled to multiple interconnects 422 of the substrate 402 via the multiple internal solder interconnects 108, multiple cylindrical interconnects 104, and multiple solder interconnects 106. A solder reflow process can be used to couple the integrated device 100 to the substrate 402. Figure 5 An example of how an integrated device 100 can be coupled to a substrate 402 is illustrated. Different specific implementations may couple different components and / or devices to the substrate 402.

[0069] Phase 3 illustrates the state after an encapsulation layer 408 is provided (e.g., formed) over substrate 402. Encapsulation layer 408 may encapsulate integrated device 100. Encapsulation layer 408 may include molding materials, resins, and / or epoxy resins. Encapsulation layer 408 may be formed using compression molding, transfer molding, or liquid molding processes. Encapsulation layer 408 may be photoetchable. Encapsulation layer 408 may be a component used for encapsulation.

[0070] Phase 4 illustrates the state after multiple solder interconnects 430 are coupled to the substrate 402. A solder reflow process can be used to couple the multiple solder interconnects 430 to the substrate 402.

[0071] An exemplary flowchart of a method for manufacturing a package including an integrated device, the integrated device including a cylindrical shell. Connectors and internal solder interconnects In some specific implementations, manufacturing the package involves several processes. Figure 9 An exemplary flowchart illustrating a method 900 for providing or manufacturing a package including an integrated device comprising pillar-shell interconnects and internal solder interconnects is shown. In some specific embodiments, Figure 9 Method 900 can be used to provide or manufacture the product described in this disclosure. Figure 4Package 400. However, method 900 can be used to provide or manufacture any package (e.g., 400) described in this disclosure.

[0072] It should be noted that Figure 9 The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some specific implementations, the order of the processes may be changed or modified.

[0073] This method (at 905) provides a substrate (e.g., 402). The substrate 402 can be manufactured or supplied by a supplier. Different embodiments may use different processes to manufacture the substrate 402. Examples of processes that can be used to manufacture the substrate 402 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 402 includes at least one dielectric layer 420, a plurality of interconnects 422, a solder mask layer 426, and a solder mask layer 428. The substrate 402 may include an embedded trace substrate (ETS). In some embodiments, the substrate may be a core substrate. In some embodiments, at least one dielectric layer 420 may include a prepreg layer and / or polyimide. Figure 8 Phase 1 illustrates and describes an example of providing a substrate.

[0074] This method (at 910) couples an integrated device (e.g., 100) to a first surface of substrate 402. For example, integrated device 100 may be coupled to a first surface (e.g., the top surface) of substrate 402. Integrated device 100 is coupled to substrate 402 via a plurality of internal solder interconnects 108, a plurality of pillar interconnects 104, and a plurality of solder interconnects 106. A solder reflow process can be used to couple integrated device 100 to substrate 402. Figure 5 An example of how an integrated device 100 can be coupled to a substrate 402 is illustrated. Figure 8 Phase 2 illustrates and describes an example of coupling an integrated device to a substrate.

[0075] This method (at 915) forms an encapsulation layer (e.g., 408) over a substrate (e.g., 402). The encapsulation layer 408 may be provided and formed over and / or around the substrate 402 and the integrated device 100. The encapsulation layer 408 may include a molding compound, resin, and / or epoxy resin. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 408. The encapsulation layer 408 may be photoetchable. The encapsulation layer 408 may be a component for encapsulation. Figure 8 Stage 3 illustrates and describes an example of forming an encapsulation layer.

[0076] This method (at 920) couples multiple solder interconnects (e.g., 430) to substrate 402. A solder reflow process can be used to couple the multiple solder interconnects 430 to substrate 402. Figure 8Phase 4 illustrates and describes an example of coupling solder interconnects to a substrate.

[0077] The package (e.g., 400) described in this disclosure may be manufactured one at a time, or may be manufactured as part of one or more wafers and / or panels and then diced into individual packages.

[0078] Exemplary electronic devices Figure 10 Examples are illustrated of various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1002, laptop computer device 1004, fixed-location terminal device 1006, wearable device 1008, or motor vehicle 1010 may include device 1000 as described herein. For example, device 1000 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 10 The illustrated devices 1002, 1004, 1006, and 1008, as well as vehicle 1010, are merely exemplary. Other electronic devices may also feature device 1000, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0079] Figures 1 to 5 , Figures 6A to 6G and / or Figures 7 to 10 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 5 , Figures 6A to 6G and / or Figures 7 to 10 And its corresponding description in this disclosure is not limited to bare dies and / or ICs. In some specific implementations, Figures 1 to 5 , Figures 6A to 6G and / or Figures 7 to 10 The descriptions therein can be used to manufacture, create, provide, and / or produce equipment and / or integrated devices. In some specific implementations, equipment may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0080] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0081] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. An object coupled to another object may be coupled to at least a portion of another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "on top of" as used in the context of one component being on top of another component in this application can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component on top of second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or entirely located in the second component.As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "A plurality of" components may include all possible components or only some of all possible components. For example, if the device comprises ten components, the use of the term "a plurality of components" may refer to all ten components or only some of those ten components.

[0082] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0083] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0084] Further examples are described below to facilitate understanding of the invention.

[0085] Aspect 1: An integrated device comprising: a bare die substrate; a plurality of pads; a plurality of internal solder interconnects coupled to the plurality of pads; and a plurality of shell interconnects coupled to the plurality of internal solder interconnects, wherein the plurality of internal solder interconnects are located between the plurality of shell interconnects and the plurality of pads.

[0086] Aspect 2: The integrated device according to Aspect 1 further includes: a plurality of under-bump metallized interconnects coupled to the plurality of pads, wherein the plurality of internal solder interconnects are coupled to the plurality of pads through the plurality of under-bump metallized interconnects; and a plurality of solder interconnects coupled to the plurality of column shell interconnects, wherein the plurality of solder interconnects are separate from the plurality of internal solder interconnects.

[0087] Aspect 3: The integrated device according to aspects 1 to 2, wherein the plurality of internal solder interconnects are at least partially located inside the plurality of cylindrical shell interconnects, wherein the cylindrical shell interconnects from the plurality of cylindrical shell interconnects comprise a first material, and wherein the internal solder interconnects from the plurality of internal solder interconnects comprise a second material, the second material being different from the first material.

[0088] Aspect 4: The integrated device according to aspects 1 to 3, wherein the plurality of pads includes a first pad and a second pad, wherein the plurality of internal solder interconnects includes a first internal solder interconnect and a second internal solder interconnect, and wherein the plurality of shell interconnects includes a first shell interconnect and a second shell interconnect.

[0089] Aspect 5: The integrated device according to Aspect 4 further includes: a first under-bump metallized interconnect coupled to the first pad; and a second under-bump metallized interconnect coupled to the second pad, wherein a first internal solder interconnect is coupled to and contacts the first under-bump metallized interconnect and the first pillar shell interconnect, and wherein the second internal solder interconnect is coupled to and contacts the second under-bump metallized interconnect and the second pillar shell interconnect.

[0090] Aspect 6: The integrated device according to aspects 4 to 5, wherein the first internal solder interconnect is located between the first pad and the first pillar interconnect, and wherein the second internal solder interconnect is located between the second pad and the second pillar interconnect.

[0091] Aspect 7: The integrated device according to aspects 4 to 6, wherein the first pillar-shell interconnect and the second pillar-shell interconnect contact the passivation layer of the integrated device.

[0092] Aspect 8: The integrated device according to aspects 4 to 7 further includes a first solder interconnect, wherein the first cylindrical shell interconnect includes a first side and a first top, wherein the first top includes a first outer top surface and a first inner top surface, wherein the first inner solder interconnect contacts the first inner top surface, and wherein the first solder interconnect contacts the first outer top surface.

[0093] Aspect 9: The integrated device according to aspects 1 to 8 further includes a die interconnect portion coupled to the die substrate, wherein the plurality of pads are coupled to the die interconnect portion.

[0094] Aspect 10: The integrated device according to aspects 1 to 9, wherein the integrated device is a part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0095] Aspect 11: A package comprising: a substrate; and an integrated device coupled to the substrate via at least a plurality of solder interconnects, wherein the integrated device comprises: a die substrate; a plurality of pads; a plurality of internal solder interconnects coupled to the plurality of pads; and a plurality of shell interconnects coupled to the plurality of internal solder interconnects, wherein the plurality of internal solder interconnects are located between the plurality of shell interconnects and the plurality of pads, and wherein the plurality of solder interconnects are coupled to the plurality of shell interconnects.

[0096] Aspect 12: According to the package of aspect 11, the integrated device further includes a plurality of under-bump metallized interconnects coupled to the plurality of pads, wherein the plurality of internal solder interconnects are coupled to the plurality of pads through the plurality of under-bump metallized interconnects, and wherein the plurality of solder interconnects are separate from the plurality of internal solder interconnects.

[0097] Aspect 13: The package according to aspects 11 to 12, wherein the plurality of internal solder interconnects are at least partially located inside the plurality of cylindrical shell interconnects, wherein the cylindrical shell interconnects from the plurality of cylindrical shell interconnects comprise a first material, and wherein the internal solder interconnects from the plurality of internal solder interconnects comprise a second material, the second material being different from the first material.

[0098] Aspect 14: The package according to aspects 11 to 13, wherein the plurality of pads includes a first pad and a second pad, wherein the plurality of internal solder interconnects includes a first internal solder interconnect and a second internal solder interconnect, and wherein the plurality of shell interconnects includes a first shell interconnect and a second shell interconnect.

[0099] Aspect 15: The package according to aspect 14 further includes: a first under-bump metallized interconnect coupled to the first pad; and a second under-bump metallized interconnect coupled to the second pad, wherein the first internal solder interconnect is coupled to and contacts the first under-bump metallized interconnect and the first pillar shell interconnect, and wherein the second internal solder interconnect is coupled to and contacts the second under-bump metallized interconnect and the second pillar shell interconnect.

[0100] Aspect 16: The package according to aspects 14 to 15, wherein the first internal solder interconnect is located between the first pad and the first pillar shell interconnect, and wherein the second internal solder interconnect is located between the second pad and the second pillar shell interconnect.

[0101] Aspect 17: The package according to aspects 14 to 16, wherein the first pillar shell interconnect and the second pillar shell interconnect contact the passivation layer of the integrated device.

[0102] Aspect 18: The package according to aspects 14 to 17 further includes a first solder interconnect, wherein the first cylindrical shell interconnect includes a first side and a first top, wherein the first top includes a first outer top surface and a first inner top surface, wherein the first inner solder interconnect contacts the first inner top surface, and wherein the first solder interconnect contacts the first outer top surface.

[0103] Aspect 19: The package according to aspects 11 to 18, wherein the package is part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0104] Aspect 20: A method for manufacturing an integrated device. The method provides an integrated device including a bare die substrate and a plurality of pads. The method couples a plurality of internal solder interconnects to the plurality of pads. The method forms a plurality of cylindrical shell interconnects coupled to the plurality of internal solder interconnects such that the plurality of internal solder interconnects are located between the plurality of cylindrical shell interconnects and the plurality of pads.

[0105] Aspect 21: According to the method of aspect 20, the method further includes coupling a plurality of solder interconnects to the plurality of cylindrical shell interconnects.

[0106] Aspect 22: According to the method of aspect 21, wherein the plurality of solder interconnects and the plurality of internal solder interconnects are separate, and wherein the integrated device further includes a plurality of under-bump metallization interconnects coupled to the plurality of pads, wherein the plurality of internal solder interconnects are coupled to the plurality of pads through the plurality of under-bump metallization interconnects.

[0107] Aspect 23: According to the method of aspects 20 to 22, wherein the plurality of internal solder interconnects are at least partially located inside the plurality of cylindrical shell interconnects.

[0108] Aspect 24: The method according to aspects 20 to 23, wherein the plurality of pads includes a first pad and a second pad, wherein the plurality of internal solder interconnects includes a first internal solder interconnect and a second internal solder interconnect, and wherein the plurality of pillar interconnects includes a first pillar interconnect and a second pillar interconnect.

[0109] Aspect 25: The method according to aspect 24, the method further comprising: forming a first under-bump metallized interconnect coupled to the first pad; and forming a second under-bump metallized interconnect coupled to the second pad, wherein a first internal solder interconnect is coupled to and contacts the first under-bump metallized interconnect and the first pillar shell interconnect, and wherein the second internal solder interconnect is coupled to and contacts the second under-bump metallized interconnect and the second pillar shell interconnect.

[0110] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated device, the integrated device comprising: bare chip substrate; Multiple pads; Multiple internal solder interconnects coupled to multiple pads; and Multiple cylindrical shell interconnects coupled to multiple internal solder interconnects. The plurality of internal solder interconnects are located between the plurality of cylindrical shell interconnects and the plurality of pads.

2. The integrated device according to claim 1, further comprising: Multiple under-bump metallized interconnects coupled to multiple pads, wherein multiple internal solder interconnects are coupled to the multiple pads through the multiple under-bump metallized interconnects; and A plurality of solder interconnects coupled to a plurality of cylindrical shell interconnects, wherein the plurality of solder interconnects are separate from the plurality of internal solder interconnects.

3. The integrated device according to claim 1, The plurality of internal solder interconnects are at least partially located inside the plurality of cylindrical shell interconnects. The cylindrical shell interconnects from the plurality of cylindrical shell interconnects include a first material, and The internal solder interconnects from the plurality of internal solder interconnects include a second material, which is different from the first material.

4. The integrated device according to claim 1, The plurality of pads includes a first pad and a second pad. The plurality of internal solder interconnects includes a first internal solder interconnect and a second internal solder interconnect, and The plurality of cylindrical shell interconnects includes a first cylindrical shell interconnect and a second cylindrical shell interconnect.

5. The integrated device according to claim 4, further comprising: The first under-bump metallized interconnect is coupled to the first pad; and The second under-bump metallized interconnect is coupled to the second pad. The first internal solder interconnect is coupled to and contacts the first under-bump metallized interconnect and the first pillar shell interconnect, and The second internal solder interconnect is coupled to and contacts the second bump under-metallized interconnect and the second column shell interconnect.

6. The integrated device according to claim 4, The first internal solder interconnect is located between the first pad and the first cylindrical shell interconnect, and The second internal solder interconnect is located between the second pad and the second cylindrical shell interconnect.

7. The integrated device of claim 4, wherein the first pillar-shell interconnect and the second pillar-shell interconnect contact the passivation layer of the integrated device.

8. The integrated device of claim 4, further comprising a first solder interconnect. The first cylindrical shell interconnect includes a first side and a first top. The first top includes a first outer top surface and a first inner top surface. The first internal solder interconnect contacts the first inner top surface, and The first solder interconnect contacts the first outer top surface.

9. The integrated device of claim 1, further comprising a die interconnect portion coupled to the die substrate, wherein the plurality of pads are coupled to the die interconnect portion.

10. The integrated device of claim 1, wherein the integrated device is a part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

11. A package comprising: substrate; and An integrated device coupled to the substrate via at least a plurality of solder interconnects, wherein the integrated device comprises: bare chip substrate; Multiple pads; Multiple internal solder interconnects coupled to multiple pads; and Multiple cylindrical shell interconnects coupled to multiple internal solder interconnects. The plurality of internal solder interconnects are located between the plurality of cylindrical shell interconnects and the plurality of pads, and The plurality of solder interconnects are coupled to the plurality of cylindrical shell interconnects.

12. The package according to claim 11, The integrated device further includes a plurality of under-bump metallized interconnects coupled to the plurality of pads. The plurality of internal solder interconnects are coupled to the plurality of pads via the plurality of under-bump metallized interconnects, and The plurality of solder interconnects are separate from the plurality of internal solder interconnects.

13. The package according to claim 11, The plurality of internal solder interconnects are at least partially located inside the plurality of cylindrical shell interconnects. The cylindrical shell interconnects from the plurality of cylindrical shell interconnects include a first material, and The internal solder interconnects from the plurality of internal solder interconnects include a second material, which is different from the first material.

14. The package according to claim 11, The plurality of pads includes a first pad and a second pad. The plurality of internal solder interconnects includes a first internal solder interconnect and a second internal solder interconnect, and The plurality of cylindrical shell interconnects includes a first cylindrical shell interconnect and a second cylindrical shell interconnect.

15. The package according to claim 14, further comprising: The first under-bump metallized interconnect is coupled to the first pad; and The second under-bump metallized interconnect is coupled to the second pad. The first internal solder interconnect is coupled to and contacts the first under-bump metallized interconnect and the first pillar shell interconnect, and The second internal solder interconnect is coupled to and contacts the second bump under-metallized interconnect and the second column shell interconnect.

16. The package according to claim 14, The first internal solder interconnect is located between the first pad and the first cylindrical shell interconnect, and The second internal solder interconnect is located between the second pad and the second cylindrical shell interconnect.

17. The package of claim 14, wherein the first pillar interconnect and the second pillar interconnect contact the passivation layer of the integrated device.

18. The package of claim 14, further comprising a first solder interconnect. The first cylindrical shell interconnect includes a first side and a first top. The first top includes a first outer top surface and a first inner top surface. The first internal solder interconnect contacts the first inner top surface, and The first solder interconnect contacts the first outer top surface.

19. The package of claim 11, wherein the package is a part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

20. A method comprising: An integrated device is provided, the integrated device comprising a bare die substrate and a plurality of pads; Couple multiple internal solder interconnects to the multiple pads; as well as Multiple cylindrical shell interconnects are formed, and the multiple cylindrical shell interconnects are coupled to the multiple internal solder interconnects such that the multiple internal solder interconnects are located between the multiple cylindrical shell interconnects and the multiple pads.

21. The method of claim 20, further comprising coupling a plurality of solder interconnects to the plurality of cylindrical shell interconnects.

22. The method according to claim 21, The plurality of solder interconnects and the plurality of internal solder interconnects are separate, and The integrated device further includes a plurality of under-bump metallized interconnects coupled to the plurality of pads, wherein the plurality of internal solder interconnects are coupled to the plurality of pads through the plurality of under-bump metallized interconnects.

23. The method of claim 20, wherein the plurality of internal solder interconnects are at least partially located inside the plurality of cylindrical shell interconnects.

24. The method according to claim 20, The plurality of pads includes a first pad and a second pad. The plurality of internal solder interconnects includes a first internal solder interconnect and a second internal solder interconnect, and The plurality of cylindrical shell interconnects includes a first cylindrical shell interconnect and a second cylindrical shell interconnect.

25. The method of claim 24, further comprising: A first under-bump metallized interconnect is formed, and the first under-bump metallized interconnect is coupled to the first pad; as well as A second under-bump metallized interconnect is formed, and the second under-bump metallized interconnect is coupled to the second pad. The first internal solder interconnect is coupled to and contacts the first under-bump metallized interconnect and the first pillar shell interconnect, and The second internal solder interconnect is coupled to and contacts the second bump under-metallized interconnect and the second column shell interconnect.

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