Resistance-type sensing array signal acquisition system with unit electrode sharing characteristic

Abstract

The invention discloses a resistance-type sensing array signal acquisition system with a unit electrode sharing characteristic. The system comprises a resistance-type sensing array with the unit electrode sharing characteristic, an automatic point-by-point switch gating circuit, an excitation end circuit and a signal end circuit. Through the design of double groups of row and column scanning wires and the zero potential isolation circuit, current crosstalk caused by multi-path gating on the same wire of the resistive sensing array with a unit electrode sharing characteristic and adjacent resistor units among different wires is avoided, so that automatic point-by-point scanning of the sensing array can be realized; no external microprocessor or other control is needed, the integration level is high, the unit scanning rate is high, and power consumption is low.

Description

Technical Field

[0001] This invention belongs to the field of resistive sensor array signal acquisition systems, and specifically relates to a resistive sensor array signal acquisition system with the feature of shared unit electrodes. Background Technology

[0002] With the development of wearable devices, intelligent robots, and the Internet of Things (IoT), flexible sensors that are bendable, thin, lightweight, and inexpensive have attracted widespread attention from researchers. Among them, flexible resistive sensors, with their advantages of high sensitivity, easy signal acquisition, and simple manufacturing processes, are widely used in applications such as human physiological signal monitoring, tactile interaction devices, and robotic skin. In practical applications, multiple sensors are often arranged in an array to form a sensor array. Compared to a single sensor, a sensor array has an additional spatial dimension, providing spatiotemporally coupled sensing information. Furthermore, sensor arrays can incorporate multiple types of sensors, utilizing the spatial relationships between sensors and their mutual cooperation and influence to achieve multi-dimensional signal perception and processing, thereby enhancing the system's sensing and processing capabilities. However, as the number and density of sensor array units continue to increase, the complexity of its circuit layout becomes increasingly apparent. In array-based layouts, the number of wires increases exponentially with the number of array units, and the high density of the array makes the integrated layout of the wires increasingly difficult. In addition, the reading and processing of a large number of array signals also places higher demands on the array signal processing system.

[0003] Researchers have done a lot of work on resistive sensor array signal acquisition systems: Patent CN119197855A proposes a matrix circuit and sensor array suitable for sensor arrays. By setting a wiring module including multiple row lines and multiple column lines, a set of row lines and a set of column lines constitute a first-level matrix in the matrix circuit. These first-level matrices are arranged in a matrix configuration to form a second-level matrix. Each sensor is correspondingly assigned to a first-level matrix, and the terminals of each sensor component are connected to the corresponding row and column lines of the first-level matrix. This enables flexible wiring when forming an array of sensors with multiple sensor components, and offers high scalability, reducing the number of leads, thereby saving costs and optimizing the layout.

[0004] Patent CN110082010A discloses a flexible tactile sensor array and an array scanning system applied to it. The sensor array includes a raised layer, an upper electrode layer, a middle layer, and a lower electrode layer. Each electrode in the upper electrode layer is interconnected with each electrode in the lower electrode layer and each piezoresistive sensitive unit in the middle layer. The scanning circuit interface is connected to the upper and lower electrode layers of the flexible tactile sensor array to achieve array scanning of the piezoresistive sensitive units. This sensor array has an extremely high response rate and stable voltage output, and in conjunction with the scanning circuit, it can achieve real-time detection and feedback of contact force.

[0005] Patent CN111289157A discloses a circuit and method for measuring pressure distribution using a piezoresistive sensor array. It includes a piezoresistive sensor array, a reverse analog gating module, a forward analog gating module, a controller, and an analog-to-digital converter. One end of the piezoresistive sensor is connected to a scanning port, and the other end is connected to a sampling port. A controllable tri-state gate is provided between the piezoresistive sensor and the sampling port. The array signal processing circuit can connect the scanning port of the reverse analog gating module and the sampling port of the forward analog gating module to the piezoresistive sensor in the piezoresistive sensor array via the controller. This allows for simple and rapid calculation of the pressure from the piezoresistive sensor, forming a pressure distribution mapping based on the piezoresistive sensor's location. The circuit features high scanning and sampling speed, small measurement error, simple and easy-to-implement structure, low cost, and low power consumption, making it suitable for industrial applications. The controllable tri-state gate increases the circuit discharge channel and improves the discharge speed. While ensuring measurement accuracy, it can increase the scanning frequency and measurement speed, guaranteeing real-time measurement.

[0006] Patent CN119714039A discloses a flexible, fully printed strain sensing array for structural health monitoring. This array employs a Wheatstone bridge-based structural design, with all four resistance values ​​in the sensing element being equal, effectively reducing the impact of temperature changes and achieving excellent temperature compensation performance. Furthermore, because the electrodes, sensing elements, and substrate are all made of stretchable materials, this flexible strain sensing array possesses a tensile strength of up to 40%. Simultaneously, within its designed area, the array can detect strain at up to 16 points at a single location, significantly improving the resolution and accuracy of strain monitoring.

[0007] Patent CN119469491A discloses a resistive flexible pressure sensing array with only a single pair of electrodes and its fabrication method. This flexible pressure sensing array can be fabricated through simple structural and circuit design, and the number of module units in the sensing array can be expanded using the same array arrangement, effectively solving the problem of difficulty in scaling up the sensing array due to circuit and structural complexity. Furthermore, this array only requires a single pair of electrodes connected to a testing instrument to measure the array resistance, simultaneously achieving the functions of identifying pressure location and detecting pressure magnitude, and the number of array electrodes is independent of the number of sensing unit modules within the array.

[0008] Despite significant progress in resistive sensor array signal acquisition systems, they still suffer from the following shortcomings: 1. In traditional resistive sensor arrays, the electrodes are generally located on the upper and lower electrode surfaces. The upper electrode layer moves with deformation and external force loading, and the electrode layer-sensing layer interface is prone to damage and slippage, which interferes with the mechanical and electrical networks of the sensing unit and reduces the consistency and repeatability of the sensing array.

[0009] 2. Some resistive sensor arrays use coplanar interdigitated electrodes as the array electrode layer, which avoids direct stress loading onto the electrode layer and reduces slippage and damage at the electrode layer-sensor layer interface during multiple deformations and pressure loading / unloading. However, the coplanar interdigitated electrode structure requires the sensor array to have extremely high density, and microstructures need to be set on the interdigitated electrode-sensor layer contact interface, which is complex and makes it difficult to maintain the consistency of the sensor array.

[0010] 3. In the upper and lower layer sandwich-type electrode layout and the same-plane interdigitated electrode layout, the electrodes are not shared. Two unit electrodes are required to be connected to one sensing unit, resulting in low electrode utilization and limiting the density of sensing array units.

[0011] 4. In resistive sensor arrays with shared unit electrodes, the electrodes are reused, and there are no clearly defined physical boundaries with electrical isolation between the unit electrodes. The unit electrodes selected for the same wire are not unique. Different unit electrodes on the same wire can form current paths with another wire, resulting in a large deviation between the circuit measurement value and the actual resistance value of the unit under test.

[0012] 5. In traditional resistive sensing array signal acquisition circuits, multiple current paths exist between the selected conductors. When measuring the resistance signal of a selected sensing unit, the current path is not unique, and the measured value is the parallel resistance value of multiple paths, which is subject to interference from the resistance values ​​of other current paths. Especially in resistive sensing arrays with shared unit electrodes, the arrangement of electrodes on the same surface makes the resistance values ​​of different current paths between the selected conductors similar, resulting in a large deviation between the measured value and the true resistance value of the unit under test.

[0013] 6. Traditional resistance sensor array signal acquisition circuits can only rely on external processing units to switch row and column selection lines, and cannot achieve automatic point-by-point scanning. They have low integration, low unit scanning rate, and complex control methods. Summary of the Invention

[0014] To address the aforementioned shortcomings of existing technologies, this invention proposes a resistive sensor array signal acquisition system with shared unit electrodes. Through a dual-set row and column scanning wire design and a zero-potential isolation circuit, it aims to avoid current crosstalk caused by multiple path selection on the same wire and between adjacent resistive units on different wires in resistive sensor arrays with shared unit electrodes. This enables automatic point-to-point scanning of the sensor array, achieving high integration, high unit scanning rate, and low power consumption without the need for external microprocessor control.

[0015] To achieve the above objectives, the present invention adopts the following technical solution: The present invention provides a resistive sensing array signal acquisition system with shared unit electrodes, characterized by: a resistive sensing array with shared unit electrodes, an automatic point-by-point switching selection circuit, an excitation circuit, and a signal circuit. The resistive sensing array with shared unit electrodes comprises: a sensing layer and an electrode array layer; The sensitive layer is a flexible conductive film made of a flexible conductive polymer; The electrode array layer is a flexible circuit board with M rows and N columns of unit electrodes, where M represents the total number of rows of unit electrodes and N represents the total number of columns of unit electrodes. The upper surface of each unit electrode is in contact with the sensitive layer, and the lower surface of each unit electrode is connected to the excitation terminal wire or the signal terminal wire. The excitation circuit includes: excitation wires, an excitation DC voltage source, and digital ground; the excitation wires include multiple sets of wires, each set of wires includes two wires, and the two wires in each set of wires are respectively connected to the unit electrodes in the same row but different columns of the electrode array layer; The signal terminal circuit includes: signal terminal wires, signal acquisition and processing circuit, and digital ground; the signal terminal wires include multiple sets of wires, each set of wires includes two wires, and the two wires in each set of wires are respectively connected to the unit electrodes in the same column but different rows in the electrode array layer; The automatic point-to-point switching selection circuit includes: two sets of shift registers and two sets of CMOS circuits; The first group of shift registers has an output bit width ≥ 2×M. The number of CMOS cells in the first group of CMOS circuits is the same as the number of output bits of the first group of shift registers. The source of each PMOS and NMOS transistor in the first group of CMOS cells is connected to the excitation terminal wire. The drain of each PMOS transistor in the first group of CMOS cells is connected to the excitation DC voltage source. The drain of each NMOS transistor in the first group of CMOS cells is connected to the digital ground in the excitation circuit. The output of each bit of the first group of shift registers is connected to the gate of each PMOS and NMOS transistor in the first group of CMOS circuits. The first group of shift registers controls the conduction or cutoff of the PMOS or NMOS transistors through the output signal to control whether the excitation terminal wire is connected to the excitation DC voltage source or digital ground. The output bit width of the second group of shift registers is ≥2×N. The number of CMOS cells in the second group of CMOS circuits is the same as the output bit width of the second group of shift registers. The source of each PMOS and NMOS transistor in the second group of CMOS circuits is connected to the signal terminal wire. The drain of each PMOS transistor in the second group of CMOS circuits is connected to the input terminal of the signal acquisition and processing circuit. The drain of each NMOS transistor in the second group of CMOS circuits is connected to the digital ground in the signal terminal circuit. The output of each register in the second group of shift registers is connected to the gate of each PMOS and NMOS transistor in the second group of CMOS circuits. The second group of shift registers controls the conduction or cutoff of the PMOS or NMOS transistors through the output terminal signal to control whether the signal terminal wire is connected to the input terminal of the zero potential isolation circuit or the digital ground in the signal acquisition and processing circuit. The automatic point-to-point switching selection circuit automatically scans the original resistance signal of the resistive sensing array point by point under external clock excitation. When the external clock is rising, the output signals of the two sets of shift registers in the automatic point-to-point switching selection circuit automatically switch to select the unit electrode. This allows the original resistance signal to be transmitted to the signal acquisition and processing circuit via the signal terminal wire for crosstalk suppression and signal amplification. Then, the sensor array measurement signal is output through the output terminal of the signal acquisition and processing circuit. Among the unit electrodes connected to the excitation terminal wire, the selected unit electrodes are connected to the excitation DC voltage source via the excitation terminal wire, and the unselected unit electrodes are connected to digital ground via the excitation terminal wire. Among the unit electrodes connected to the signal terminal wire, the selected unit electrodes are connected to the signal acquisition and processing circuit via the signal terminal wire, and the unselected unit electrodes are connected to digital ground via the signal terminal wire.

[0016] The resistive sensing array signal acquisition system with shared unit electrodes described in this invention is also characterized by: For the unit electrodes in the odd-numbered rows of the electrode array layer, the first wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+1th column of the unit electrodes in the odd-numbered rows, and the second wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+3th column of the unit electrodes in the odd-numbered rows. For the unit electrodes in the even-numbered rows of the electrode array layer, the first wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+2th column of the even-numbered row, and the second wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+4th column of the even-numbered row, where k represents the sequence number and 4k+4≤N.

[0017] Furthermore, for the unit electrodes in the odd-numbered columns of the electrode array layer, the first wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+2th row of the unit electrodes in the odd-numbered columns, and the second wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+4th row of the unit electrodes in the odd-numbered columns. For the even-numbered columns of unit electrodes in the electrode array layer, the first wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+1th row of the even-numbered columns, and the second wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+3rd row of the even-numbered columns, where k represents the sequence number and 4k+4≤M.

[0018] Furthermore, the first group of shift registers is composed of M-bit D flip-flops connected in series, and the second group of shift registers is composed of N-bit D flip-flops connected in series. The output of each D flip-flop in each group of shift registers is connected to the input of the next D flip-flop. The input of the first D flip-flop in each group of shift registers is connected to the output of the last D flip-flop and the data input wire of the shift register, respectively. The clock input of each D flip-flop in each group of shift registers is connected to the clock input wire of its own shift register. The data input wires of each shift register are connected to the initial input activation wires in the automatic point-by-point switch gating circuit. The clock input wires of the first shift register are connected to the external clock and the initial clock activation wires in the automatic point-by-point switch gating circuit, respectively. The clock input wires of the second shift register are connected to the output of the last bit D flip-flop in the first shift register and the initial clock activation wire, respectively.

[0019] Furthermore, the signal acquisition and processing circuit includes: a zero-potential isolation circuit and a signal processing circuit; The input terminal of the zero-potential isolation circuit is connected to the signal terminal wire to receive the original resistance signal; the output terminal of the zero-potential isolation circuit is connected to the input terminal of the signal processing circuit, and the output terminal of the signal processing circuit is used to output the sensor array measurement signal. The zero-potential isolation circuit is composed of an operational amplifier; the positive input terminal of the operational amplifier is connected to the signal terminal wire through a switch selection circuit, the inverting input terminal of the operational amplifier is connected to digital ground, and the output terminal of the operational amplifier is connected to the positive input terminal and the input terminal of the signal processing circuit respectively. The signal processing circuit consists of an inverting proportional operational circuit and an even number of forward proportional operational circuits. The inverting proportional operational circuit and each forward proportional operational circuit are composed of operational amplifiers. The input terminal of the inverting operational circuit is connected to the output terminal of the zero-potential isolation circuit, and the output terminal of the inverting operational circuit is connected to the input terminal of the first forward proportional operational circuit. Except for the first forward proportional operational circuit, the input terminals of all other forward proportional operational circuits are connected to the output terminals of the previous forward proportional operational circuits. The output terminal of the last forward proportional operational circuit is used to output the sensor array measurement signal.

[0020] The control method of a resistive sensor array signal acquisition system with shared unit electrodes, as described in this invention, includes the following steps: Step 1: When the sensor array signal acquisition system receives an external input signal, it sets all its input terminals to low level, thereby completing the initialization of the sensor array signal acquisition system. Step 2: The automatic point-to-point switching selection circuit sets the clock input terminals of the first and second shift registers to high level through the initial clock activation wire; after holding this high level for a certain time T1, it sets the data input terminals of the first and second shift registers to high level through the initial input activation wire; after holding this high level for a certain time T2, it sets the clock and data input terminals of the first and second shift registers to low level through the initial clock activation wire and the initial input activation wire; thus completing the initial setup of the automatic point-to-point switching selection circuit. Step 3: Provide a square wave signal to the clock input terminal of the first group of shift registers through an external clock. The frequency of the square wave signal is lower than the maximum clock input frequency of the shift register. During the high-level time of the square wave signal, the output terminal of the signal processing circuit outputs the sensor array measurement signal, which is the resistance value between the two closest unit electrodes among the excitation terminal wire and the signal terminal wire of the currently selected automatic point-by-point switching selection circuit.

[0021] Compared with existing technologies, the beneficial effects of this invention are reflected in: 1. This invention proposes a resistive sensing array with shared unit electrodes. This array has only single-sided electrodes, avoiding direct stress loading onto the electrode layer, reducing slippage and damage at the sensitive layer-electrode layer contact interface, and improving array consistency and repeatability. The array unit electrodes are reusable; the array sensitive unit depends only on the combination of two selected unit electrodes, improving array electrode reuse efficiency. The sensitive layer can be fabricated as a single thin film, and the array density depends only on the electrode density, enabling the low-cost fabrication of extremely high-density flexible resistive sensing arrays.

[0022] 2. This invention introduces a zero-potential circuit into the signal acquisition and processing circuit of the resistive sensing array. When measuring a single sensing unit, all other unit electrodes are connected to digital ground, and the signal terminal wire of the sensing unit is connected to the zero-potential isolation circuit. This ensures that the signal terminal of the unit under test maintains essentially the same potential as the other electrodes, avoiding current crosstalk between different wires and significantly reducing the deviation between the measured value and the true resistance value of the unit under test.

[0023] 3. The present invention designs two sets of row and column scanning circuits, in which the unit electrodes connected by the same wire are separated by at least three unit electrodes. This eliminates the influence of multiple current paths on the circuit measurement value from the circuit topology level, and reduces the deviation between the measured value and the actual resistance value of the unit under test in the resistive sensing array signal acquisition system with the characteristic of shared unit electrodes.

[0024] 4. The switch selection circuit designed in this invention includes an automatic point-by-point selection mode. In the automatic point-by-point selection mode, only an external clock signal is needed to automatically complete the traversal and selection of row and column signal lines, without the need for external microprocessor control, resulting in high integration and high unit scanning rate.

[0025] 6. When reading the signal value of the array sensing unit, only the excitation terminal electrode of the unit under test is at a high potential, while the other electrodes are at zero potential, so that the current path is formed between the electrodes of the unit under test in almost only the sensing array; and only one set of MOS transistors that control row and column selection is in the conducting state at the same time, so that the power consumption of the array signal acquisition circuit is extremely low. Attached Figure Description

[0026] Figure 1 A schematic diagram of a resistive sensor array signal acquisition system with shared unit electrodes. Figure 2 A schematic diagram of a resistive sensing array with shared unit electrodes; Figure 3 A schematic diagram of the wiring of a traditional single-group scanning circuit for a resistive sensor array signal acquisition system with shared unit electrodes. Figure 4A schematic diagram of the wiring for a dual-scanning circuit in a resistive sensor array signal acquisition system with shared unit electrodes. Figure 5 This is a schematic diagram of an automatic point-by-point selection circuit; Figure 6 This is a schematic diagram of the signal acquisition and processing circuit. Figure 7 This is a schematic diagram of a traditional direct scanning method unit signal reading circuit; Figure 8 This is a simulation diagram of a traditional direct scanning method unit signal reading circuit; Figure 9 This is a schematic diagram of a unit signal reading circuit using zero-potential isolation. Figure 10 This is a simulation diagram of a unit signal readout circuit using zero-potential isolation; Figure 11 This is a schematic diagram of a control method for a resistive sensor array signal acquisition system with shared unit electrodes. Detailed Implementation

[0027] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following embodiments are implemented based on the technical solution of the present invention, and detailed implementation methods and specific operation processes are given. However, the protection scope of the present invention is not limited to the following embodiments.

[0028] Example 1: like Figure 1 As shown, the resistive sensor array signal acquisition system with shared unit electrode features proposed in this embodiment includes: a resistive sensor array 1 with shared unit electrode features, an automatic point-by-point switching selection circuit 2, an excitation terminal circuit 3, and a signal terminal circuit 4.

[0029] like Figure 2 As shown, a resistive sensing array with shared unit electrodes comprises: a sensitive layer and an electrode array layer. The sensitive layer is a flexible conductive thin film made of a flexible conductive polymer; the electrode array layer is a flexible circuit board with M=8 rows and N=6 columns of unit electrodes. The upper surface of each unit electrode is in contact with the sensitive layer, and the lower surface of each unit electrode is connected to an excitation terminal wire or a signal terminal wire. Here, M represents the total number of rows of unit electrodes, and N represents the total number of columns of unit electrodes.

[0030] In a resistive sensor array, the unit electrodes are shared. The sensitive unit acquired by the resistive sensor array signal acquisition system depends only on the combination of the two selected unit electrodes. The same unit electrode may be selected multiple times when acquiring signals from different sensitive units.

[0031] The excitation circuit includes: excitation wires, an excitation DC voltage source, and digital ground; the excitation wires include eight sets of wires, each set containing two wires; the two wires in each set are respectively connected to unit electrodes in the same row but different columns of the electrode array layer. For unit electrodes in odd-numbered rows of the electrode array layer, the first wire in each set of wires in the excitation circuit is connected to the unit electrode in the 4k+1th column of the odd-numbered row, and the second wire in each set of wires in the excitation circuit is connected to the unit electrode in the 4k+3th column of the odd-numbered row. For the unit electrodes in the even-numbered rows of the electrode array layer, the first wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+2th column of the even-numbered row, and the second wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+4th column of the even-numbered row, where k represents the sequence number and 4k+4≤N.

[0032] In this embodiment, for rows 1, 3, 5, and 7, the first wire of each group of the excitation circuit is connected to the unit electrode in column 1 and column 5 of that row, respectively, and the second wire of each group is connected to the unit electrode in column 3 of that row, respectively. For rows 2, 4, 6, and 8, the first wire of each group of the excitation circuit is connected to the unit electrode in column 2 and column 6 of that row, respectively, and the second wire of each group is connected to the unit electrode in column 4 of that row, respectively.

[0033] The signal terminal circuit includes: signal terminal wires, signal acquisition and processing circuits, and digital ground; the signal terminal wires include six sets of wires, each set of wires includes two wires; the two wires in each set of wires are respectively connected to the unit electrodes in the same column but different rows in the electrode array layer.

[0034] For the unit electrodes in the odd-numbered columns of the electrode array layer, the first wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+2th row of the unit electrodes in the odd-numbered columns, and the second wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+4th row of the unit electrodes in the odd-numbered columns. For the even-numbered columns of unit electrodes in the electrode array layer, the first wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+1th row of the even-numbered columns, and the second wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+3rd row of the even-numbered columns, where k represents the sequence number and 4k+4≤M.

[0035] In this embodiment, for columns 1, 3, and 5, the first wire of each group of signal terminal circuits is connected to the unit electrodes of rows 2 and 6 of that column, respectively, and the second wire of each group is connected to the unit electrodes of rows 4 and 8 of that column, respectively. For columns 2, 4, and 6, the first wire of each group of signal terminal circuits is connected to the unit electrodes of rows 1 and 5 of that column, respectively, and the second wire of each group is connected to the unit electrodes of rows 3 and 7 of that column, respectively.

[0036] Figure 3 The diagram shows a traditional single-group scanning circuit wiring diagram for a resistive sensor array signal acquisition system with shared unit electrodes. Traditional resistive sensor arrays use row and column scanning circuits to select the upper and lower electrodes at specific locations to read the sensing unit signals. However, resistive sensor arrays with shared unit characteristics employ a coplanar electrode layout. Directly using the traditional single-channel row and column scanning method, for example, when… L 1 and R When the three conductors are selected, there are two current paths at the same time. The measured signal is the parallel value of the resistance of the two units, which deviates greatly from the actual value of the unit to be measured.

[0037] Figure 4 The diagram shows the wiring schematic of a dual-scanning circuit for a resistive sensor array signal acquisition system with shared unit electrodes. By designing two sets of scanning circuits, for example, when... L 1 and r When a conductor is selected, there is only one selected current path in the array, thus eliminating signal crosstalk caused by multi-path conduction at the circuit topology level. This allows the sensing unit in a resistive sensing array with shared unit electrodes to still be selected through a certain row or column electrode.

[0038] like Figure 5 As shown, in this embodiment, the automatic point-to-point switching selection circuit includes two sets of shift registers and two sets of CMOS circuits.

[0039] The first shift register contains sixteen output bits. The number of CMOS cells in the first CMOS circuit is the same as the number of output bits of the first shift register. The source of each PMOS and NMOS transistor in the first CMOS cell is connected to the excitation terminal wire. The drain of each PMOS transistor in the first CMOS cell is connected to the excitation DC voltage source. The drain of each NMOS transistor in the first CMOS cell is connected to the digital ground in the excitation circuit. The output of each bit in the first shift register is connected to the gate of each PMOS and NMOS transistor in the first CMOS cell. The first shift register controls the conduction or cutoff of the PMOS or NMOS transistor through the output signal to control whether the excitation terminal wire is connected to the excitation DC voltage source or digital ground.

[0040] The second shift register contains twelve output bits. The number of CMOS cells in the second CMOS circuit is the same as the number of output bits in the second shift register. The source of each PMOS and NMOS transistor in the second CMOS cell is connected to the signal terminal wire. The drain of each PMOS transistor in the second CMOS cell is connected to the input terminal of the signal acquisition and processing circuit. The drain of each NMOS transistor in the second CMOS cell is connected to the digital ground in the signal terminal circuit. The output of each bit in the second shift register is connected to the gate of each PMOS and NMOS transistor in the second CMOS cell. The second shift register controls the conduction or cutoff of the PMOS or NMOS transistor through the output signal to control whether the signal terminal wire is connected to the input terminal of the zero-potential isolation circuit or the digital ground in the signal acquisition and processing circuit.

[0041] The automatic point-to-point switching selection circuit automatically scans the original resistance signal of the resistive sensor array point by point under external clock excitation. When the external clock is rising, the output signals of the two sets of shift registers in the automatic point-to-point switching selection circuit automatically switch the selection unit electrode, so that the original resistance signal is transmitted to the signal acquisition and processing circuit through the signal terminal wire for crosstalk suppression and signal amplification. Then, the sensor array measurement signal is output through the output terminal of the signal acquisition and processing circuit. Among the unit electrodes connected to the excitation terminal wire, the selected unit electrode is connected to the excitation DC voltage source through the excitation terminal wire, and the unselected unit electrode is connected to the digital ground through the excitation terminal wire. Among the unit electrodes connected to the signal terminal wire, the selected unit electrode is connected to the signal acquisition and processing circuit through the signal terminal wire, and the unselected unit electrode is connected to the digital ground through the signal terminal wire.

[0042] like Figure 6 As shown, in this embodiment, the signal acquisition and processing circuit includes a zero-potential isolation circuit and a signal processing circuit. The input terminal of the zero-potential isolation circuit is connected to the signal terminal wire and is used to receive the raw resistance signal. The output terminal of the zero-potential isolation circuit is connected to the input terminal of the signal processing circuit, and the output terminal of the signal processing circuit is used to output the sensor array measurement signal.

[0043] The zero-potential isolation circuit consists of an operational amplifier. The positive input terminal of the operational amplifier is connected to the signal terminal wire through a switch selection circuit, the inverting input terminal of the operational amplifier is connected to digital ground, and the output terminal of the operational amplifier is connected to the positive input terminal and the input terminal of the signal processing circuit.

[0044] The signal processing circuit consists of one inverting proportional operational amplifier circuit and two non-inverting proportional operational amplifier circuits connected in series. Both the inverting and non-inverting proportional operational amplifier circuits are composed of operational amplifiers. The input of the inverting operational amplifier circuit is connected to the output of a zero-potential isolation circuit, and its output is connected to the input of the first positive proportional operational amplifier circuit. Except for the first positive proportional operational amplifier circuit, the inputs of all other positive proportional operational amplifier circuits are connected to the output of the preceding positive proportional operational amplifier circuit. The output of the last positive proportional operational amplifier circuit is used to output the sensor array measurement signal.

[0045] Figure 7 This is a schematic diagram of a traditional direct scanning method for reading signals from individual cells. Because resistive sensing arrays with shared cell electrodes use a single, continuous sensing layer, there are no clearly defined physical boundaries with electrical isolation between cells, resulting in significant crosstalk. For example... Figure 7 As shown, when measuring the signal of sensing unit R25, electrode 2 is connected to the digital DC voltage source, and electrode 5 is connected to the signal terminal wire. Current path 1 is the current flowing through the sensing unit R25 under test, and its magnitude should be as close as possible to the measured current on the signal terminal wire. However, current paths 2-5 through adjacent sensing units will also introduce crosstalk current to the signal terminal wire, affecting the circuit measurement results. Figure 8 This is a simulation diagram of a traditional direct scanning method unit signal reading circuit. When the sensing unit R25 has a high resistance, almost all the measured current on the signal terminal wire comes from current path 1, resulting in a small measurement error. However, when the resistance value of R25 is low, most of the measured current on the signal terminal wire comes from crosstalk current in current path 2-current path 5, causing a large deviation between the circuit measurement value and the true value.

[0046] To address the current crosstalk problem introduced by adjacent sensing units on the sensitive layer, this invention designs a zero-potential isolation circuit. Figure 9 This is a schematic diagram of a unit signal readout circuit using zero-potential isolation. When measuring the signal of sensing unit R25, electrode 2 is connected to a digital DC voltage source, and electrode 5 is connected to the zero-potential isolation circuit via a signal terminal wire, placing electrode 5 at near-zero potential. All other electrodes are connected to digital ground. In this configuration, crosstalk current is shielded by the grounded electrodes, and the measured current at the signal terminal almost entirely originates from current path 1, significantly reducing current crosstalk introduced by unselected sensing units. Figure 10 This is a simulation diagram of a unit signal reading circuit using zero-potential isolation. Figure 10 Simulation results show that, after adopting the zero-potential isolation circuit, regardless of the resistance value of the unit under test, the measured current at the signal terminal is always approximately equal to the current in current path 1, which greatly reduces the circuit measurement error.

[0047] like Figure 11As shown, the control method of the resistive sensor array signal acquisition system with shared unit electrodes in this embodiment includes the following steps: Step 1: When the sensor array signal acquisition system receives an external input signal, it sets all its input terminals to low level, thereby completing the initialization of the sensor array signal acquisition system. Step 2: The automatic point-to-point switching selection circuit sets the clock input terminals of the first and second shift registers to high level through the initial clock activation wire; after holding this high level for a certain time T1, it sets the data input terminals of the first and second shift registers to high level through the initial input activation wire; after holding this high level for a certain time T2, it sets the clock and data input terminals of the first and second shift registers to low level through the initial clock activation wire and the initial input activation wire; thus completing the initial setup of the automatic point-to-point switching selection circuit. Step 3: Provide a square wave signal to the clock input terminal of the first group of shift registers through an external clock. The frequency of the square wave signal is lower than the maximum clock input frequency of the shift register. During the high-level time of the square wave signal, the output terminal of the signal processing circuit outputs the sensor array measurement signal, which is the resistance value between the two closest unit electrodes on the excitation terminal wire and the signal terminal wire of the currently selected automatic point-by-point switching selection circuit.

Claims

1. A resistive sensing array signal acquisition system with shared unit electrodes, characterized in that, include: A resistive sensing array with shared unit electrodes, an automatic point-by-point switching selection circuit, an excitation circuit, and a signal circuit; The resistive sensing array with shared unit electrodes comprises: a sensing layer and an electrode array layer; The sensitive layer is a flexible conductive film made of a flexible conductive polymer; The electrode array layer is a flexible circuit board with M rows and N columns of unit electrodes, where M represents the total number of rows of unit electrodes and N represents the total number of columns of unit electrodes. The upper surface of each unit electrode is in contact with the sensitive layer, and the lower surface of each unit electrode is connected to the excitation terminal wire or the signal terminal wire. The excitation circuit includes: excitation wires, an excitation DC voltage source, and digital ground; the excitation wires include multiple sets of wires, each set of wires includes two wires, and the two wires in each set of wires are respectively connected to the unit electrodes in the same row but different columns of the electrode array layer; The signal terminal circuit includes: signal terminal wires, signal acquisition and processing circuit, and digital ground; the signal terminal wires include multiple sets of wires, each set of wires includes two wires, and the two wires in each set of wires are respectively connected to the unit electrodes in the same column but different rows in the electrode array layer; The automatic point-to-point switching selection circuit includes: two sets of shift registers and two sets of CMOS circuits; The first group of shift registers has an output bit width ≥ 2×M. The number of CMOS cells in the first group of CMOS circuits is the same as the number of output bits of the first group of shift registers. The source of each PMOS and NMOS transistor in the first group of CMOS cells is connected to the excitation terminal wire. The drain of each PMOS transistor in the first group of CMOS cells is connected to the excitation DC voltage source. The drain of each NMOS transistor in the first group of CMOS cells is connected to the digital ground in the excitation circuit. The output of each bit of the first group of shift registers is connected to the gate of each PMOS and NMOS transistor in the first group of CMOS circuits. The first group of shift registers controls the conduction or cutoff of the PMOS or NMOS transistors through the output signal to control whether the excitation terminal wire is connected to the excitation DC voltage source or digital ground. The output bit width of the second group of shift registers is ≥2×N. The number of CMOS cells in the second group of CMOS circuits is the same as the output bit width of the second group of shift registers. The source of each PMOS and NMOS transistor in the second group of CMOS circuits is connected to the signal terminal wire. The drain of each PMOS transistor in the second group of CMOS circuits is connected to the input terminal of the signal acquisition and processing circuit. The drain of each NMOS transistor in the second group of CMOS circuits is connected to the digital ground in the signal terminal circuit. The output of each register in the second group of shift registers is connected to the gate of each PMOS and NMOS transistor in the second group of CMOS circuits. The second group of shift registers controls the conduction or cutoff of the PMOS or NMOS transistors through the output terminal signal to control whether the signal terminal wire is connected to the input terminal of the zero potential isolation circuit or the digital ground in the signal acquisition and processing circuit. The automatic point-to-point switching selection circuit automatically scans the original resistance signal of the resistive sensing array point by point under external clock excitation. When the external clock is rising, the output signals of the two sets of shift registers in the automatic point-to-point switching selection circuit automatically switch to select the unit electrode. This allows the original resistance signal to be transmitted to the signal acquisition and processing circuit via the signal terminal wire for crosstalk suppression and signal amplification. Then, the sensor array measurement signal is output through the output terminal of the signal acquisition and processing circuit. Among the unit electrodes connected to the excitation terminal wire, the selected unit electrodes are connected to the excitation DC voltage source via the excitation terminal wire, and the unselected unit electrodes are connected to digital ground via the excitation terminal wire. Among the unit electrodes connected to the signal terminal wire, the selected unit electrodes are connected to the signal acquisition and processing circuit via the signal terminal wire, and the unselected unit electrodes are connected to digital ground via the signal terminal wire.

2. The resistive sensing array signal acquisition system with shared unit electrodes according to claim 1, characterized in that: For the unit electrodes in the odd-numbered rows of the electrode array layer, the first wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+1th column of the unit electrodes in the odd-numbered rows, and the second wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+3th column of the unit electrodes in the odd-numbered rows. For the unit electrodes in the even-numbered rows of the electrode array layer, the first wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+2th column of the even-numbered row, and the second wire in each group of wires in the excitation circuit is connected to the unit electrode in the 4k+4th column of the even-numbered row, where k represents the sequence number and 4k+4≤N.

3. The resistive sensing array signal acquisition system with shared unit electrodes according to claim 1, characterized in that: For the unit electrodes in the odd-numbered columns of the electrode array layer, the first wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+2th row of the unit electrodes in the odd-numbered columns, and the second wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+4th row of the unit electrodes in the odd-numbered columns. For the even-numbered columns of unit electrodes in the electrode array layer, the first wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+1th row of the even-numbered columns, and the second wire in each group of wires in the signal terminal circuit is connected to the unit electrode in the 4k+3rd row of the even-numbered columns, where k represents the sequence number and 4k+4≤M.

4. A resistive sensing array signal acquisition system with shared unit electrodes as described in claim 1, characterized in that: The first group of shift registers consists of M-bit D flip-flops connected in series, and the second group of shift registers consists of N-bit D flip-flops connected in series. The output of each D flip-flop in each group of shift registers is connected to the input of the next D flip-flop. The input of the first D flip-flop in each group of shift registers is connected to the output of the last D flip-flop and the data input wire of the shift register, respectively. The clock input of each D flip-flop in each group of shift registers is connected to the clock input wire of its own shift register. The data input wires of each shift register are connected to the initial input activation wires in the automatic point-by-point switch gating circuit. The clock input wires of the first shift register are connected to the external clock and the initial clock activation wires in the automatic point-by-point switch gating circuit, respectively. The clock input wires of the second shift register are connected to the output of the last bit D flip-flop in the first shift register and the initial clock activation wire, respectively.

5. A resistive sensing array signal acquisition system with shared unit electrodes as described in claim 1, characterized in that, The signal acquisition and processing circuit includes: a zero-potential isolation circuit and a signal processing circuit; The input terminal of the zero-potential isolation circuit is connected to the signal terminal wire to receive the original resistance signal; the output terminal of the zero-potential isolation circuit is connected to the input terminal of the signal processing circuit, and the output terminal of the signal processing circuit is used to output the sensor array measurement signal. The zero-potential isolation circuit is composed of an operational amplifier; the positive input terminal of the operational amplifier is connected to the signal terminal wire through a switch selection circuit, the inverting input terminal of the operational amplifier is connected to digital ground, and the output terminal of the operational amplifier is connected to the positive input terminal and the input terminal of the signal processing circuit respectively. The signal processing circuit consists of an inverting proportional operational circuit and an even number of forward proportional operational circuits. The inverting proportional operational circuit and each forward proportional operational circuit are composed of operational amplifiers. The input terminal of the inverting operational circuit is connected to the output terminal of the zero-potential isolation circuit, and the output terminal of the inverting operational circuit is connected to the input terminal of the first forward proportional operational circuit. Except for the first forward proportional operational circuit, the input terminals of all other forward proportional operational circuits are connected to the output terminals of the previous forward proportional operational circuits. The output terminal of the last forward proportional operational circuit is used to output the sensor array measurement signal.

6. The control method for a resistive sensing array signal acquisition system with shared unit electrodes as described in claim 1, characterized in that, Includes the following steps: Step 1: When the sensor array signal acquisition system receives an external input signal, it sets all its input terminals to low level, thereby completing the initialization of the sensor array signal acquisition system. Step 2: The automatic point-to-point switching selection circuit sets the clock input terminals of the first and second shift registers to high level through the initial clock activation wire; after holding this high level for a certain time T1, it sets the data input terminals of the first and second shift registers to high level through the initial input activation wire; after holding this high level for a certain time T2, it sets the clock and data input terminals of the first and second shift registers to low level through the initial clock activation wire and the initial input activation wire; thus completing the initial setup of the automatic point-to-point switching selection circuit. Step 3: Provide a square wave signal to the clock input terminal of the first group of shift registers through an external clock. The frequency of the square wave signal is lower than the maximum clock input frequency of the shift register. During the high-level time of the square wave signal, the output terminal of the signal processing circuit outputs the sensor array measurement signal, which is the resistance value between the two closest unit electrodes among the excitation terminal wire and the signal terminal wire of the currently selected automatic point-by-point switching selection circuit.

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