Power-on reset control method compatible with multiple environments

Abstract

According to the power-on reset control method compatible with multiple environments provided by the invention, the built power-on reset control circuit comprises the thermosensitive comparison circuit, the configuration trimming circuit and the power-on reset signal generation circuit, and whether the current environment temperature accords with the working temperature range of the consumable chip or not is judged through the thermosensitive comparison circuit; the follow-up work is executed only under the condition of conformity; according to the method, configuration data for electrification of a consumable chip of each signal is stored in the chip in advance, the configuration data for electrification is sent to a configuration trimming circuit after electrification, and the configuration trimming circuit is matched with the configuration data for electrification to modulate and generate a control voltage signal suitable for the consumable chip in real time; and the power-on reset signal is sent to the power-on reset signal generation circuit to generate a power-on reset signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of printer consumable chip, in particular to a power-on reset control method compatible with multiple environments. BACKGROUND

[0002] In the current intelligent printer, the consumable box such as ink cartridge, toner cartridge and powder box is detachably installed on the printer body. The consumable chip and control circuit are arranged on the consumable box to store consumable related data and complete communication with the printer body. Common consumable boxes include original consumable boxes and third-party manufactured printer consumable boxes. In the design process of the consumable chip and control circuit of the consumable box, the design of the power-on reset circuit is included.

[0003] Power-on reset is a hardware mechanism in electronic systems that triggers a reset function through the voltage change when the power is turned on. Its core principle is to use the charging and discharging characteristics of RC circuit to make the reset pin produce a level change that meets the timing requirements when the device is powered on, thereby completing register initialization, program counter zeroing and other operations, and initializing the modules in the chip to a known state. For example, the most simple power-on reset circuit is based on the principle of RC delay, which uses the characteristic that the voltage across the capacitor cannot change abruptly. Through the resistance R, the capacitor C is charged, so that the reset signal voltage config_C reaches the threshold voltage Vth of the mos tube, generating a reset signal RESET. The advantage of this structure is simple structure, small internal area of integrated circuit chip and low cost. However, the precision is poor, the anti-interference ability is poor, and some slight jitter may cause the level to reverse. At the same time, for some low-power mode voltage drop but host standby state, this circuit may directly shut down the host, and in order to solve these drawbacks, the front stage increases voltage monitoring, and the back end increases Schmidt trigger, latch and other circuits to solve the above shortcomings. Because high power consumption may cause long-term high-temperature work and may also exacerbate chip damage, a separate over-temperature protection circuit needs to be designed for the consumable chip in some models of printers.

[0004] Because different models of printers correspond to different environmental parameters, such as power-on voltage, power-on time, power-off voltage and working temperature. According to the conventional design idea, when designing the consumable chip, according to the different peripheral environment of the device, the corresponding power-on reset circuit and other related peripheral circuits of the consumable chip need to be designed according to different device environmental parameters. However, if the corresponding power-on reset circuit and other related peripheral circuits of the consumable chip are redesigned and adjusted according to different device environmental parameters, the cost is relatively high, and there may be certain deviation due to process reasons, which is risky and does not meet the actual production requirements. SUMMARY

[0005] In order to solve the problem of high design cost caused by the separate design of the power-on reset circuit of the consumable chip of the printer device for different environmental parameters, the application provides a power-on reset control method compatible with multiple environments, which can make the same circuit suitable for different device environmental parameters and applied to various types of printer consumable boxes.

[0006] The technical solution of the application is as follows: a power-on reset control method compatible with multiple environments, characterized in that it comprises the following steps: S1: designing a thermal comparison circuit; The thermal comparison circuit determines whether the consumable chip can work normally according to the current environmental temperature TEMP, generates an environmental state signal CTRL, and sends the environmental state signal CTRL to the subsequent circuit; the environmental state signal includes: normal state and abnormal state; S2: designing a configuration trimming circuit; The configuration trimming circuit receives the environmental state signal CTRL; When the environmental state signal CTRL is in the normal state, the configuration trimming circuit reads the power-on configuration data stored in the consumable chip, obtains the corresponding voltage dividing resistor string for the power-on voltage configuration, generates the corresponding control voltage signal CONFIG_V of the consumable chip based on the voltage dividing resistor string, and sends the control voltage signal CONFIG_V to the subsequent circuit; When the environmental state signal CTRL is in the abnormal state, the generation of the control voltage signal CONFIG_V is stopped; S3: designing a power-on reset signal generation circuit; The power-on reset signal generation circuit receives the control voltage signal CONFIG_V sent by the configuration trimming circuit, generates a reset signal RESET by using the RC delay principle, and sends the signal to other modules of the consumable chip; S4: constructing a power-on reset control circuit and integrating the power-on reset control circuit into the consumable chip; The power-on reset control circuit comprises: a thermal comparison circuit, a configuration trimming circuit and a power-on reset signal generation circuit connected in sequence: S5: Before leaving the factory, the power-on related configuration data corresponding to the consumable chip is written in the memory of the consumable chip; S6: After power-on, the consumable chip reads the power-on configuration data and sends it to the configuration trimming circuit; The thermal sensitive comparison circuit generates an environment state signal CTRL according to a real-time environment temperature and sends the environment state signal CTRL into the configuration adjustment circuit; when the environment state signal CTRL is normal, the configuration adjustment circuit generates a control voltage signal CONFIG_V based on the received configuration data for power-on and sends the control voltage signal CONFIG_V into the power-on reset signal generation circuit, and the power-on reset signal generation circuit outputs a power-on reset signal RESET according to the received CONFIG_V and sends the power-on reset signal RESET into other modules; when the environment state signal CTRL is abnormal, the power-on reset signal RESET is not generated.

[0007] It further features that: The thermal sensitive comparison circuit comprises a comparator circuit and a thermal resistance modulation voltage module; the thermal resistance modulation voltage module generates a thermal resistance modulation voltage according to an environment temperature TEMP and sends the thermal resistance modulation voltage into the comparator circuit; the comparator circuit compares the thermal resistance modulation voltage with a reference voltage VREF to obtain an environment temperature judgment result, generates a stable environment state signal CTRL according to the environment temperature judgment result, and sends the environment state signal CTRL into the configuration adjustment circuit; The environment state signal CTRL comprises 1 and 0; wherein 1 represents normal working and 0 represents an abnormal state; The configuration adjustment circuit comprises a MOS switch tube combination, a resistance string and a configuration module; The number of MOS switch tubes included in the MOS switch tube combination is greater than 1; and the number of resistors included in the resistance string is greater than 1; The MOS switch tube combination is connected between the configuration module and the resistance string, the configuration module controls the opening and closing of the MOS tubes in the MOS switch tube combination according to the configuration data for power-on, realizes the adjustment of the resistance value of the resistance string, further configures the resistance string as a voltage dividing resistor adapted to the power-on voltage, obtains the power-on voltage in proportion, and outputs a control voltage signal CONFIG_V; The configuration module comprises a decoder DEC2 and a selector; and the MOS switch tube combination comprises a PMOS tube combination and an NMOS tube combination; The configuration data for power-on comprises a P-tube configuration configRise for power-on voltage and an N-tube configuration configFall for power-on voltage; The selector is connected with all PMOS tubes, and the decoder DEC2 is connected with all NMOS tubes; The consumable chip sends the P-tube configuration configRise for power-on voltage into the selector, the selector controls the opening and closing of each POMS tube according to the configuration data configRise, configures the resistance string as a voltage dividing resistor adapted to the power-on voltage, and further obtains the power-on voltage range in proportion. The consumable chip sends the power-on voltage N tube configuration configFall into the decoder DEC2, and the decoder DEC2 controls the switch of each NOMS tube according to the configuration data configFall, fine tunes in the voltage range adjusted by the PMOS tube, and obtains a control voltage signal CONFIG_V; The power-on reset signal generation circuit includes a signal generation resistor, a signal generation capacitor, and a comparison NMOS tube; The signal generation resistor and the signal generation capacitor constitute an RC circuit; The CONFIG_V signal output by the configuration trimming circuit is input to the gate of the NMOS tube, the drain of the NMOS tube is connected to a resistor, and the source is grounded. When the gate voltage CONFIG_V of the comparison NMOS tube exceeds the threshold voltage Vth of the NMOS tube, the resistor in the RC circuit charges the capacitor, and outputs the power-on reset signal RESET; The configuration trimming circuit further includes a decoder DEC1; The power-on configuration data further includes a power-on delay time configuration config Delay; The power-on reset signal generation circuit further includes a delay control module, and the delay control module includes a delay NMOS tube, and the delay NMOS tube is connected to the signal generation capacitor; The consumable chip sends the power-on delay time configuration config Delay into the decoder DEC1, and the decoder DEC1 controls the switch of the delay NMOS tube according to the configuration data config Delay, controls the charging time of the capacitor, and realizes signal delay; The thermosensitive comparison circuit continuously judges whether the ambient temperature meets the working range of the consumable chip after the power-on process ends; The power-on reset signal generation circuit works according to the judgment result of the thermosensitive circuit. If the ambient temperature is within the working temperature range of the consumable chip, the RESET signal is continuously maintained, otherwise when the ambient temperature exceeds the working range of the consumable chip, the output of the RESET signal is stopped; If the RESET signal can be received by other modules of the consumable chip, it is judged that the current ambient temperature state is within the working range of the consumable chip; if the RESET signal cannot be received by other modules, it is judged that the current ambient temperature is not suitable for the consumable chip to work; As shown in Figure 2 The thermosensitive comparison circuit includes resistors R0-R4, a comparator COMP1, a capacitor C1, an NMOS tube N1, Schmidt triggers I1 and I2, an inverter I3, and an RS latch. The RS latch is composed of two groups of AND gates connected to each other. The resistor R0 is a thermistor, one end of the resistor R0 is connected to VDD, the other end of the resistor R0 is connected to the + input pin of the comparator COMP1, one end of the resistor R1, the - input pin of the comparator COMP1 is connected to the reference voltage VREF, the output of the comparator COMP1 is connected to the input pin of the Schmitt trigger I1, the output pin of the Schmitt trigger I1 is connected to one input end vin2 of the RS latch, the other input end vin1 of the RS latch is the output end of the Schmitt trigger I2, the input end of the Schmitt trigger I2 is connected to the positive electrode of the capacitor C1, one end of the resistor R4 and the drain of the NMOS tube N1, the gate of the NMOS tube N1 is connected to the reference low voltage VREF, the source of the NMOS tube N1 is grounded; the output end vout of the RS latch is connected to the input end of the inverter I3, and the output end of the inverter I3 outputs the environmental state signal CTRL; The other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3, the other end of the resistor R3 is grounded, and the other end of the resistor R4 is connected to VDD. As shown in Figure 3 , 5 and 6, the configuration trimming circuit comprises a voltage clamping unit Tielo, a selector MUX1, decoders DEC1 and DEC2, a voltage clamping unit T1, an inverter I4, PMOS tubes P1-P7, NMOS tubes N2-N6, resistors R5-R14. The voltage clamping unit Tielo is connected between VDD and VSS to output low level, the output pin of the voltage clamping unit Tielo is connected to the input pin of the inverter I4, the output pin of the inverter I4 is connected to the gate of the PMOS tube P1, the source of the PMOS tube P1 is connected to VDD, the drain of the PMOS tube P1 is connected to the source of the PMOS tube P3, the gate of the PMOS tube P3 is connected to VSS, the drain of the PMOS tube P3 is connected to the drain of the PMOS tube P2, the source of the PMOS tube P4, the source of the PMOS tube P5, the source of the PMOS tube P6, the source of the PMOS tube P2 is connected to VDD, the gate of the PMOS tube P2 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to VSS, the gate of the PMOS tube P4, the gate of the PMOS tube P5, the gate of the PMOS tube P6, the gate of the PMOS tube P7 are commonly connected to the RISEOUT signal output pin of the selector MUX1, the drain of the PMOS tube P4, the drain of the PMOS tube P5, the drain of the PMOS tube P6 are connected to one end of the resistor R6, the other end of the resistor R6 is connected to the drain of the NMOS tube N2, one end of the resistor R9, the source and drain of the PMOS tube P7, both ends of the resistor R8, and the output pin of the configuration voltage signal CONFIG_V, the gate of the NMOS tube N2, the gate of the NMOS tube N3, the gate of the NMOS tube N4, the gate of the NMOS tube N5 are commonly connected to the signal FALLOUT signal output end of the decoder DEC2, the source of the NMOS tube N2 is connected to the drain of the NMOS tube N3, the other end of the resistor R9, both ends of the resistor R10, one end of the resistor R11, the source of the NMOS tube N3 is connected to the drain of the NMOS tube N4, the other end of the resistor R11, one end of the resistor R12, the source of the NMOS tube N4 is connected to the drain of the NMOS tube N5, the other end of the resistor R12, both ends of the resistor R13, one end of the resistor R14, the source of the NMOS tube N5 is connected to the other end of the resistor R14, the drain of the NMOS tube N6, the source of the NMOS tube N6 is connected to VSS, the gate of the NMOS tube N6 is connected to the ambient state signal CTRL output end of the thermosensitive comparison circuit; the DECIN pin of the decoder DEC2 is the CTRL_DELAY signal input end, the DECIN pin of the selector MUX1 is the CTRL_RISE signal input end, the DECIN pin of the decoder DEC2 is the CTRL_FALL signal input end, both ends of the resistor R7 are interconnected; As Figure 4 , 7As shown in FIGS. 7 and 8, the power-on reset signal generating circuit includes NMOS tubes N7-N16, PMOS tubes P8-P16, resistors R15, capacitors C2-C5, Schmitt triggers I5, I8, I9, I10, and I11, inverters I6, I7, and I12, The gate of the NMOS transistor N7 is connected to the CONFIG V signal output pin of the configuration trimming circuit, the drain of the NMOS transistor N7 is connected to one end of the resistor R15, the input pin of the Schmitt trigger I5, the other end of the resistor R15 is connected to the power supply VS, the source of the NMOS transistor N7 is grounded to GS, the output end of the Schmitt trigger I5 is connected to the input end of the inverter I6, the output end of the inverter I6 is connected to the input end of the inverter I7, the gate of the NMOS transistor N9, and the gate of the PMOS transistor P8, the output end of the inverter I7 is connected to the gate of the NMOS transistor N8, the drain of the NMOS transistor N8 is connected to GS, one end of the resistor R16 is connected to the source of the NMOS transistor N8, the other end of the resistor R16 is connected to the drain of the PMOS transistor P16, the gate of the PMOS transistor P16, the gate of the PMOS transistor P9, the gate of the PMOS transistor P11, the gate of the PMOS transistor P13, the gate of the PMOS transistor P15, the source of the PMOS transistor P16 is connected to VS, the drain of the PMOS transistor P9 is connected to the source of the PMOS transistor P8, the source of the NMOS transistor N9 is connected to the drain of the PMOS transistor P8, the source of the NMOS transistor N10, and the input end of the Schmitt trigger I8, the gates of the NMOS transistor N10, the NMOS transistor N12, the NMOS transistor N14, and the NMOS transistor N16 are connected to the CONFIG D signal output pin output by the configuration trimming circuit, the positive electrode of the capacitor C2 is connected to the drain of the NMOS transistor N10, the positive electrode of the capacitor C3 is connected to the drain of the NMOS transistor N12, the positive electrode of the capacitor C4 is connected to the drain of the NMOS transistor N14, the positive electrode of the capacitor C5 is connected to the drain of the NMOS transistor N16, the negative electrodes of the capacitor C2, the capacitor C3, the capacitor C4, and the capacitor C5 are connected to GS, the sources of the PMOS transistor P9, the PMOS transistor P11, the PMOS transistor P13, and the PMOS transistor P15 are connected to VS, the drains of the NMOS transistor N9, the NMOS transistor N11, the NMOS transistor N13, and the NMOS transistor N15 are connected to GS, the output end of the Schmitt trigger I8 is connected to the gate of the PMOS transistor P10 and the gate of the NMOS transistor N11, the source of the PMOS transistor P10 is connected to the drain of the PMOS transistor P11, the source of the PMOS transistor P12 is connected to the drain of the PMOS transistor P13, the source of the PMOS transistor P14 is connected to the drain of the PMOS transistor P15, and the drain of the PMOS transistor P10 is connected to the source of the NMOS transistor N11, the source of the NMOS transistor N12, and the input end of the Schmitt trigger I9.The output end of the Schmitt trigger I9 is connected with the gate of the PMOS tube P12 and the gate of the NMOS tube N13, the drain of the PMOS tube P12 is connected with the source of the NMOS tube N13, the source of the NMOS tube N14 and the input end of the Schmitt trigger I10, the output end of the Schmitt trigger I10 is connected with the gate of the PMOS tube P14 and the gate of the NMOS tube N15, the drain of the PMOS tube P14 is connected with the source of the NMOS tube N15, the source of the NMOS tube N16 and the input end of the Schmitt trigger I11, the output end of the Schmitt trigger I11 is connected with the input end of the inverter I12, and the output end of the inverter I12 outputs the power-on reset signal RESET as an output pin. The application provides a power-on reset control method compatible with multiple environments, a thermosensitive comparison circuit, a configuration adjustment circuit and a power-on reset signal generation circuit are included in a power-on reset control circuit constructed by the method, whether the current environment temperature meets the working temperature range of the consumable chip is determined by the thermosensitive comparison circuit, and only when the condition is met, subsequent work is performed; the power-on configuration data of each signal of the consumable chip is stored in the chip in advance, and the power-on configuration data is sent to the configuration adjustment circuit after power-on, the configuration adjustment circuit is used to cooperate with the power-on configuration data to generate a control voltage signal suitable for the consumable chip in real time, and the control voltage signal is sent to the power-on reset signal generation circuit to generate a power-on reset signal; the power-on reset control circuit of the method ensures the compatibility of the circuit by cooperating with the pre-stored power-on configuration data, and the same circuit can be applied to the circuits of different models of consumable chips, thereby effectively reducing the research and development cost. Moreover, the power-on reset control circuit of the method can realize the overheating protection function of various models of chips through the thermosensitive comparison circuit, and does not need to additionally design an overheating protection circuit, thereby further reducing the research and development cost. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 It is a whole module schematic diagram of the multiple compatible power-on reset control circuit in the application; Figure 2 It is an internal structure example of the thermosensitive comparison circuit; Figure 3 It is an internal structure example of the configuration adjustment circuit; Figure 4 It is an internal structure example of the power-on reset signal generation circuit; Figure 5 It is Figure 3 It is a structure schematic diagram of the 3-1 part in the middle; Figure 6 It is Figure 3 It is a structure schematic diagram of the 3-2 part in the middle; Figure 7 It is Figure 4Enlarged structural diagram of section 4-1; Figure 8 for Figure 4 Enlarged structural diagram of section 4-2; Figure 9 This is a Cadence simulation diagram showing a 1.5V power-on voltage. Figure 10 This is a Cadence simulation diagram showing a 2.3V power-on voltage. Figure 11 This is a schematic diagram of a Cadence simulation with a 1.9V power-down voltage. Figure 12 This is a schematic diagram of a Cadence simulation with a 1.5V power-down condition. Figure 13 A Cadence simulation diagram showing the generation of a 4µs reset signal upon power-on. Figure 14 Cadence simulation diagram showing the 58µs reset signal generated upon power-on; Figure 15 This is a schematic diagram of the thermal comparator circuit data simulation. Detailed Implementation

[0009] This application includes a power-on reset control method compatible with multiple environments, which includes the following steps.

[0010] S1: Design a thermistor comparator circuit; The thermal comparator circuit determines whether the consumable chip can work normally based on the current ambient temperature TEMP, and generates an ambient status signal CTRL, which is then sent to subsequent circuits. The ambient status signal includes normal and abnormal states.

[0011] The thermistor comparator circuit includes a comparator circuit and a thermistor modulation voltage module. The thermistor modulation voltage module generates a thermistor modulation voltage V_res based on the ambient temperature TEMP and sends it to the comparator circuit. The comparator circuit compares the thermistor modulation voltage with the reference voltage VREF to obtain the ambient temperature judgment result. Based on the ambient temperature judgment result, a stable ambient status signal CTRL is generated and sent to the configuration and adjustment circuit. The ambient status signal CTRL includes 1 and 0; where 1 indicates normal operation and 0 indicates abnormal state.

[0012] Specific integrated circuit diagrams are as follows Figure 2 As shown, the thermistor comparator circuit includes: resistors R0~R4, comparator COMP1, capacitor C1, NMOS transistor N1, Schmitt triggers I1 and I2, inverter I3 and RS latch; these devices constitute the comparator circuit, thermistor modulation voltage module, shaping circuit and a latch circuit.

[0013] The latch circuit is based on RS latch, which is composed of two groups of AND gates connected to each other.

[0014] The "0" or "1" is obtained by comparing the thermistor modulation voltage with the reference voltage VREF, and then sent to the latch circuit through the shaping circuit to obtain a control signal to control the subsequent configuration trimming circuit. The thermistor R0 is a negative temperature coefficient thermistor (NTC), that is, the higher the temperature, the smaller the resistance. The resistance ratio of the resistance string is about 20:1:1:2 (thermistor data at 25°C) when the temperature is stable at-25°C-40°C, and the resistance ratio of the resistance string is about 2:1:1:2 (thermistor data at 80°C) when the temperature rises.

[0015] Based on the example, the working process of the thermosensitive comparison circuit is as follows. Figure 2

[0016] Before power-on, check each module independently, and there is no high resistance state, undefined state or data stored in the last state, and there is no possible space circuit for power-on moment leakage. At the beginning of power-on moment, the power-on reset module circuit is slower than the other two modules due to the influence of RC, and the thermosensitive comparison circuit will work first. The thermosensitive comparison circuit is powered on because there is no work and no power consumption before the chip, and the temperature is low, so the thermistor resistance is large. Therefore, the input voltage of the comparator thermistor voltage adjustment side is low, about 1 / 6 of VDD. The other end of the comparator is the reference voltage VREF, which is a reference voltage independent of process, power voltage and temperature, about 1.2V. Therefore, the reference voltage at one end of the comparator COMP1 is always greater than the voltage at the thermistor end, and the comparator output gets "1" through the shaping circuit and is sent to the latch circuit.

[0017] The latch circuit Latch is based on the conventional RS latch (two groups of AND gates a1 and a2 connected to each other), and has two input ends, one end connected to the output signal "1" of the shaping circuit, and the other end connected to the signal after digital processing (rectification and filtering) of the reference voltage Vref. Before digital processing of the reference voltage, the signal input is "0", the latch circuit CTRL signal output is "1", and after subsequent digital processing, the signal input is "1". Because the comparator shaping circuit still outputs "1" at this time, the latch circuit completes a state of keeping lock, that is, keeping the last state as "1". In other words, when power-on, as long as the temperature is not high, the thermosensitive comparison circuit module output CTRL signal is always "1" and stable.

[0018] S2: design configuration trimming circuit; The configuration trimming circuit receives the environmental state signal CTRL; ​When the environment state signal CTRL is in a normal state, the configuration trimming circuit reads the configuration data for power-on stored in the consumable chip, configures the corresponding voltage dividing resistor string for the power-on voltage, generates the corresponding control voltage signal CONFIG_V of the consumable chip based on the voltage dividing resistor string, and sends the control voltage signal CONFIG_V to the subsequent circuit; when the environment state signal CTRL is in an abnormal state, the generation of the control voltage signal CONFIG_V is stopped.

[0019] The configuration trimming circuit comprises a MOS switch tube combination, a resistor string and a configuration module. The number of MOS switch tubes included in the MOS switch tube combination is greater than 1, and the number of resistors included in the resistor string is greater than 1. The MOS switch tube combination is connected between the configuration module and the resistor string, the configuration module controls the opening and closing of the MOS tubes in the MOS switch tube combination according to the configuration data for power-on, realizes the adjustment of the resistance value of the resistor string, and then configures the resistor string as a voltage dividing resistor adapted to the power-on voltage, obtains the power-on voltage in proportion, and outputs the control voltage signal CONFIG_V.

[0020] The present application designs a configuration trimming circuit that can be compatible with a larger output voltage range, sets a corresponding configuration file for each type of consumable chip, and uses the configuration file to make the configuration trimming circuit output different control voltage signals CONFIG_V to realize compatibility with different types of consumable chips. The specific configuration file and trimming circuit can be realized based on the existing circuit that can realize the control voltage range, and the present application uses a selector, a compiler and MOS tubes to form a corresponding configuration circuit.

[0021] The configuration module comprises a decoder DEC2 and a selector, and the MOS switch tube combination comprises a PMOS tube combination and an NMOS tube combination; the selector is connected to all PMOS tubes, and the decoder DEC2 is connected to all NMOS tubes.

[0022] The consumable chip sends the P tube configuration configRise for power-on into the selector, the selector controls the opening and closing of each POMS tube according to the configuration data configRise, configures the resistor string as a voltage dividing resistor adapted to the power-on voltage, and then obtains the power-on voltage range in proportion; the consumable chip sends the N tube configuration configFall for power-on into the decoder DEC2, the decoder DEC2 controls the opening and closing of each NOMS tube according to the configuration data configFall, fine tunes within the voltage range adjusted by the PMOS tube, and obtains the control voltage signal CONFIG_V.

[0023] The specific decoder and selector can be realized based on the prior art. The two decoders in the embodiment are both based on a 2-4 decoder with two input ports and four output ports, and the selector is realized by a 4-1 selector with four input ports and one output port. The input of the decoder and the selector is a binary file, and the corresponding configuration data is also stored in the consumable chip in the form of binary data. After power-on, the consumable chip directly sends the binary configuration file into the designated port, and the encoder and the decoder configure the switch of the MOS tube corresponding to the output port according to the configuration file. For example, for the 2-4 decoder, the input port is A and B, and the output port is D0-D3. When the input data is 01, it indicates that the NMOS tube corresponding to D1 needs to be turned on; and when the input configuration data is 11, the NMOS tubes corresponding to D0-D3 are all turned on.

[0024] Based on the examples of Figure 3 、 Figure 5 and Figure 6 , the working content of the configuration adjustment circuit is as follows.

[0025] The d end of the NMOS tube N6 in the configuration adjustment circuit is connected to the upper resistance string, the s end is connected to VSS, and the g end is connected to the control signal CTRL output by the thermal sensitive comparison circuit. When the thermal sensitive comparison circuit outputs "1", the NMOS tube N6 can only be turned on, so that the entire voltage dividing resistance string has a current passing through the ground, and the configuration adjustment circuit can work. On the contrary, if the thermal sensitive comparison circuit outputs "0", the entire voltage dividing resistance string has no current passing through the ground, and the open circuit output is VDD3.3V, and the subsequent power-on reset module will not work.

[0026] The resistance string in the configuration adjustment circuit can modulate the power-on voltage and the power-off voltage, and the adjustment range of the four PMOS tubes is related to the resistance values of R6 and R8. The specific values can be adaptively adjusted according to the preset adjustment range. Figure 3 The resistors R6-R14 in the configuration adjustment circuit are not single resistors but a series of resistors. The number of the corresponding series resistors is represented by segments, and the resistance value after series connection is represented by r. For example, the segments corresponding to R6 is 20, and r is 365.199k. The segments corresponding to R8 is 16, and the corresponding resistance value r is 292.159k.

[0027] As Figure 5As shown, the resistance string R6 corresponds to 3 adjustment PMOS (mp33) tubes P4, P5 and P6 in parallel, the three tubes are the same size, the number m is 1, 1, 1 respectively, and there is a controllable PMOS (mp33) tube P7 for enabling the resistance string, the size of the PMOS tube P7 is consistent with P4, P5 and P6, and the resistance R8 in parallel with the resistance below is the same size, except that the number s in series is 16, the four PMOS tubes are controlled by the RISEOUT generated by the configuration data configRise sent by the signal port CTRL_RISE after the selector, the purpose of this is to adjust as many grades as possible and to maximize the redundancy range. Under the control of the PMOS tube, the upper end of the resistance string output can adjust the power-on voltage and power-off voltage integrally.

[0028] As shown in Figure 6 R9, R11, R12, R13, respectively, segments are 14, 4, 8, 16, each resistance string is connected with an NMOS tube N2~N5 in parallel, the NOMS size is the same, the four resistances in parallel are the same size, the 4 NMOS tubes N2~N5 receive the FALLOUT signal controlled by the 2-4 decoder control DEC2, and the decoder DEC2 controls the switches in the NMOS tubes N2~N5 according to the configuration data configFall, and the voltage is adjusted in a small scale under the control of the PMOS tubes P4, P5, P6 and P7 without changing the whole. After the PMOS tube adjusts the voltage in a larger range, the NMOS tube fine tunes downward in the range, and finally adjusts to reach the adaptive voltage of the consumable chip.

[0029] The decoder control DEC2 and the selector MUX1 control the switches of the 4 NMOS tubes and the 4 PMOS tubes respectively according to the configuration data configFall and configRise, modulate a proportional voltage, and output to the rear power-on reset circuit. The specific configuration data is designed according to the specific adjustment range of the PMOS tube and the NMOS tube in the actual design, and the actual value of the consumable chip.

[0030] The configuration scheme designed in the configuration adjustment circuit in this embodiment is to design multiple large-scale adjustments through 4 PMOS tubes, and then realize relatively small-scale adjustments through NMOS tubes, so as to realize the adjustment of various different power-on voltages. Because the core device NMOS tube N7 in the power-on reset signal generation circuit is selected once, the width-length ratio cannot be changed after the tape-out, and the corresponding threshold voltage Vth cannot be changed, so the resistance string ratio can only be modified to adjust the adaptive voltage node, that is, to modulate the range in which the whole chip can work normally.

[0031] S3: design a power-on reset signal generation circuit; The power-on reset signal generation circuit receives the control voltage signal CONFIG_V sent by the configuration modulation circuit, generates a reset signal RESET using the RC delay principle, and sends the signal to other modules of the consumable chip.

[0032] The power-on reset signal generation circuit designed in the present application mainly includes an RC delay circuit and a Schmitt trigger circuit, and some bias circuits, filter circuits, adjustable delay circuits, and protection circuits are added to the RC delay circuit. The circuit obtains corresponding control and adjustment through the configuration modulation circuit.

[0033] The power-on reset signal generation circuit includes a signal generation resistor, a signal generation capacitor, and a comparison NMOS transistor. The signal generation resistor and the signal generation capacitor form an RC circuit. The CONFIG_V signal output by the configuration modulation circuit is input to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to a resistor, and the source is grounded. When the gate voltage of the comparison NMOS transistor exceeds the threshold voltage Vth of the NMOS transistor, the resistor in the RC circuit charges the capacitor, and outputs the power-on reset signal RESET.

[0034] In addition to the compatibility of the power-on voltage with different models, the power-on delay can also achieve the compatibility of different models of chips. A decoder DEC1 is added to the configuration modulation circuit, and a delay control module is added to the power-on reset signal generation circuit to control the power-on delay. The decoder DEC1 is a 2-4 decoder with enable control.

[0035] The delay control module includes a delay NMOS transistor, and the delay NMOS transistor is connected to the signal generation capacitor. The consumable chip sends the power-on delay time configuration config Delay to the decoder DEC1, the decoder DEC1 generates a CONFIG_D signal according to the configuration data configDelay, and the CONFIG_D signal is sent to the power-on reset signal generation circuit together with the CONFIG_V signal. The switch of the delay NMOS transistor is controlled by the CONFIG_D signal to control the charging time of the capacitor, and the signal delay is realized.

[0036] Based on Figure 4 , Figure 7 and Figure 8For example, in the power-on reset signal generation circuit designed in this application, resistor R15 and capacitors C2~C5 constitute an RC circuit. The drain of the lower left NMOS transistor N7 is connected to resistor R15, the source is grounded, and the gate is connected to the output signal CONFIG_V of the configuration modulation circuit. The configuration tuning circuit outputs a voltage to the gate of NMOS transistor N7. When the output exceeds the threshold voltage Vth, the RC circuit can operate normally. The signal obtained after passing through the RC circuit is shaped using a Schmitt trigger.

[0037] Utilizing the characteristic that capacitors cannot undergo abrupt changes, a delay circuit is used to delay, pull up, and reshape the signal. A more finely detailed and adjustable design is implemented: the four capacitors C2-C5 are connected in parallel series. C2-C5 have the same size, with a unit capacitance of 701.745F, but the number of capacitors in parallel is 2, 8, 16, and 32 respectively, controlled by the four NMOS transistors N10, N12, N14, and N16. The CONFIG_D signal from the DEC1 switch decoder of the four NMOS transistors is used for control. After the delay, the signal is shaped to obtain the output power-on reset signal RESET (marked Rst in the diagram).

[0038] S4: Construct a power-on reset control circuit and integrate the power-on reset control circuit into the consumable chip; The circuit structure designed in this application is as follows: Figure 1 As shown, the power-on reset control circuit includes: a thermistor comparator circuit, a configuration adjustment circuit, and a power-on reset signal generation circuit connected in sequence. The power-on configuration data pre-stored in the consumable chip includes: power-on voltage N-transistor configuration `configFall`, power-on voltage P-transistor configuration `configRise`, and power-on delay time configuration `configDelay`. The ports in the circuit that communicate with the consumable chip correspond to the input ports of the three configuration files: CTRL_FALL corresponds to power-on voltage N-transistor configuration `configFall`, CTRL_RISE corresponds to power-on voltage P-transistor configuration `configRise`, and CTRL_DELAY corresponds to power-on delay time configuration `configDelay`. Figure 1 The TEMP signal refers to the actual ambient temperature, not the specific input signal.

[0039] S5: Before leaving the factory, the power-on configuration data corresponding to the consumable chip is pre-written into the memory of the consumable chip.

[0040] S6: After power-on, the consumable chip reads the power-on configuration data and sends it to the configuration adjustment circuit; The thermal sensitive comparison circuit generates an environment state signal CTRL according to a real-time environment temperature and sends the environment state signal CTRL into a configuration modulation circuit; when the environment state signal CTRL is normal, the configuration modulation circuit generates a control voltage signal CONFIG_V based on the received configuration data for power-on and sends the control voltage signal CONFIG_V into a power-on reset signal generation circuit, the power-on reset signal generation circuit outputs a power-on reset signal RESET according to the received CONFIG_V and sends the power-on reset signal RESET into other modules; when the environment state signal CTRL is abnormal, the power-on reset signal RESET is not generated.

[0041] After the reset signal Rst is obtained, other modules inside the chip start to work correspondingly. If everything is normal, the chip maintains stable work. The thermal sensitive comparison circuit continues to judge whether the environment temperature meets the working range of the consumable chip after the power-on process is completed.

[0042] The power-on reset signal generation circuit works according to the judgment result of the thermal sensitive circuit, if the environment temperature is within the working temperature range of the consumable chip, the RESET signal is continuously maintained to be output, otherwise, when the environment temperature exceeds the working range of the consumable chip, the output of the RESET signal is stopped; If the other modules of the consumable chip can receive the RESET signal, it is judged that the current environment temperature state is within the working range of the consumable chip; if the other modules cannot receive the RESET signal, it is judged that the current environment temperature is not suitable for the work of the consumable chip.

[0043] Specifically, if the chip load is too large, the power consumption is too high, the chip itself is heated, or in the extreme application environment, the peripheral device causes the chip to heat. Then the thermal sensitive comparison circuit starts to work again. The temperature rises, the resistance value of the thermal resistor slowly decreases, the input voltage of the + input end of the comparator COMP1 increases because the resistance value of the thermal resistor above slowly decreases. The reference voltage of the other end (- input end) of the comparator still maintains 1.2V, so when a critical point is reached, the voltage of the + input end is greater than the reference voltage, and the output of the thermal sensitive comparator is inverted to obtain “0” after shaping. The input of one end of the latch circuit is 0, and the other end remains unchanged, so that the stored signal changes, and the overall module CTRL signal output is “0”; at this time, the configuration modulation circuit, nmos is cut off, the voltage resistance string current to ground is closed, and the open circuit causes the whole module to close the function, and the subsequent power-on reset module cannot work normally because the input of the previous stage changes. The reset signal cannot be normally output, and the subsequent other modules of the chip also cannot work normally. The low-power self-protection stage is carried out. In the present application, the overheat protection of the chip is ensured by the thermal sensitive comparison circuit.

[0044] Figures 9-15 , based on Figures 2-4The simulation results of the schematic circuit constructed by the embodiment are executed in the Cadence Virtuoso ADE environment. In the figure, VDD is a power voltage; V_config is a control voltage signal CONFIG_V in the scheme, which is a minimum opening voltage when the threshold voltage Vth of the NMOS tube N7 in the power-on reset signal generation circuit is opened by the output of the configuration modulation circuit; and RST is a power-on reset signal RESET in the application.

[0045] The opening voltage of the conventional power-on reset circuit is usually set to be above 1.8V to prevent accidents when the power voltage is 3.3V. In the scheme of the application, Figure 9 The power-on simulation process for a power voltage of 1.5V is realized based on four PMOS tubes P4-P7 and four NMOS tubes N2-N5. In the figure, the horizontal coordinate is time, the unit is millisecond, and the vertical coordinate is voltage value, the unit is V. Figure 9 In the figure, VDD rises from 0 to 3.3V, the control voltage signal V_config output by the configuration modulation circuit changes from 0 to 1.5242V at the 9th millisecond, and the power-on reset signal RST output by the power-on reset signal generation circuit also changes to 3.3V at about the 27th millisecond. The RST signal keeps the output state between the 27th millisecond and the 50th millisecond. After the 50th millisecond, the power-off state is entered.

[0046] In the embodiment, each gear of the PMOS tube can adjust the power-on voltage by about 0.5V, and each gear of the NMOS tube can adjust the power-on voltage by about 0.1V. If the configuration data of the four PMOS tubes are adjusted to the maximum value on the basis of the configuration data of the four NMOS tubes, the power-on voltage becomes 2.3V. Figure 9 The power-on reset simulation process corresponding to the 2.3V power-on voltage is shown in Figure 10 .

[0047] In order to save energy, the existing printer mostly supports a low-power sleep function. When the printer is not used for a long time, it will automatically enter a low-power sleep state. In this state, most of the modules of the printer do not work, only a small part of the modules can receive external triggering events, and the printer can be awakened at any time. When the normal working state enters the low-power state, there will be a power-off process. The common implementation manner of the power-off process is that the main control chip of the printer controls and adjusts the power voltage VDD to a standby voltage value, such as adjusting VDD from 3.3V to a lower voltage, such as 1.92V. At this time, the signal output by the power-on reset circuit is also automatically adjusted to 1.92V. Figure 11 That is, when the power-off voltage is set to 1.92V, the simulation of the power-off process is performed.

[0048] By controlling the PMOS and NMOS switch, the adjustment of the power-off voltage can also be changed. Figure 11 On the basis of keeping the PMOS unchanged, adjusting the configuration of the NMOS, and making the configuration of the NMOS reach the minimum value, the power-off voltage is adjusted from 1.92v to 1.5097v. Figure 12 The simulation of the power-off process when the power-off voltage is set to 1.5097v. In this embodiment, the resistance string corresponding to the control of the NMOS adjusts each gear to 1.5V, 1.55V, 1.72V, and 1.9V, respectively.

[0049] There is no specific requirement for the time when the reset signal is generated after the power-on of the conventional chip, but some chips need to be reset in a short time after power-on and then initialized. Based on the delay control module designed in the power-on reset signal generation circuit of the present scheme, combined with the decoder DEC1 in the configuration adjustment circuit, the power-on delay time configuration config Delay can be used to adjust the time from power-on to the generation of the reset signal. For example, Figure 11 and 12 In the simulation, when the power-on time of 0-3.3V is set to 20us, the present scheme can adjust the time from power-on to the generation of the reset signal to 4us (such as Figure 13 ) to 58us (such as Figure 14 ). Specifically, the gears that can be adjusted in this embodiment are 4us, 15us, 29us, and 58us.

[0050] As shown in Figure 15 , it is a data comparison diagram of the thermosensitive comparison circuit. In the figure, V_res data is the thermosensitive resistance modulation voltage of the + input end of the comparator COMP1 in the thermosensitive comparison circuit; VREF is the reference voltage input into the - input end of the comparator COMP1, which is constant; out_comp is the output result of the comparator COMP1; and CTRL is the output signal of the thermosensitive comparison circuit. Through simulation, it can be seen that V_res first rises from 0 to 2.3v, then remains constant, and then drops to 0.7v at about 21ms; and the output result out_comp of the comparator COMP1 and the output signal CTRL of the thermosensitive comparison circuit change with the change of V_res.

[0051] After using the technical scheme of the present application, different power-on reset requirements of different types of consumable boxes can be adapted by burning and reading the corresponding power-on configuration data of each type of chip without secondary modification and re-flowing, which greatly reduces the economic cost, time cost, and process deviation risk, meets the characteristics of one chip compatible with multiple, and has the overheat protection characteristic.

Claims

1. A power-on reset control method compatible with multiple environments, characterized in that, It includes the following steps: S1: Design a thermistor comparator circuit; The thermal comparator circuit determines whether the consumable chip can work normally based on the current ambient temperature TEMP, generates an environmental status signal CTRL, and sends the environmental status signal CTRL to the subsequent circuit; the environmental status signal includes: normal state and abnormal state; S2: Design and configure the adjustment circuit; The configuration adjustment circuit receives the environmental status signal CTRL. When the environmental status signal CTRL is in the normal state, the configuration adjustment circuit reads the power-on configuration data stored inside the consumable chip, configures the corresponding voltage divider resistor string for the power-on voltage, generates the control voltage signal CONFIG_V corresponding to the consumable chip based on the voltage divider resistor string, and sends the control voltage signal CONFIG_V into the subsequent circuit. When the environmental status signal CTRL is in an abnormal state, the generation of the control voltage signal CONFIG_V is stopped. S3: Design a power-on reset signal generation circuit; The power-on reset signal generation circuit receives the control voltage signal CONFIG_V sent by the configuration adjustment circuit, generates a reset signal RESET using the RC delay principle, and sends the signal to other modules of the consumable chip. S4: Construct a power-on reset control circuit and integrate the power-on reset control circuit into the consumable chip; The power-on reset control circuit includes: a thermistor comparator circuit, a configuration adjustment circuit, and a power-on reset signal generation circuit connected in sequence. S5: Before leaving the factory, the power-on configuration data corresponding to the consumable chip is pre-written into the memory of the consumable chip; S6: After power-on, the consumable chip reads the power-on configuration data and sends it to the configuration adjustment circuit; The thermal comparator circuit generates an environmental status signal CTRL based on the real-time ambient temperature and sends it to the configuration adjustment circuit. When the environmental status signal CTRL is normal, the configuration adjustment circuit generates a control voltage signal CONFIG_V based on the received power-on configuration data and sends it to the power-on reset signal generation circuit. The power-on reset signal generation circuit outputs a power-on reset signal RESET based on the received CONFIG_V and sends it to other modules. When the environmental status signal CTRL is abnormal, the power-on reset signal RESET is not generated.

2. The power-on reset control method compatible with multiple environments according to claim 1, characterized in that: The thermistor comparison circuit includes a comparator circuit and a thermistor modulation voltage module. The thermistor modulation voltage module generates a thermistor modulation voltage based on the ambient temperature TEMP and sends it to the comparator circuit. The comparator circuit compares the thermistor modulation voltage with the reference voltage VREF to obtain an ambient temperature judgment result. Based on the ambient temperature judgment result, a stable ambient state signal CTRL is generated and sent to the configuration adjustment circuit. The environmental status signal CTRL includes 1 and 0; where 1 indicates normal operation and 0 indicates abnormal operation.

3. The power-on reset control method compatible with multiple environments according to claim 1, characterized in that: The configuration adjustment circuit includes: a combination of MOS switches, a resistor string, and a configuration module; The number of MOS switches included in the MOS switch combination is greater than 1; the number of resistors included in the resistor string is greater than 1; The MOS switch assembly is connected between the configuration module and the resistor string. The configuration module controls the MOS transistors in the MOS switch assembly to turn on and off according to the power-on configuration data, thereby adjusting the resistance value of the resistor string and configuring the resistor string as a voltage divider resistor adapted to the power-on voltage. The power-on voltage is obtained proportionally, and the control voltage signal CONFIG_V is output.

4. The power-on reset control method compatible with multiple environments according to claim 3, characterized in that: The configuration module includes a decoder DEC2 and a selector; the MOS switch combination includes a PMOS switch combination and an NMOS switch combination. The power-on configuration data includes: power-on voltage P-channel configuration configRise and power-on voltage N-channel configuration configFall; The selector is connected to all PMOS transistors, and the decoder DEC2 is connected to all NMOS transistors; The consumable chip sends the power-on voltage P-tube configuration configRise to the selector. The selector controls the switching of each P-tube according to the configuration data configRise, and configures the resistor string as a voltage divider resistor adapted to the power-on voltage, thereby obtaining the power-on voltage range proportionally. The consumable chip sends the power-on voltage N-channel configuration configFall to the decoder DEC2. The decoder DEC2 controls the switching of each N-channel according to the configuration data configFall, and makes fine adjustments within the voltage range adjusted by the PMOS channel to obtain the control voltage signal CONFIG_V.

5. The power-on reset control method compatible with multiple environments according to claim 1, characterized in that: The power-on reset signal generation circuit includes: a resistor for signal generation, a capacitor for signal generation, and an NMOS transistor for comparison; The resistor and capacitor used for signal generation constitute an RC circuit. The CONFIG_V signal output by the configuration adjustment circuit is input to the gate of the NMOS transistor. The drain of the NMOS transistor is connected to a resistor, and the source is grounded. When the gate voltage CONFIG_V of the NMOS transistor exceeds the threshold voltage Vth of the NMOS transistor, the resistor in the RC circuit charges the capacitor and outputs the power-on reset signal RESET.

6. The power-on reset control method compatible with multiple environments according to claim 4, characterized in that: The configuration adjustment circuit also includes: a decoder DEC1; The power-on configuration data also includes: power-on delay time configuration (config Delay); The power-on reset signal generation circuit further includes a delay control module, which includes a delay NMOS transistor connected to the signal generation capacitor. The consumable chip sends the power-on delay time configuration config Delay to the decoder DEC1. The decoder DEC1 controls the switching of the delay NMOS transistor according to the configuration data config Delay, thereby controlling the capacitor charging time and realizing signal delay.

7. The power-on reset control method compatible with multiple environments according to claim 1, characterized in that: After the power-on process is completed, the thermal comparator circuit continuously determines whether the ambient temperature is within the operating range of the consumable chip. The power-on reset signal generation circuit operates based on the judgment result of the thermal circuit. If the ambient temperature is within the operating temperature range of the consumable chip, it will continue to output the RESET signal; otherwise, when the ambient temperature exceeds the operating range of the consumable chip, it will stop outputting the RESET signal. If other modules of the consumable chip can receive the RESET signal, it is determined that the current ambient temperature is within the working range of the consumable chip; if other modules cannot receive the RESET signal, it is determined that the current ambient temperature is not suitable for the consumable chip to work.

8. The power-on reset control method compatible with multiple environments according to claim 1, characterized in that: The thermal comparator circuit includes: resistors R0~R4, comparator COMP1, capacitor C1, NMOS transistor N1, Schmitt triggers I1 and I2, inverter I3, and RS latch; the RS latch is composed of two sets of AND gates connected to each other. The resistor R0 is a thermistor. One end of the resistor R0 is connected to VDD, and the other end is connected to the + input pin of the comparator COMP1 and one end of the resistor R1. The - input pin of the comparator COMP1 is connected to the reference voltage VREF. The output of the comparator COMP1 is connected to the input pin of the Schmitt trigger I1. The output pin of the Schmitt trigger I1 is connected to one input pin vin2 of the RS latch. The other input pin vin1 of the RS latch is the output pin of the Schmitt trigger I2. The input pin of the Schmitt trigger I2 is connected to the positive terminal of the capacitor C1, one end of the resistor R4, and the drain of the NMOS transistor N1. The gate of the NMOS transistor N1 is connected to the reference low voltage VREF, and the source of the NMOS transistor N1 is grounded. The output pin vout of the RS latch is connected to the input pin of the inverter I3. The output pin of the inverter I3 outputs the ambient status signal CTRL. The other end of resistor R1 is connected to one end of resistor R2, the other end of resistor R2 is connected to one end of resistor R3, the other end of resistor R3 is grounded, and the other end of resistor R4 is connected to VDD.

9. The power-on reset control method compatible with multiple environments according to claim 8, characterized in that: The configuration adjustment circuit includes: voltage clamping unit Tielo, selector MUX1, decoders DEC1 and DEC2, voltage clamping unit T1, inverter I4, PMOS transistors P1~P7, NMOS transistors N2~N6, and resistors R5~R14. The voltage clamping unit Tielo is connected between VDD and VSS, and its output pin outputs a low level. The output pin of Tielo is connected to the input pin of inverter I4. The output pin of inverter I4 is connected to the gate of PMOS transistor P1. The source of PMOS transistor P1 is connected to VDD. The drain of PMOS transistor P1 is connected to the source of PMOS transistor P3. The gate of PMOS transistor P3 is connected to VSS. The drain of PMOS transistor P3 is connected to the drain of PMOS transistor P2, the source of PMOS transistor P4, and the P... The sources of PMOS transistors P5, P6, and P2 are connected to VDD. The gate of PMOS transistor P2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to VSS. The gates of PMOS transistors P4, P5, P6, and P7 are all connected to the RISEOUT signal output pin of selector MUX1. The drains of PMOS transistors P4, P5, and P6 are connected to the... One end of resistor R6 and the other end of resistor R6 are connected to the drain of NMOS transistor N2, one end of resistor R9, the source and drain of PMOS transistor P7, both ends of resistor R8, and the output pin to output the configuration control voltage signal CONFIG_V. The gates of NMOS transistors N2, N3, N4, and N5 are all connected to the FALLOUT signal output terminal of decoder DEC2. The source of NMOS transistor N2 is connected to the drain of NMOS transistor N3. The other end of resistor R9, both ends of resistor R10, one end of resistor R11, the source of NMOS transistor N3 connected to the drain of NMOS transistor N4, the other end of resistor R11, one end of resistor R12, the source of NMOS transistor N4 connected to the drain of NMOS transistor N5, the other end of resistor R12, both ends of resistor R13, one end of resistor R14, the source of NMOS transistor N5 connected to the other end of resistor R14, the drain of NMOS transistor N6, the source of NMOS transistor N6 connected to VSS, the gate of NMOS transistor N6 connected to the environmental status signal CTRL output terminal of the thermistor comparator circuit; the DECIN pin of decoder DEC2 serves as the CTRL_DELAY signal input terminal, the DECIN pin of selector MUX1 serves as the CTRL_RISE signal input terminal, the DECIN pin of decoder DEC2 serves as the CTRL_FALL signal input terminal, and the two ends of resistor R7 are interconnected.

10. The power-on reset control method compatible with multiple environments according to claim 9, characterized in that: The power-on reset signal generation circuit includes: NMOS transistors N7~N16, PMOS transistors P8~P16, resistor R15, capacitors C2~C5, Schmitt triggers I5, I8, I9, I10 and I11, and inverters I6, I7 and I12. The gate of NMOS transistor N7 is connected to the CONFIG_V signal output pin of the configuration adjustment circuit. The drain of NMOS transistor N7 is connected to one end of resistor R15 and the input pin of Schmitt trigger I5. The other end of resistor R15 is connected to power supply VS. The source of NMOS transistor N7 is grounded to GS. The output of Schmitt trigger I5 is connected to the input of inverter I6. The output of inverter I6 is connected to the input of inverter I7, the gate of NMOS transistor N9, and the gate of PMOS transistor P8. The output of inverter I7 is connected to the gate of NMOS transistor N8. The drain of NMOS transistor N8 is connected to GS. The source of NMOS transistor N8 is... Connect one end of resistor R16, and connect the other end of resistor R16 to the drain of PMOS transistor P16, the gate of PMOS transistor P16, the gate of PMOS transistor P9, the gate of PMOS transistor P11, the gate of PMOS transistor P13, and the gate of PMOS transistor P15. Connect the source of PMOS transistor P16 to VS. Connect the drain of PMOS transistor P9 to the source of PMOS transistor P8. Connect the source of NMOS transistor N9 to the drain of PMOS transistor P8, the source of NMOS transistor N10, the input of Schmitt trigger I8, the gate of NMOS transistor N10, the gate of NMOS transistor N12, and the gate of NMOS transistor N14. The gate of the NMOS transistor N10 and the gate of the NMOS transistor N16 are connected to the CONFIG_D signal output pin of the configuration adjustment circuit. The positive terminal of capacitor C2 is connected to the drain of the NMOS transistor N10. The positive terminal of capacitor C3 is connected to the drain of the NMOS transistor N12. The positive terminal of capacitor C4 is connected to the drain of the NMOS transistor N14. The positive terminal of capacitor C5 is connected to the drain of the NMOS transistor N16. The negative terminals of capacitors C2, C3, C4, and C5 are connected to GS. The sources of PMOS transistors P9, P11, P13, and P15 are connected to VS. The drains of NMOS transistors N9, N11, N13, and N15 are connected to the gate and gate (GS). The output of Schmitt trigger I8 is connected to the gates of PMOS transistors P10 and N11. The source of PMOS transistor P10 is connected to the drain of PMOS transistor P11. The source of PMOS transistor P12 is connected to the drain of PMOS transistor P13. The source of PMOS transistor P14 is connected to the drain of PMOS transistor P15. The drain of PMOS transistor P10 is connected to the sources of NMOS transistors N11 and N12, and the input of Schmitt trigger I9.The output of Schmitt trigger I9 is ​​connected to the gate of PMOS transistor P12 and the gate of NMOS transistor N13. The drain of PMOS transistor P12 is connected to the source of NMOS transistor N13, the source of NMOS transistor N14, and the input of Schmitt trigger I10. The output of Schmitt trigger I10 is connected to the gate of PMOS transistor P14 and the gate of NMOS transistor N15. The drain of PMOS transistor P14 is connected to the source of NMOS transistor N15, the source of NMOS transistor N16, and the input of Schmitt trigger I11. The output of Schmitt trigger I11 is connected to the input of inverter I12. The output of inverter I12 serves as an output pin, outputting the power-on reset signal RESET.

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